ST72334J/N,

ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
PRODUCT PREVIEW

■ 8K or 16K Program memory

(ROM or Single voltage FLASH)
with read-out protection
■ 256-bytes EEPROM Data memory
■ In-Situ Programming (Remote ISP)
■ Enhanced Reset System
■ Low voltage supply supervisor with
3 programmable levels
■ Low consumption resonator or RC oscillators PSDIP42
and by-pass for external clock source, with safe PSDIP56
control capabilities
■ 4 Power saving modes
■ Standard Interrupt Controller
■ 44 or 32 multifunctional bidirectional I/O lines:
– External interrupt capability (4 vectors)
– 21 or 19 alternate function lines
– 12 or 8 high sink outputs TQFP64 TQFP44
■ Real time base, Beep and Clock-out capabilities 14 x 14 10 x 10
■ Configurable watchdog reset
■ Two 16-bit timers with:
– 2 input captures (only one on timer A)
– 2 output compares (only one on timer A)
– External clock input on timer A ■ 8-bit data manipulation
– PWM and Pulse generator modes ■ 63 basic instructions
■ SPI synchronous serial interface ■ 17 main addressing modes
■ SCI asynchronous serial interface ■ 8 x 8 unsigned multiply instruction
■ 8-bit ADC with 8 input pins ■ True bit manipulation
(6 only on ST72334Jx,
not available on ST72124J2)
■ Full hardware/software development package

Device Summary
Features ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
Program memory - bytes 8K 8K 16K 8K 16K 8K 16K 8K 16K
RAM (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256)
EEPROM - bytes - - - - - 256 256 256 256
Watchdog,
16-bit Tim-
Peripherals Watchdog, 16-bit Timers, SPI, SCI, ADC
ers, SPI,
SCI
Operating Supply 3.0V to 5.5V
CPU Frequency 500 kHz to 8 MHz (with 1 to 16 MHz oscillator)
Operating Temperature -40°C to +85°C (-40°C to +105/125°C optional)
Packages TQFP44 / SDIP42 TQFP64 / SDIP56 TQFP44 / SDIP42 TQFP64 / SDIP56

Rev. 1.0

September 1999 1/125

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
1
 Table of Contents
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 Structural organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.4 In-Situ Programming (ISP) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.3 Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.4 Data EEPROM and Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.5 Data EEPROM Access Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.2 Safe Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 33
4.5 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.2 HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.3 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2.4 SLOW Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 .... 45
6.2 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2.1 I/O Port Interrupt Sensitivity Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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6.2.2 I/O Port Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2.3 Miscellaneous Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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7.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.4 GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.1 Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.2 Reset Sequence Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.3 Multi-Oscillator, Clock Security System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.7 MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.1 PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.1.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.1.2 User-supplied TQFP64 Adaptor / Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.1.3 User-supplied TQFP44 Adaptor / Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.2 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . 121
9.2.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.2.2 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION
New Features available on the ST72C334
■ 8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection

■ New ADC with a better accuracy and conversion time

■ New configurable Clock, Reset and Supply system

■ New power saving mode with real time base: Active Halt

■ Beep capability on PF1

■ New interrupt source: Clock security system (CSS) or Main clock controller (MCC)

ST72C334 I/O Confuguration and Pinout

■ Same pinout as ST72E331

■ PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331)

■ PA3, PB3, PB4 and PF2 have no pull-up configuration (all IOs present on TQFP44)

■ PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and
pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pad without high sink
capabilities. PA4 and PA5 were 20mA true open drain.
New Memory Locations in ST72C334
■ 20h: MISCR register becomes MISCR1 register (naming change)

■ 29h: new control/status register for the MCC module

■ 2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the
WDGSR register keeping the WDOGF flag compatibility.
■ 40h: new MISCR2 register

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ST72334J/N, ST72314J/N, ST72124J

2 GENERAL DESCRIPTION

2.1 INTRODUCTION
The ST72334J/N, ST72314J/N and ST72124J de- The ST72C334J/N, ST72C314J/N and
vices are members of the ST7 microcontroller fam- ST72C124J versions feature single-voltage
ily. They can be grouped as follows: FLASH memory with byte-by-byte In-Situ Pro-
– ST72334J/N devices are designed for mid-range gramming (ISP) capability.
applications with Data EEPROM, ADC, SPI and Under software control, all devices can be placed
SCI interface capabilities. in WAIT, SLOW, ACTIVE-HALT or HALT mode,
– ST72314J/N devices target the same range of reducing power consumption when the application
applications but without Data EEPROM. is in idle or standby state.
– ST72124J devices are for applications that do The enhanced instruction set and addressing
not need Data EEPROM and the ADC peripher- modes of the ST7 offer both power and flexibility to
al. software developers, enabling the design of highly
efficient and compact application code. In addition
All devices are based on a common industry- to standard 8-bit data management, all ST7 micro-
standard 8-bit core, featuring an enhanced instruc- controllers feature true bit manipulation, 8x8 un-
tion set. signed multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram

OSC1 MULTI OSC Internal

+ CLOCK PORT A PA7:0
OSC2 CLOCK FILTER (8 bits for N versions)
(5 bits for J versions)
VSS POWER
VDD PORT B PB7:0
SUPPLY
(8 bits for N versions)
(5 bits for J versions)
PORT D TIMER B
PD7:0
(8 bits for N versions) 8-BIT ADC PORT C PC7:0
(6 bits for J versions) (8 bits)
ADDRESS AND DATA BUS

VSSA SPI

VDDA
PORT F
RESET PF7,6,4,2:0
CONTROL (6 bits)
VPP/TES T AND LVD TIMER A

8-BIT CORE
PORT E
ALU
PE7:0
(6 bits for N versions)
SCI (2 bits for J versions)
PROGRAM
MEMORY
(8 or 16K Bytes)
WATCH DOG

Data-EEPROM RAM
(256 Bytes) (384 or 512 Bytes)

6/125

5
 ST72334J/N, ST72314J/N, ST72124J

2.2 PIN DESCRIPTION

Figure 2. 64-Pin TQFP Package Pinout (N versions)

PE0 / TDO
PE1 / RDI

PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
ISPSEL
RESET
VDD_2

VSS_2
OSC1
OSC2
NC
NC

NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
(HS) PE4 1 48 VSS_1
(HS) PE5 2 47 VDD_1
(HS) PE6 3 46 PA3
(HS) PE7 4 45 PA2
EI0
PB0 5 44 PA1
PB1 6 43 PA0
PB2 7 EI2 42 PC7 / SS
PB3 8 41 PC6 / SCK / ISPCLK
PB4 9 40 PC5 / MOSI
PB5 10 39 PC4 / MISO / ISPDATA
PB6 11 EI3 38 PC3 (HS) / ICAP1_B
PB7 12 37 PC2 (HS) / ICAP2_B
AIN0 / PD0 13 36 PC1 / OCMP1_B
AIN1 / PD1 14 35 PC0 / OCMP2_B
AIN2 / PD2 15 EI1 34 VSS_0
AIN3 / PD3 16 33 VDD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_3
VSSA
VDDA
AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7

VSS_3
MCO / PF0
BEEP / PF1
PF2
NC
OCMP1_A / PF4
NC
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7

7/125
6
ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont’d)

Figure 3. 56-Pin SDIP Package Pinout (N versions)

PB4 1 56 PB3
PB5 2 55 PB2
EI3 EI2
PB6 3 54 PB1
PB7 4 53 PB0
AIN0 / PD0 5 52 PE7 (HS)
AIN1 / PD1 6 51 PE6 (HS)
AIN2 / PD2 7 50 PE5 (HS)
AIN3 / PD3 8 49 PE4 (HS)
AIN4 / PD4 9 48 PE1 / RDI
AIN5 / PD5 10 47 PE0 / TDO
AIN6 / PD6 11 46 VDD_2
AIN7 / PD7 12 45 OSC1
VDDA 13 44 OSC2
VSSA 14 43 VSS_2
MCO / PF0 15 42 RESET
BEEP / PF1 16 EI1 41 ISPSEL
PF2 17 40 PA7 (HS)
OCMP1_A / PF4 18 39 PA6 (HS)I
ICAP1_A / (HS) PF6 19 38 PA5 (HS)
EXTCLK_A / (HS) PF7 20 37 PA4 (HS)
VDD_0 21 36 VSS_1
VSS_0 22 35 VDD_1
OCMP2_B / PC0 23 34 PA3
OCMP1_B / PC1 24 33 PA2
EI0
ICAP2_B / (HS) PC2 25 32 PA1
ICAP1_B / (HS) PC3 26 31 PA0
ISPDATA/ MISO / PC4 27 30 PC7 / SS
MOSI / PC5 28 29 PC6 / SCK / ISPCLK

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 ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont’d)

Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)

PE0 / TDO

PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
ISPSEL
RESET
VDD_2

VSS_2
OSC1
OSC2
44 43 42 41 40 39 38 37 36 35 34
PE1 / RDI 1 33 VSS_1
PB0 2 32 VDD_1
PB1 3 EI0 31 PA3
EI2
PB2 4 30 PC7 / SS
PB3 5 29 PC6 / SCK / ISPCLK
PB4 6 EI3 28 PC5 / MOSI
AIN0 / PD0 7 27 PC4 / MISO / ISPDATA
AIN1 / PD1 8 26 PC3 (HS) / ICAP1_B
AIN2 / PD2 9 25 PC2 (HS) / ICAP2_B
AIN3 / PD3 10 EI1 24 PC1 / OCMP1_B
AIN4 / PD4 11 23 PC0 / OCMP2_B
12 13 14 15 16 17 18 19 20 21 22
VSSA
VDDA
AIN5 / PD5

VSS_0
MCO / PF0
BEEP / PF1
PF2
OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
VDD_0

PB4 1 EI3 42 PB3

AIN0 / PD0 2 41 PB2
AIN1 / PD1 3 EI2 PB1
40
AIN2 / PD2 4 39 PB0
AIN3 / PD3 5 38 PE1 / RDI
AIN4 / PD4 6 37 PE0 / TDO
AIN5 / PD5 7 36 VDD_2
VDDA 8 35 OSC1
VSSA 9 34 OSC2
MCO / PF0 10 33 VSS_2
BEEP / PF1 11 EI1 32 RESET
PF2 12 31 ISPSEL
OCMP1_A / PF4 13 30 PA7 (HS)
ICAP1_A / (HS) PF6 14 29 PA6 (HS)
EXTCLK_A / (HS) PF7 15 28 PA5 (HS)
OCMP2_B / PC0 16 27 PA4 (HS)
OCMP1_B / PC1 17 26 VSS_1
ICAP2_B/ (HS) PC2 18 25 VDD_1
ICAP1_B / (HS) PC3 19 EI0 24 PA3
ISPDATA / MISO / PC4 20 23 PC7 / SS
MOSI / PC5 21 22 PC6 / SCK / ISPCLK

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ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = high sink (on N-buffer only),
Port configuration capabilities:
– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output: OD = open drain, T = true open drain, PP = push-pull
Note: the Reset configuration of each pin is shown in bold.
Table 1. Device Pin Description
Pin n° Level Port Main
Type

Output function
TQFP64

Input
Output
SDIP56

SDIP42

Pin Name Alternate function

QFP44

Input

(after
float
wpu

ana

OD

PP
int

reset)
1 49 PE4 (HS) I/O CT HS X X X X Port E4
2 50 PE5 (HS) I/O CT HS X X X X Port E5
3 51 PE6 (HS) I/O CT HS X X X X Port E6
4 52 PE7 (HS) I/O CT HS X X X X Port E7
5 53 2 39 PB0 I/O CT X EI2 X X Port B0
6 54 3 40 PB1 I/O CT X EI2 X X Port B1
7 55 4 41 PB2 I/O CT X EI2 X X Port B2
8 56 5 42 PB3 I/O CT X EI2 X X Port B3
9 1 6 1 PB4 I/O CT X EI3 X X Port B4
10 2 PB5 I/O CT X EI3 X X Port B5
11 3 PB6 I/O CT X EI3 X X Port B6
12 4 PB7 I/O CT X EI3 X X Port B7
13 5 7 2 PD0/AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0
14 6 8 3 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1
15 7 9 4 PD2/AIN2 I/O CT X X X X X Port D2 ADC Analog Input 2
16 8 10 5 PD3/AIN3 I/O CT X X X X X Port D3 ADC Analog Input 3
17 9 11 6 PD4/AIN4 I/O CT X X X X X Port D4 ADC Analog Input 4
18 10 12 7 PD5/AIN5 I/O CT X X X X X Port D5 ADC Analog Input 5
19 11 PD6/AIN6 I/O CT X X X X X Port D6 ADC Analog Input 6
20 12 PD7/AIN7 I/O CT X X X X X Port D7 ADC Analog Input 7
21 13 13 8 VDDA S Analog Power Supply Voltage
22 14 14 9 VSSA S Analog Ground Voltage
23 VDD_3 S Digital Main Supply Voltage
24 VSS_3 S Digital Ground Voltage
25 15 15 10 PF0/MCO I/O CT X EI1 X X Port F0 Main clock output (fOSC/2)
26 16 16 11 PF1/BEEP I/O CT X EI1 X X Port F1 Beep signal output
27 17 17 12 PF2 I/O CT X EI1 X X Port F2
28 NC Not Connected

10/125
 ST72334J/N, ST72314J/N, ST72124J

Pin n° Level Port Main

Type
Output function
TQFP64

Input

Output
SDIP56

SDIP42

Pin Name Alternate function

QFP44

Input
(after

float
wpu

ana

OD

PP
int
reset)
29 18 18 13 PF4/OCMP1_A I/O CT X X X X Port F4 Timer A Output Compare 1
30 NC Not Connected
31 19 19 14 PF6 (HS)/ICAP1_A I/O CT HS X X X X Port F6 Timer A Input Capture 1
32 20 20 15 PF7 (HS)/EXTCLK_A I/O CT HS X X X X Port F7 Timer A External Clock Source
33 21 21 VDD_0 S Digital Main Supply Voltage
34 22 22 VSS_0 S Digital Ground Voltage
35 23 23 16 PC0/OCMP2_B I/O CT X X X X Port C0 Timer B Output Compare 2
36 24 24 17 PC1/OCMP1_B I/O CT X X X X Port C1 Timer B Output Compare 1
37 25 25 18 PC2 (HS)/ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2
38 26 26 19 PC3 (HS)/ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1
39 27 27 20 PC4/MISO I/O CT X X X X Port C4 SPI Master In / Slave Out Data
40 28 28 21 PC5/MOSI I/O CT X X X X Port C5 SPI Master Out / Slave In Data
41 29 29 22 PC6/SCK I/O CT X X X X Port C6 SPI Serial Clock
42 30 30 23 PC7/SS I/O CT X X X X Port C7 SPI Slave Select (active low)
43 31 PA0 I/O CT X EI0 X X Port A0
44 32 PA1 I/O CT X EI0 X X Port A1
45 33 PA2 I/O CT X EI0 X X Port A2
46 34 31 24 PA3 I/O CT X EI0 X X Port A3
47 35 32 25 VDD_1 S Digital Main Supply Voltage
48 36 33 26 VSS_1 S Digital Ground Voltage
49 37 34 27 PA4 (HS) I/O CT HS X X X X Port A4
50 38 35 28 PA5 (HS) I/O CT HS X X X X Port A5
51 39 36 29 PA6 (HS) I/O CT HS X T Port A6
52 40 37 30 PA7 (HS) I/O CT HS X T Port A7
Must be tied low in user mode. In pro-
gramming mode when available, this pin
53 41 38 31 ISPSEL I
acts as In-Situ Programming mode se-
lection.
Top priority non maskable interrupt (ac-
54 42 39 32 RESET I/O C X X
tive low)
55 NC
Not Connected
56 NC
57 43 40 33 VSS_3 S Digital Ground Voltage
58 44 41 34 OSC2 These pins connect a parallel-resonant
crystal or an external clock source to the
59 45 42 35 OSC1 on-chip main oscillator.
60 46 43 36 VDD_3 S Digital Main Supply Voltage
61 47 44 37 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out
62 48 1 38 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In
63 NC
Not Connected
64 NC

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ST72334J/N, ST72314J/N, ST72124J

2.3 REGISTER & MEMORY MAP

As shown in the Figure 5, the MCU is capable of 8 Kbytes of user program memory. The RAM
addressing 64K bytes of memories and I/O regis- space includes up to 256 bytes for the stack from
ters. 0100h to 01FFh.
The available memory locations consist of 128 The highest address bytes contain the user reset
bytes of register locations, 384 or 512 bytes of and interrupt vectors.
RAM, up to 256 bytes of data EEPROM and 4 or
Figure 5. Memory Map

0000h 0080h
HW Registers Short Addressing
(see Table 2) RAM (zero page)
007Fh 00FFh
0080h 0100h 256 Bytes Stack or
384 Bytes RAM
01FFh 01FFh
16-bit Addressing RAM

512 Bytes RAM

027Fh
0200h / 0280h
Reserved 0080h
Short Addressing
0BFFh
00FFh RAM (zero page)
0C00h
256 Bytes Data EEPROM 0100h
0CFFh
0D00h
256 Bytes Stack or
Reserved
BFFFh 16-bit Addressing RAM
C000h 01FFh
16K Bytes
E000h 8K Bytes Program 0200h 16-bit Addressing
Program Memory RAM
027Fh
FFDFh Memory
FFE0h
Interrupt & Reset Vectors
(see Table 6 page 37)
FFFFh

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 ST72334J/N, ST72314J/N, ST72124J

REGISTER & MEMORY MAP (Cont’d)

Table 2. Hardware Register Map

Register Reset
Address Block Register Name Remarks
Label Status

0000h PADR Port A Data Register 00h R/W

0001h Port A PADDR Port A Data Direction Register 00h R/W
0002h PAOR Port A Option Register 00h R/W 1)

0003h Reserved Area (1 Byte)

0004h PCDR Port C Data Register 00h R/W

0005h Port C PCDDR Port C Data Direction Register 00h R/W
0006h PCOR Port C Option Register 00h R/W

0007h Reserved Area (1 Byte)

0008h PBDR Port B Data Register 00h R/W

0009h Port B PBDDR Port B Data Direction Register 00h R/W
000Ah PBOR Port B Option Register 00h R/W 1)

000Bh Reserved Area (1 Byte)

000Ch PEDR Port E Data Register 00h R/W

000Dh Port E PEDDR Port E Data Direction Register 00h R/W
000Eh PEOR Port E Option Register 00h R/W 1)

000Fh Reserved Area (1 Byte)

0010h PDDR Port D Data Register 00h R/W

0011h Port D PDDDR Port D Data Direction Register 00h R/W
0012h PDOR Port D Option Register 00h R/W 1)

0013h Reserved Area (1 Byte)

0014h PFDR Port F Data Register 00h R/W

0015h Port F PFDDR Port F Data Direction Register 00h R/W
0016h PFOR Port F Option Register 00h R/W

0017h
to Reserved Area (9 Bytes)
001Fh

0020h MISCR1 Miscellaneous Register 1 00h R/W

0021h SPIDR SPI Data I/O Register xxh R/W

0022h SPI SPICR SPI Control Register 0xh R/W
0023h SPISR SPI Status Register 00h Read Only

0024h
to Reserved Area (5 Bytes)
0028h

0029h MCC MCCSR Main Clock Control / Status Register 01h R/W

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ST72334J/N, ST72314J/N, ST72124J

Register Reset
Address Block Register Name Remarks
Label Status

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh CRSR Clock, Reset, Supply Control / Status Register 00h R/W

002Ch Data-EEPROM EECSR Data-EEPROM Control/Status Register 00h R/W

002Dh
Reserved Area (4 Bytes)
0030h

0031h TACR2 Timer A Control Register 2 00h R/W

0032h TACR1 Timer A Control Register 1 00h R/W
0033h TASR Timer A Status Register xxh Read Only
0034h TAIC1HR Timer A Input Capture 1 High Register xxh Read Only
0035h TAIC1LR Timer A Input Capture 1 Low Register xxh Read Only
0036h TAOC1HR Timer A Output Compare 1 High Register 80h R/W
0037h TAOC1LR Timer A Output Compare 1 Low Register 00h R/W
0038h TIMER A TACHR Timer A Counter High Register FFh Read Only
0039h TACLR Timer A Counter Low Register FCh Read Only
003Ah TAACHR Timer A Alternate Counter High Register FFh Read Only
003Bh TAACLR Timer A Alternate Counter Low Register FCh Read Only
003Ch TAIC2HR Timer A Input Capture 2 High Register xxh Read Only 2)
003Dh TAIC2LR Timer A Input Capture 2 Low Register xxh Read Only 2)
003Eh TAOC2HR Timer A Output Compare 2 High Register 80h R/W 2)
003Fh TAOC2LR Timer A Output Compare 2 Low Register 00h R/W 2)

0040h MISCR2 Miscellaneous Register 2 00h R/W

0041h TBCR2 Timer B Control Register 2 00h R/W

0042h TBCR1 Timer B Control Register 1 00h R/W
0043h TBSR Timer B Status Register xxh Read Only
0044h TBIC1HR Timer B Input Capture 1 High Register xxh Read Only
0045h TBIC1LR Timer B Input Capture 1 Low Register xxh Read Only
0046h TBOC1HR Timer B Output Compare 1 High Register 80h R/W
0047h TBOC1LR Timer B Output Compare 1 Low Register 00h R/W
0048h TIMER B TBCHR Timer B Counter High Register FFh Read Only
0049h TBCLR Timer B Counter Low Register FCh Read Only
004Ah TBACHR Timer B Alternate Counter High Register FFh Read Only
004Bh TBACLR Timer B Alternate Counter Low Register FCh Read Only
004Ch TBIC2HR Timer B Input Capture 2 High Register xxh Read Only
004Dh TBIC2LR Timer B Input Capture 2 Low Register xxh Read Only
004Eh TBOC2HR Timer B Output Compare 2 High Register 80h R/W
004Fh TBOC2LR Timer B Output Compare 2 Low Register 00h R/W

0050h SCISR SCI Status Register C0h Read Only

0051h SCIDR SCI Data Register xxh R/W
0052h SCIBRR SCI Baud Rate Register 00xx xxxx R/W
0053h SCICR1 SCI Control Register 1 xxh R/W
SCI
0054h SCICR2 SCI Control Register 2 00h R/W
0055h SCIERPR SCI Extended Receive Prescaler Register 00h R/W
0056h Reserved area ---
0057h SCIETPR SCI Extended Transmit Prescaler Register 00h R/W

14/125
 ST72334J/N, ST72314J/N, ST72124J

Register Reset
Address Block Register Name Remarks
Label Status

0058h
Reserved Area (24 Bytes)
006Fh

0070h ADCDR Data Register xxh Read Only

ADC
0071h ADCCSR Control/Status Register 00h R/W

0072h
to Reserved Area (14 Bytes)
007Fh

Notes:
1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
2) External pin not available.
3) Not used in versions without Low Voltage Detector Reset.

15/125
ST72334J/N, ST72314J/N, ST72124J

2.4 FLASH PROGRAM MEMORY

2.4.1 Introduction This mode needs five signals (plus the VDD signal
Flash devices have a single voltage non-volatile if necessary) to be connected to the programming
FLASH memory that may be programmed in-situ tool. This signals are:
(or plugged in a programming tool) on a byte-by- – RESET: device reset
byte basis. – VSS: device ground power supply
2.4.2 Main features – ISPCLK: ISP output serial clock pin
■ Remote In-Situ Programming (ISP) mode
– ISPDATA: ISP input serial data pin
– ISPSEL: Remote ISP mode selection. This pin
■ Up to 16 bytes programmed in the same cycle
must be connected to VSS on the application
■ MTP memory (Multiple Time Programmable) board
■ Read-out memory protection against piracy If any of these pins are used for other purposes on
the application, a serial resistor has to be imple-
2.4.3 Structural organisation mented to avoid a conflict if the other device forces
The FLASH program memory is organised in a the signal level.
single 8-bit wide memory block which can be used Figure 6 shows a typical hardware interface to a
for storing both code and data constants. standard ST7 programming tool. For more details
The FLASH program memory is mapped in the up- on the pin locations, refer to the device pinout de-
per part of the ST7 addressing space (F000h- scription.
FFFFh) and includes the reset and interrupt user Figure 6. Typical Remote ISP Interface
vector area .
HE10 CONNECTOR TYPE
2.4.4 In-Situ Programming (ISP) mode TO PROGRAMMING TOOL
XTAL
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up-
1
dated using a standard ST7 programming tools af- CL0 CL1
ter the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area im-
pact. ISPSEL
VDD
OSC2

OSC1

10kΩ
An example Remote ISP hardware interface to the
standard ST7 programming tool is described be- VSS
low. For more details on ISP programming, refer to
the ST7 Programming Specification. RESET

ISPCLK
Remote ISP Overview ST7
The Remote ISP mode is initiated by a specific se- ISPDATA
quence on the dedicated ISPSEL pin.
4.7kΩ
The Remote ISP is performed in three steps:
– Selection of the RAM execution mode
APPLICATION
– Download of Remote ISP code in RAM
– Execution of Remote ISP code in RAM to pro- 2.5 Program Memory Read-out Protection
gram the user program into the FLASH
The read-out protection is enabled through an op-
Remote ISP hardware configuration tion bit.
In Remote ISP mode, the ST7 has to be supplied For FLASH devices, when this option is selected,
with power (VDD and VSS) and a clock signal (os- the program and data stored in the FLASH memo-
cillator and application crystal circuit for example). ry are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
first automatically erased.
1

16/125
 ST72334J/N, ST72314J/N, ST72124J

2.6 DATA EEPROM

2.6.1 Introduction 2.6.2 Main Features

The Electrically Erasable Programmable Read ■ Up to 16 Bytes programmed in the same cycle
Only Memory can be used as a non volatile back- ■ EEPROM mono-voltage (charge pump)
up for storing data. Using the EEPROM requires a ■ Chained erase and programming cycles
basic access protocol described in this chapter.
■ Internal control of the global programming cycle
duration
■ End of programming cycle interrupt flag

■ WAIT mode management

Figure 7. EEPROM Block Diagram

FALLING
EEPROM INTERRUPT EDGE
DETECTOR

HIGH VOLTAGE
PUMP

RESERVED EEPROM
EECSR
0 0 0 0 0 IE LAT PGM

EEPROM
ADDRESS 4 ROW
MEMORY MATRIX
DECODER DECODER
(1 ROW = 16 x 8 BITS)

128 128

4 DATA 16 x 8 BITS
MULTIPLEXER DATA LATCHES

ADDRESS BUS DATA BUS

17/125
ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont’d)

2.6.3 Memory Access When PGM bit is set by the software, all the previ-
The Data EEPROM memory read/write access ous bytes written in the data latches (up to 16) are
modes are controlled by the LAT bit of the EEP- programmed in the EEPROM cells. The effective
ROM Control/Status register (EECSR). The flow- high address (row) is determined by the last EEP-
chart in Figure 8 describes these different memory ROM write sequence. To avoid wrong program-
access modes. ming, the user must take care that all the bytes
written between two programming sequences
Read Operation (LAT=0) have the same high address: only the four Least
The EEPROM can be read as a normal ROM loca- Significant Bits of the address can change.
tion when the LAT bit of the EECSR register is At the end of the programming cycle, the PGM and
cleared. In a read cycle, the byte to be accessed is LAT bits are cleared simultaneously, and an inter-
put on the data bus in less than 1 CPU clock cycle. rupt is generated if the IE bit is set. The Data EEP-
This means that reading data from EEPROM ROM interrupt request is cleared by hardware
takes the same time as reading data from when the Data EEPROM interrupt vector is
EPROM, but this memory cannot be used to exe- fetched.
cute machine code. Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
Write Operation (LAT=1)
will over-program the memory (logical AND be-
To access the write mode, the LAT bit has to be tween the two write access data result) because
set by software (the PGM bit remains cleared). the data latches are only cleared at the end of the
When a write access to the EEPROM area occurs, programming cycle and by the falling edge of LAT
the value is latched inside the 16 data latches ac- bit.
cording to its address. It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 8. Data EEPROM Programming Flowchart

READ MODE WRITE MODE

LAT=0 LAT=1
PGM=0 PGM=0

WRITE UP TO 16 BYTES
READ BYTES
IN EEPROM AREA
IN EEPROM AREA
(with the same 12 MSB of the address)

START PROGRAMMING CYCLE

LAT=1
PGM=1 (set by software)

INTERRUPT GENERATION
IF IE=1 0 1
LAT

CLEARED BY HARDWARE

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 ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont’d)

2.6.4 Data EEPROM and Power Saving Modes 2.6.5 Data EEPROM Access Error Handling
Wait mode If a read access occurs while LAT=1, then the data
bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol- If a write access occurs while LAT=0, then the
ler. The DATA EEPROM will immediately enter data on the bus will not be latched.
this mode if there is no programming in progress, If a programming cycle is interrupted (by software/
otherwise the DATA EEPROM will finish the cycle RESET action), the memory data will not be guar-
and then enter WAIT mode. anteed.
Halt mode
The DATA EEPROM immediatly enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.

Figure 9. Data EEPROM Programming Cycle

READ OPERATION NOT POSSIBLE READ OPERATION POSSIBLE

INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE WRITE CYCLE

WRITE OF
DATA LATCHES
t PROG

LAT

PGM

EEPROM INTERRUPT

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ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont’d)

2.6.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 IE LAT PGM

Bit 7:3 = Reserved, forced by hardware to 0.

Bit 2 = IE Interrupt enable

This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when the software enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled

Bit 1 = LAT Latch Access Transfer

This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode

Bit 0 = PGM Programming control and status

This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is clearedby hardware and an interrupt is generated
if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress

Note: if the PGM bit is cleared during the program-

ming cycle, the memory data is not guaranteed.

Table 3. DATA EEPROM Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

EECSR IE RWM PGM

002Ch
Reset Value 0 0 0 0 0 0 0 0

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3 CENTRAL PROCESSING UNIT

3.1 INTRODUCTION Accumulator (A)

This CPU has a full 8-bit architecture and contains The Accumulator is an 8-bit general purpose reg-
six internal registers allowing efficient 8-bit data ister used to hold operands and the results of the
manipulation. arithmetic and logic calculations and to manipulate
data.
3.2 MAIN FEATURES Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
■ 63 basic instructions are used to create either effective addresses or
■ Fast 8-bit by 8-bit multiply temporary storage areas for data manipulation.
■ 17 main addressing modes (The Cross-Assembler generates a precede in-
■ Two 8-bit index registers struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
■ Low power modes matic procedures (not pushed to and popped from
■ Maskable hardware interrupts the stack).
■ Non-maskable software interrupt Program Counter (PC)
The program counter is a 16-bit register containing
3.3 CPU REGISTERS the address of the next instruction to be executed
The 6 CPU registers shown in Figure 10 are not by the CPU. It is made of two 8-bit registers PCL
present in the memory mapping and are accessed (Program Counter Low which is the LSB) and PCH
by specific instructions. (Program Counter High which is the MSB).

Figure 10. CPU Registers

7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh

15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 1 H I N Z C
CONDITIO N CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X

15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value

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CENTRAL PROCESSING UNIT (Cont’d)

CONDITION CODE REGISTER (CC) Bit 2 = N Negative.
Read/Write This bit is set and cleared by hardware. It is repre-
Reset Value: 111x1xxx sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
7 0 bit of the result.
0: The result of the last operation is positive or null.
1 1 1 H I N Z C 1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
The 8-bit Condition Code register contains the in- This bit is accessed by the JRMI and JRPL instruc-
terrupt mask and four flags representative of the tions.
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions. Bit 1 = Z Zero.
These bits can be individually tested and/or con- This bit is set and cleared by hardware. This bit in-
trolled by specific instructions. dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
Bit 4 = H Half carry. zero.
This bit is set by hardware when a carry occurs be- 1: The result of the last operation is zero.
tween bits 3 and 4 of the ALU during an ADD or This bit is accessed by the JREQ and JRNE test
ADC instruction. It is reset by hardware during the instructions.
same instructions.
0: No half carry has occurred.
1: A half carry has occurred. Bit 0 = C Carry/borrow.
This bit is tested using the JRH or JRNH instruc- This bit is set and cleared by hardware and soft-
tion. The H bit is useful in BCD arithmetic subrou- ware. It indicates an overflow or an underflow has
tines. occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
Bit 3 = I Interrupt mask.
This bit is driven by the SCF and RCF instructions
This bit is set by hardware when entering in inter- and tested by the JRC and JRNC instructions. It is
rupt or by software to disable all interrupts except also affected by the “bit test and branch”, shift and
the TRAP software interrupt. This bit is cleared by rotate instructions.
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.

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CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP) The least significant byte of the Stack Pointer
Read/Write (called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
15 8 Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
0 0 0 0 0 0 0 1 stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
7 0 flow.
The stack is used to save the return address dur-
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
The Stack Pointer is a 16-bit register which is al- the stack by means of the PUSH and POP instruc-
ways pointing to the next free location in the stack. tions. In the case of an interrupt, the PCL is stored
It is then decremented after data has been pushed at the first location pointed to by the SP. Then the
onto the stack and incremented before data is other registers are stored in the next locations as
popped from the stack (see Figure 11). shown in Figure 11.
Since the stack is 256 bytes deep, the 8th most – When an interrupt is received, the SP is decre-
significant bits are forced by hardware. Following mented and the context is pushed on the stack.
an MCU Reset, or after a Reset Stack Pointer in- – On return from interrupt, the SP is incremented
struction (RSP), the Stack Pointer contains its re- and the context is popped from the stack.
set value (the SP7 to SP0 bits are set) which is the A subroutine call occupies two locations and an in-
stack higher address. terrupt five locations in the stack area.
Figure 11. Stack Manipulation Example

CALL Interrupt PUSH Y POP Y IRET RET

Subroutine Event or RSP

@ 0100h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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4 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72334J/N, ST72314J/N and ST72124J mi- ■ Reset Sequence Manager (RSM)
crocontrollers include a range of utility features for ■ Multi-Oscillator (MO)
securing the application in critical situations (for
example in case of a power brown-out), and re- – 4 Crystal/Ceramic resonator oscillators
ducing the number of external components. An – 1 External RC oscillator
overview is shown in Figure 12. – 1 Internal RC oscillator
■ Clock Security System (CSS)
Main Features
– Clock Filter
■ Supply Manager with Main supply Low voltage
detection (LVD) – Backup Safe Oscillator

Figure 12. Clock, Reset and Supply Block Diagram

MCO

CLOCK SECUR ITY SYSTE M

(CSS)

OSC2 MULTI- fOSC MAIN CLOCK fCPU

CLOCK SAFE
OSCILLATOR CONTROLLER
OSC1 FILTER OSC
(MO) (MCC)

RESET SEQUEN CE
RESET MANAGER FROM
WATCH DOG
(RSM)
PERIP HERAL

VDD LOW VOLTAGE

LVD CSS WDG
DETECTO R
VSS (LVD) CRSR 0 0 0 RF 0 IE D RF

CSS INTER RUPT

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4.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management In these conditions, secure operation is always en-
features in the application, the Low Voltage Detec- sured for the application without the need for ex-
tor function (LVD) generates a static reset when ternal reset hardware.
the VDD supply voltage is below a VLVDf reference During a Low Voltage Detector Reset, the RESET
value. This means that it secures the power-up as pin is held low, thus permitting the MCU to reset
well as the power-down keeping the ST7 in reset. other devices.
The V LVDf reference value for a voltage drop is Notes:
lower than the VLVDr reference value for power-on 1) the LVD allows the device to be used without any exter-
in order to avoid a parasitic reset when the MCU nal RESET circuitry.
starts running and sinks current on the supply 2) three different reference levels are selectable through
(hysteresis). the OPTION BYTE according to the application require-
ment.
The LVD Reset circuitry generates a reset when
VDD is below: LVD application note
– VLVDr when VDD is rising Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
– VLVDf when VDD is falling
register.
The LVD function is illustrated in the Figure 13.
This bit is set by hardware when a LVD reset is
Provided the minimum VDD value (guaranteed for generated and cleared by software (writing zero).
the oscillator frequency) is below VLVDf, the MCU
can only be in two modes:
– under full software control
– in static safe reset
Figure 13. Low Voltage Detector vs Reset

VDD

HYSTE RESIS
VLVDhyst
VLVDr
VLVDf

RESET

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4.2 RESET SEQUENCE MANAGER (RSM)

The reset sequence manager includes three RE- The 4096 CPU clock cycle delay allows the oscil-
SET sources as shown in Figure 15: lator to stabilise and ensures that recovery has
■ EXTERNAL RESET SOURCE pulse taken place from the Reset state.
■ Internal LVD RESET (Low Voltage Detection) The RESET vector fetch phase duration is 2 clock
■ Internal WATCHDOG RESET
cycles.
These sources act on the RESET PIN and it is al- Figure 14. RESET Sequence Phases
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map. RESET
The basic RESET sequence consists of 3 phases INTERNAL RESET FETCH
DELAY
as shown in Figure 14: 4096 CLOCK CYCLES VECTOR

■ Delay depending on the RESET source

■ 4096 CPU clock cycle delay

■ RESET vector fetch

Figure 15. Reset Block Diagram

VDD INTERNAL
f CPU RESET

COUNTER
RON

RESET

WATCHDOG RESET

LVD RESET

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RESET SEQUENCE MANAGER (Cont’d)

External RESET pin A RESET signal originating from an external
The RESET pin is both an input and an open-drain source must have a duration of at least tPULSE in
output with integrated RON weak pull-up resistor. order to be recognized. Two RESET sequences
This pull-up has no fixed value but varies in ac- can be associated with this RESET source as
cordance with the input voltage. It can be pulled shown in Figure 16.
low by external circuitry to reset the device. Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least tDELAYmin.
Figure 16. External RESET Sequences

VDD
VDDnominal
VLVDf
SHORT PULSE ON RESET PIN

RESET
RUN INTERNAL RESET FETCH
RUN
DELAY
4096 CLOCK CYCLES VECTOR

tDE LAYmin
t PULSE
EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

VDD
VDDnominal
VLVDf

RESET
LONG PULSE ON RESET PIN

RUN RUN
INTERNAL RESET FETCH
DELAY
4096 CLOCK CYCLES VECTOR

t PULSE
EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

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RESET SEQUENCE MANAGER (Cont’d)

Internal Low Voltage Detection RESET ■ Voltage Drop RESET
Two different RESET sequences caused by the in- The device RESET pin acts as an output that is
ternal LVD circuitry can be distinguished: pulled low when VDD<VLVDr (rising edge) or
■ Power-On RESET VDD<VLVDf (falling edge) as shown in Figure 9.

Figure 17. LVD RESET Sequences

VDD
VDDnominal
VLVDr

RESET
RUN
POWER-ON RESET

INTERNAL RESET FETCH

DELAY
4096 CLOCK CYCLES VECTOR

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

VDD

VDDnominal
VLVDr
VLVDf

RESET
RUN RUN
VOLTAGE DROP RESET

INTERNAL RESET FETCH

DELAY
4096 CLOCK CYCLES VECTOR

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

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RESET SEQUENCE MANAGER (Cont’d)

Internal Watchdog RESET Starting from the Watchdog counter underflow, the
The RESET sequence generated by a internal device RESET pin acts as an output that is pulled
Watchdog counter overflow is shown in Figure 18. low during at least tDELAYmin.

Figure 18. Watchdog RESET Sequence

VDD

VDDnominal

VLVDf

RESET
RUN RUN
INTERNAL RESET FETCH
DELAY
4096 CLOCK CYCLES VECTOR

EXTERNAL RESET SOURCE

tDE LAYmin

RESET PIN

WATCHDOG RESET

WATCHDOG UNDERFLOW

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MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by 7 Crystal/Ceramic Oscillators
different sources coming from the multi-oscillator This family of oscillators has the advantage of pro-
block: ducing a high accuracy on the main clock of the
■ an external source ST7. The selection within a list of 4 oscillators with
■ 4 crystal or ceramic resonator oscillators different frequency ranges has to be done by OP-
■ 1 external RC oscillator
TION BYTE in order to reduce the consumption. In
this mode of the MO block, the resonator and the
■ 1 internal high frequency RC oscillator load capacitances have to be connected as shown
Each oscillator is optimized for a given frequency in Figure 20 and have to be mounted as close as
range in terms of consumption and is selectable possible to the oscillator pins in order to minimize
through the OPTION BYTE. output distortion and start-up stabilization time.
The loading capacitance values must be adjusted
External Clock Source according to the selected oscillator.
The default OPTION BYTE value selects the Ex- These oscillators, when selected via the OPTION
ternal Clock in the MO block. In this mode, a clock BYTE, are not stopped during the RESET phase
signal (square, sinus or triangle) with ~50% duty to avoid losing time in the oscillator start-up phase.
cycle has to drive the OSC1 pin while the OSC2
pin is tied to ground (see Figure 19).
Figure 19. MO External Clock Figure 20. MO Crystal/Ceramic Resonator

ST7
OSC1 OSC2
ST7
OSC1 OSC2

C L0 C L1
EXTERNAL LOAD
SOURCE CAPACITANCES

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MULTI-OSCILLATOR (Cont’d)
External RC Oscillator Internal RC Oscillator
This oscillator allows a low cost solution for the The Internal RC oscillator mode is based on the
main clock of the ST7 using only an external resis- same principle as the External RC oscillator in-
tor and an external capacitor (see Figure 21). The cluding the resistance and the capacitance of the
selection of the external RC oscillator has to be device. This mode is the most cost effective one
done by OPTION BYTE. with the drawback of a lower frequency accuracy.
The frequency of the external RC oscillator (in the Its frequency is in the range of several MHz.
range of some MHz.) is fixed by the resistor and In this mode, the two oscillator pins have to be tied
the capacitor values: to ground as shown in Figure 22.
4 1)
fOSC ~ The selection of the internal RC oscillator has to
REX . CEX be done by OPTION BYTE.
The previous formula shows that in this MO mode,
the accuracy of the clock is directly linked to the
accuracy of the discrete components.
Figure 21. MO External RC Figure 22. MO Internal RC

ST7
OSC1 OSC2
ST7
OSC1 OSC2

REX CEX

Note:
1) This formula provides an approximation of the frequency with typical REX and CEX values at VDD=5V.
It is given only as design guidelines.

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4.3 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the 4.3.2 Safe Oscillator Control
ST7 against main clock problems. To allow the in- The Safe Oscillator of the CSS block is a low fre-
tegration of the security features in the applica- quency back-up clock source (see Figure 24).
tions, it is based on a clock filter control and an In-
ternal Safe Oscillator. The CSS can be disabled by If the clock signal disappears (due to a broken or
OPTION BYTE. disconnected resonator...) during a Safe Oscillator
period, the Safe oscillator delivers a low frequency
4.3.1 Clock Filter Control clock signal which allows the ST7 to perform some
The Clock Filter is based on a clock frequency lim- rescue operations.
itation function. Automatically, the ST7 clock source switches back
This filter function is able to detect and filter high from the Safe Oscillator if the original clock source
frequency spikes on the ST7 main clock. recovers.
If the oscillator is not working properly (e.g. work- Limitation detection
ing at a harmonic frequency of the resonator), the The automatic Safe Oscillator selection is notified
current active oscillator clock can be totally fil- by hardware setting the CSSD bit of the CRSR
tered, and then no clock signal is available for the register. An interrupt can be generated if the CS-
ST7 from this oscillator anymore. If the original SIE bit has been previously set.
clock source recovers, the filtering is stopped au- These two bits are described in the CRSR register
tomatically and the oscillator supplies the ST7 description.
clock.

Figure 23. Clock Filter Function

MAIN
OSCILLATOR
CLOCK

INTERNAL
ST7
CLOCK

Figure 24. Safe Oscillator Function

MAIN
OSCILLATOR
CLOCK

SAFE
OSCILLATOR
CLOCK

INTERNAL
ST7
CLOCK

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4.4 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION

CLOCK RESET AND SUPPLY REGISTER Bit 1 = CSSD Clock security system detection
(CRSR) This bit indicates that the safe oscillator of the
Read/Write Clock Security System block has been selected by
hardware due to a disturbance on the main clock
Reset Value: 000x 000x (00h) signal (fOSC). It is set by hardware and cleared by
a read of the CRSR register when the original os-
7 0 cillator recovers.
0: Safe oscillator is not active
LVD CSS CSS WDG
0 0 0 0 1: Safe oscillator has been activated
RF IE D RF
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
Bit 7:5 = Reserved, always read as 0.
Bit 0 = WDGRF Watchdog reset flag
Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generat-
This bit indicates that the last Reset was generat- ed by the Watchdog peripheral. It is set by hard-
ed by the LVD block. It is set by hardware (LVD re- ware (watchdog reset) and cleared by software
set) and cleared by software (writing zero). See (writing zero) or a LVD Reset (to ensure a stable
WDGRF flag description for more details. When cleared state of the WDGRF flag when CPU
the LVD is disabled by OPTION BYTE, the LVDRF starts).
bit value is undefined. Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 = Reserved, always read as 0. RESET Sources LVDRF WDGRF
External RESET pin 0 0
Bit 2 = CSSIE Clock security syst interrupt enable
. Watchdog 0 1
This bit enables the interrupt when a disturbance LVD 1 X
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
Application notes
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the In case the LVDRF flag is not cleared upon anoth-
CSSIE bit has no effect. er RESET type occurs (extern or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this condition, a watchdog reset can be detect-
ed by the software while an external reset not.
Table 4. Clock, Reset and Supply Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

CRSR LVDRF CFIE CSSD WDGRF

002Bh
Reset Value 0 0 0 x 0 0 0 x

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4.5 MAIN CLOCK CONTROLLER (MCC)

The MCC block supplies the clock for the ST7 The counter allows to generate an interrupt based
CPU and its internal peripherals. It allows to man- on a accurate real time clock. Four different time
age the power saving modes such as the SLOW bases depending directly on fOSC are available.
and ACTIVE-HALT modes. The whole functionali- The whole functionality is controlled by four bits of
ty is managed by the Main Clock Control/Status the MCCSR register: TB1, TB0, OIE and OIF.
Register (MCCSR) and the Miscellaneous Regis- The clock-out capability allows to configure a ded-
ter 1 (MISCR1). icated I/O port pin as an fOSC/2 clock out to drive
The MCC block consists of: external devices. It is controlled by the MCO bit in
– a programmable CPU clock prescaler the MISCR1 register.
When selected, the clock out pin suspends the
– a time base counter with interrupt capability clock during ACTIVE-HALT mode.
– a clock-out signal to supply external devices
The prescaler allows to select the main clock fre-
quency and is controlled with three bits of the
MISCR1: CP1, CP0 and SMS.
Figure 25. Main Clock Controller (MCC) Block Diagram

MCC
OSC2
fOSC
OSCILLATOR DIV 2
OSC1

DIV 2, 4, 8, 16

PROGRAMMABLE
DIVIDER

MCCSR 0 0 0 0 TB1 TB0 OIE OIF

MCC INTERRUPT

MISCR1 - - MCO - - CP1 CP0 SMS

CPU CLOCK fCPU

TO CPU AND
PERIPHER ALS

PORT
MCO ALTERNATE fOSC/2
FUNCTION

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MAIN CLOCK CONTROLLER (Cont’d)

MISCELLANEOUS REGISTER 1 (MISCR1) A modification of the time base is taken into ac-
See section 6.2 on page 47. count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
MAIN CLOCK CONTROL/STATUS REGISTER use this time base as a real time clock.
(MCCSR)
Read/Write Bit 1 = OIE Oscillator interrupt enable
Reset Value: 0000 0001 (01h) This bit set and cleared by software.
0: Oscillator interrupt disabled
7 0 1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
0 0 0 0 TB1 TB0 OIE OIF mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode.
Bit 7:4 = Reserved, always read as 0. Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
Bit 3:2 = TB1-TB0 Time base control reading the CSR register. It indicates when set
These bits select the programmable divider time that the main oscillator has measured the selected
base. They are set and cleared by software. elapsed time (TB1:0).
0: Timeout not reached
Time Base 1: Timeout reached
Counter
TB1 TB0 Warning: The BRES and BSET instructions must
Prescaler
fOSC =8MHz fOSC=16MHz
not be used on the MCCSR register to avoid unin-
32000 4ms 2ms 0 0 tentionally clearing the OIF bit.
64000 8ms 4ms 0 1
160000 20ms 10ms 1 0
400000 50ms 25ms 1 1

Table 5. MCC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

MCCSR TB1 TB0 OIE OIF

0029h
Reset Value 0 0 0 0 0 0 0 1

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5 INTERRUPTS & POWER SAVING MODES

5.1 INTERRUPTS
The ST7 core may be interrupted by one of two dif- Halt low power mode (refer to the “Exit from HALT“
ferent methods: maskable hardware interrupts as column in the Interrupt Mapping Table).
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 26. External Interrupts
The maskable interrupts must be enabled clearing External interrupt vectors can be loaded in the PC
the I bit in order to be serviced. However, disabled register if the corresponding external interrupt oc-
interrupts may be latched and processed when curred and if the I bit is cleared. These interrupts
they are enabled (see external interrupts subsec- allow the processor to leave the Halt low power
tion). mode.
When an interrupt has to be serviced: The external interrupt polarity is selected through
– Normal processing is suspended at the end of the miscellaneous register or interrupt register (if
the current instruction execution. available).
– The PC, X, A and CC registers are saved onto External interrupt triggered on edge will be latched
the stack. and the interrupt request automatically cleared
upon entering the interrupt service routine.
– The I bit of the CC register is set to prevent addi-
tional interrupts. If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
– The PC is then loaded with the interrupt vector of nals are logically ANDed before entering the edge/
the interrupt to service and the first instruction of level detection block.
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address- Warning: The type of sensitivity defined in the
es). Miscellaneous or Interrupt register (if available)
applies to the EI source. In case of an ANDed
The interrupt service routine should finish with the source (as described on the I/O ports section), a
IRET instruction which causes the contents of the low level on an I/O pin configured as input with in-
saved registers to be recovered from the stack. terrupt, masks the interrupt request even in case
Note: As a consequence of the IRET instruction, of rising-edge sensitivity.
the I bit will be cleared and the main program will Peripheral Interrupts
resume.
Different peripheral interrupt flags in the status
Priority management register are able to cause an interrupt when they
By default, the interrupt being serviced cannot be are active if both:
interrupted because the I bit is set by hardware – The I bit of the CC register is cleared.
when entering an interrupt routine.
– The corresponding enable bit is set in the control
If several interrupts are simultaneously pending, a register.
hardware priority defines which one will be serv-
iced first (see the Interrupt Mapping Table). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Non Maskable Software Interrupts
Clearing an interrupt request is done by:
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit. – writing “0” to the corresponding bit in the status
It will be serviced according to the flowchart on register or
Figure 26. – an access to the status register while the flag is
set followed by a read or write of an associated
register.
Interrupts and Low power mode
Note: the clearing sequence resets the internal
All interrupts allow the processor to leave the Wait latch. A pending interrupt (i.e. waiting for being en-
low power mode. Only external and specific men- abled) will therefore be lost if the clear sequence is
tioned interrupts allow the processor to leave the executed.

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INTERRUPTS (Cont’d)
Figure 26. Interrupt Processing Flowchart

FROM RESET

N
BIT I SET

Y N
BIT I SET

FETCH NEXT INSTR UCTION Y

N
IRET
STACK PC, X, A, CC
Y SET I BIT
LOAD PC FROM INTERRUPT VECTO R
EXECU TE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 6. Interrupt Mapping

Exit
Source Register Priority Address
N° Description from
Block Label Order Vector
HALT
RESET Reset Highest yes FFFEh-FFFFh
N/A Priority
TRAP Software Interrupt no FFFCh-FFFDh
0 Not used FFFAh-FFFBh
MCC Main Clock Controller Time Base Interrupt MCCSR yes
1 FFF8h-FFF9h
CSS or Clock Security System Interrupt CRSR
2 EI0 External Interrupt Port A3..0 FFF6h-FFF7h
3 EI1 External Interrupt Port F2..0 FFF4h-FFF5h
N/A
4 EI2 External Interrupt Port B3..0 FFF2h-FFF3h
5 EI3 External Interrupt Port B7..4 FFF0h-FFF1h
6 Not used FFEEh-FFE Fh
7 SPI SPI Peripheral Interrupts SPISR no FFECh-FFEDh
8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh
9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE9h
10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE7h
11 Data-EEPROM Data EEPROM Interrupt EECSR FFE4h-FFE5h
12 Lowest FFE2h-FFE3h
Not used
13 Priority FFE0h-FFE1h

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5.2 POWER SAVING MODES

5.2.1 Introduction
To give a large measure of flexibility to the applica- means of a master clock which is based on the
tion in terms of power consumption, four main main oscillator frequency divided by 2 (fCPU).
power saving modes are implemented in the ST7. From Run mode, the different power saving
After a RESET the normal operating mode is se- modes may be selected by setting the relevant
lected by default (RUN mode). This mode drives register bits or by calling the specific ST7 software
the device (CPU and embedded peripherals) by instruction whose action depends on the the oscil-
lator status.
Figure 27. Power saving mode consumption / transitions

HALT ACTIVE-HALT SLOW WAIT WAIT SLOW RUN

Low High

POWER CONSUMPTION

5.2.2 HALT Modes

The HALT modes are the lowest power consump- Mode capability or a reset (see Table 6 page 37).
tion modes of the MCU. They are entered by exe- A 4096 CPU clock cycles delay is performed be-
cuting the ST7 HALT instruction (see Figure 29). fore the CPU operation resumes (see Figure 28).
Two different HALT modes can be distinguished: After the start up delay, the CPU resumes opera-
– HALT: main oscillator is turned off, tion by servicing the interrupt or by fetching the re-
set vector which woke it up.
– ACTIVE-HALT: only main oscillator is running.
The decision to enter either in HALT or ACTIVE- Table 7. HALT Modes selection
HALT mode is given by the main oscillator enable
MCCSR
interrupt flag (OIE bit in CROSS-MCCSR register: Power Saving Mode entered when HALT
OIE
see Table 7). instruction is executed
flag
When entering HALT modes, the I bit in the CC
register is forced to 0 to enable interrupts. 0 HALT (reset if watchdog enabled)

The MCU can exit HALT or ACTIVE-HALT modes 1 ACTIVE-HALT (no reset if watchdog enabled)
on reception of an interrupt with Exit from Halt
Figure 28. HALT /ACTIVE-HALT Modes timing overview

4096 CPU CYCLE

RUN HALT OR ACTIVE-HALT RUN
DELAY

RESET FETCH
HALT OR VECTOR
INSTRUCTION INTERRUPT

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POWER SAVING MODES (Cont’d)

Standard HALT mode Specific ACTIVE-HALT mode
In this mode the main oscillator is turned off caus- As soon as the interrupt capability of the main os-
ing all internal processing to be stopped, including cillator is selected (OIE bit set), the HALT instruc-
the operation of the on-chip peripherals. All periph- tion will make the device enter a specific ACTIVE-
erals are not clocked except the ones which get HALT power saving mode instead of the standard
their clock supply from another clock generator HALT one.
(such as an external or auxiliary oscillator). This mode consists of having only the main oscil-
The compatibility of Watchdog operation with Halt lator and its associated counter running to keep a
mode is configured by the “WDGHALT” option bit wake-up time base. All other peripherals are not
of the OPTION BYTE. The HALT instruction when clocked except the ones which get their clock sup-
executed while the Watchdog system is enabled, ply from another clock generator (such as external
can generate a Watchdog RESET (see dedicated or auxiliary oscillator).
section for more details). The safeguard against staying locked in this AC-
When exiting HALT mode by means of a RESET TIVE-HALT mode is insured by the oscillator inter-
or an interrupt, the oscillator is immediately turned rupt.
on and the 4096 CPU cycle delay is used to stabi-
lize the oscillator. Note: As soon as the interrupt capability of one of
the oscillators is selected (OIE bit set), entering in
ACTIVE-HALT mode while the Watchdog is active
does not generate a RESET.
This means that the device cannot to spend more
than a defined delay in this power saving mode.
Figure 29. HALT modes flow-chart

If WDGHA LT
bit reset in HALT INSTR UCTION
OPTION BYTE

MAIN 1
N WAT CHDOG Y 0
OSCILLATOR
ENABLE OIE BIT
HALT ACTIV E-HALT

OSCILLATOR OFF OSCILLATOR ON

PERIPHERALS OFF PERIPH ERALS OFF
CPU OFF CPU OFF
I BIT 0 I BIT 0

N
RESET 4096 clock cycles delay

N EXTE RNAL* OSCILLATOR ON

INTERRUP T PERIPH ERALS ON
OSCILLATOR ON CPU ON
PERIP HERALS OFF FETCH RESET VECTOR
Y
CPU OFF OR SERVICE INTERRUPT **

Notes: * External interrupt or internal interrupts with Exit from Halt Mode capability
** Before servicing an interrupt, the CC register is pushed on the stack.

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POWER SAVING MODES (Cont’d)

5.2.3 WAIT Mode
WAIT mode places the MCU in a low power con- mode until an interrupt or Reset occurs, whereup-
sumption mode by stopping the CPU. on the Program Counter branches to the starting
This power saving mode is selected by calling the address of the interrupt or Reset service routine.
“WFI” ST7 software instruction. The MCU will remain in WAIT mode until a Reset
All peripherals remain active. During WAIT mode, or an Interrupt occurs, causing it to wake up.
the I bit of the CC register is forced to 0 to enable Refer to Figure 30.
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in WAIT
Figure 30. WAIT mode flow-chart

OSCILLATOR ON
PERIPHERA LS ON
WFI INSTRUCTION
CPU OFF
I BIT 0

N
RESET
if exit caused by a RESET, a 4096 CPU
N Y
clock cycle delay is inserted.
INTERRUPT

Y
OSCILLATOR ON
PERIPHERALS ON
OSCILLATOR ON CPU ON
PERIPHERALS OFF* FETCH RESET VECTOR
CPU OFF OR SERVICE INTER RUPT**

Note: * The peripheral clock is stopped only when exit caused by RESET and not by an interrupt.
** Before servicing an interrupt, the CC register is pushed on the stack.

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POWER SAVING MODES (Cont’d)

5.2.4 SLOW Mode
This mode has two targets: disables Slow mode and two CPx bits which select
– To reduce power consumption by decreasing the the internal slow frequency (fCPU).
internal clock in the device, In this mode, the oscillator frequency can be divid-
– To adapt the internal clock frequency (fCPU) to ed by 4, 8, 16 or 32 instead of 2 in normal operat-
the available supply voltage. ing mode. The CPU and peripherals are clocked at
this lower frequency.
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 31. SLOW Mode: timing diagram for internal CPU clock transitions

NEW FREQUENCY
ACTIV E WHEN NORMAL MODE ACTIVE
OSC/4 & OSC/8 = 0 (OSC/4, OSC/8 STOPPED)

fOSC/4

fOSC/8

fCPU

CP1:0 00 01
MISCR1
REGISTE R
SMS 1 0

NEW FREQUENCY
REQUEST NORMAL MODE
REQUEST

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6 ON-CHIP PERIPHERALS

6.1 I/O PORTS

6.1.1 Introduction Each external interrupt vector is linked to a dedi-
The I/O ports offer different functional modes: cated group of I/O port pins (see Interrupt section).
– transfer of data through digital inputs and outputs If more than one input pins are selected simultane-
and for specific pins: ously as interrupt source, these are logically AND-
– external interrupt generation ed. For this reason if one of the interrupt pins is
– alternate signal input/output for the on-chip pe- tied low, it masks the other ones.
ripherals (SPI, SCI, TIMERs...). In case of a floating input with interrupt configura-
An I/O port contains up to 8 pins. Each pin can be tion, special cares mentioned in the I/O port imple-
programmed independently as digital input (with or mentation section have to be taken.
without interrupt generation) or digital output. Output Mode
6.1.2 Functional Description The output configuration is selected by setting the
Each port is associated to 2 main registers: corresponding DDR register bit.
– Data Register (DR) In this case, writing the DR register applies this
digital value to the I/O pin through the latch. Then
– Data Direction Register (DDR) reading the DR register returns the previously
and one optional register: stored value.
– Option Register (OR) Two different output modes can be selected by
software through the OR register: Output push-pull
Each I/O pin may be programmed using the corre-
and open-drain.
sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same cor- DR register value and output pin status:
respondence is used for the DR register.
DR Push-pu ll Open-drain
The following description takes into account the 0 VSS Vss
OR register, for specific port which do not provide
this register refer to the I/O Port Implementation 1 VDD Floating
section. The generic I/O block diagram is shown
on Figure 32 Note: In this mode, interrupt function is disabled.
Input Modes Alternate function
The input configuration is selected by clearing the When an on-chip peripheral is configured to use a
corresponding DDR register bit. pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
In this case, reading the DR register returns the standard I/O programming.
digital value applied to the external I/O pin.
When the signal is coming from an on-chip periph-
Different input modes can be selected by software eral, the I/O pin is automatically configured in out-
through the OR register. put mode (push-pull or open drain according to the
Note1: Writing the DR register modifies the latch peripheral).
value but does not affect the pin status.
Note2: When switching from input to output mode, When the signal is going to an on-chip peripheral,
the DR register has to be written first to drive the the I/O pin has to be configured in input mode. In
correct level on the pin as soon as the ports is con- this case, the pin’s state is also digitally readable
figured as an output. by addressing the DR register.
External interrupt function Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
When an I/O is configured in Input with Interrupt, input. When an on chip peripheral use a pin as in-
an event on this I/O can generate an external In- put and output, this pin has to be configured in in-
terrupt request to the CPU. put floating mode.
Each pin can independently generate an Interrupt WARNING: The alternate function must not be ac-
request. The interrupt sensitivity is given inde- tivated as long as the pin is configured as input
pendently according to the description mentioned with interrupt, in order to avoid generating spurious
in the Miscellaneous register. interrupts.

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I/O PORTS (Cont’d)

Figure 32. I/O Block Diagram

ALTERNATE
1
OUTPUT VDD P-BUFFER
(see table below)
0
ALTERNATE
PULL-UP
ENABLE
(see table below)

DR V DD

DDR

PULL-UP
PAD
CONDITION
OR
DATA BUS

If implemented

OR SEL

N-BUFFER
DIODES
(see table below)
DDR SEL
ANALOG
INPUT
CMOS
SCHMITT
DR SEL
1 TRIGGER

0
ALTERNATE
INPUT
EXTERNAL
FROM
INTERRUPT OTHER
SOURCE (EIx) BITS
POLARITY
SELECTION

Table 8. Port Mode Options

Diodes
Configuration Mode Pull-Up P-Buffer
to VDD to VSS
Floating with/without Interrupt Off
Input Off
Pull-up with/without Interrupt On
On
Push-pull On On
Off
Output Open Drain (logic level) Off
True Open Drain NI NI NI (see note)

Legend:NI - not implemented Note: the diode to VDD is not implemented in the
Off - implemented not activated true open drain pads. A local protection between
On - implemented and activated the pad and VSS is implemented to protect the de-
vice against positive stress.

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I/O PORTS (Cont’d)

6.1.3 I/O Port Implementation Switching these I/O ports from one state to anoth-
The I/O port register configurations are summa- er should be done in a sequence that prevents un-
rised as following. wanted side effects. Recommended safe transi-
tions are illustrated in Figure 33 Other transitions
Standard Ports are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4
such as spurious interrupt generation.
MODE DDR OR
Figure 33. Interrupt I/O Port State Transition
floating input 0 0
pull-up input 0 1
01 00 10 11
open drain output 1 0
push-pull output 1 1 INPUT INPUT OUTPUT OUTPUT
pull-up/floating floating open-drain push-pull
Interrupt Ports interrupt (reset state)

PA2:0, PB6:4, PB2:0, PF1:0 (with pull-up) XX = DDR, OR

MODE DDR OR
floating input 0 0 True Open Drain Ports
pull-up interrupt input 0 1
PA7:6
open drain output 1 0
push-pull output 1 1 MODE DDR
floating input 0
PA3, PB7, PB3, PF2 (without pull-up)
open drain (high sink ports) 1
MODE DDR OR
floating input 0 0
floating interrupt input 0 1
open drain output 1 0
push-pull output 1 1

Table 9. Port Configuration

Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1
PA7:6 floating true open-drain
PA5:4 floating pull-up open drain push-pull
Port A
PA3 floating floating interrupt open drain push-pull
PA2:0 floating pull-up interrupt open drain push-pull
PB7, PB3 floating floating interrupt open drain push-pull
Port B
PB6:4, PB2:0 floating pull-up interrupt open drain push-pull
Port C PC7:0 floating pull-up open drain push-pull
Port D PD7:0 floating pull-up open drain push-pull
Port E PE7:4, PE1:0 floating pull-up open drain push-pull
PF7:6, PF4 floating pull-up open drain push-pull
Port F PF2 floating floating interrupt open drain push-pull
PF1:0 floating pull-up interrupt open drain push-pull

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I/O PORTS (Cont’d)

6.1.4 Register Description

DATA REGISTER (DR) OPTION REGISTER (OR)
Port x Data Register Port x Option Register
PxDR with x = A, B, C, D, E or F. PxOR with x = A, B, C, D, E or F.
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)

7 0 7 0

D7 D6 D5 D4 D3 D2 D1 D0 O7 O6 O5 O4 O3 O2 O1 O0

Bit 7:0 = D[7:0] Data register 8 bits. Bit 7:0 = O[7:0] Option register 8 bits.
The DR register has a specific behaviour accord- For specific I/O pins, this register is not implement-
ing to the selected input/output configuration. Writ- ed. In this case the DDR register is enough to se-
ing the DR register is always taken into account lect the I/O pin configuration.
even if the pin is configured as an input; this allows The OR register allows to distinguish: in input
to always have the expected level on the pin when mode if the pull-up with interrupt capability or the
toggling to output mode. Reading the DR register basic pull-up configuration is selected, in output
returns either the DR register latch content (pin mode if the push-pull or open drain configuration is
configured as output) or the digital value applied to selected.
the I/O pin (pin configured as input).
Each bit is set and cleared by software.
Input mode:
DATA DIRECTION REGISTER (DDR) 0: floating input
Port x Data Direction Register 1: pull-up input with or without interrupt
PxDDR with x = A, B, C, D, E or F.
Output mode:
Read/Write 0: output open drain (with P-Buffer unactivated)
Reset Value: 0000 0000 (00h) 1: output push-pull

7 0

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

Bit 7:0 = DD[7:0] Data direction register 8 bits.

The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode

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I/O PORTS (Cont’d)

Table 10. I/O Port Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

Reset Value
0 0 0 0 0 0 0 0
of all IO port registers
0000h PADR
0001h PADDR MSB LSB
0002h PAOR 1)

0004h PCDR
0005h PCDDR MSB LSB
0006h PCOR
0008h PBDR
0009h PBDDR MSB LSB
1)
000Ah PBOR
000Ch PEDR

000Dh PEDDR MSB LSB

1)
000Eh PEOR
0010h PDDR
0011h PDDDR MSB LSB
0012h PDOR 1)
0014h PFDR
0015h PFDDR MSB LSB
0016h PFOR
Notes:
1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.

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6.2 MISCELLANEOUS REGISTERS

The miscellaneous registers allow control over 6.2.2 I/O Port Alternate Functions
several different features such as the external in- The MISCR registers manage four I/O port miscel-
terrupts or the I/O alternate functions. laneous alternate functions:
6.2.1 I/O Port Interrupt Sensitivity Description ■ Main clock signal (fCPU) output on PF0

The external interrupt sensitivity is controlled by ■ A beep signal output on PF1 (with 3 selectable
the ISxx bits of the MISCR1 miscellaneous regis- audio frequencies)
ter. This control allows to have two fully independ- ■ SPI pin configuration:
ent external interrupt source sensitivities. – SS pin internal control to use the PC7 I/O port
Each external interrupt source can be generated function while the SPI is active.
on four different events on the pin: These functions are described in detail in the Sec-
■ Falling edge tion 6.2.3 Miscellaneous Registers Description.
■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

To guarantee correct functionality, the sensitivity

bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.

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MISCELLANEOUS REGISTERS (Cont’d)

6.2.3 Miscellaneous Registers Description
MISCELLANEOUS REGISTER 1 (MISCR1) Bit 4:3 = IS2[1:0] EI0 and EI1 sensitivity
Read/Write The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:-
Reset Value: 0000 0000 (00h) EI0 (port A3..0) and EI1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
7 0 is set to 1 (interrupt disabled).

IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS

Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
Bit 7:6 = IS1[1:0] EI2 and EI3 sensitivity conditioned by the setting of the SMS bit. These
The interrupt sensitivity, defined using the IS1[1:0] two bits are set and cleared by software
bits, is applied to the following external interrupts: CP1 CP0 fCPU in SLOW mode
EI2 (port B3..0) and EI3 (port B7..4). These 2 bits
0 0 fOSC / 4
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled). 1 0 fOSC / 8
0 1 fOSC / 16
IS11 IS10 External Interrupt Sensitivity
1 1 fOSC / 32
0 0 Falling edge & low level
0 1 Rising edge only
1 0 Falling edge only Bit 0 = SMS Slow mode select
1 1 Rising and falling edge This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC / 2
1: Slow mode. fCPU is given by CP1, CP0
Bit 5 = MCO Main clock out selection See low power consumption mode and MCC
This bit enables the MCO alternate function on the chapters for more details.
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(fOSC/2 on I/O port)
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.

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MISCELLANEOUS REGISTERS (Cont’d)

MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)

7 0

- - BC1 BC0 - - SSM SSI

Bit 7:6 = Reserved Must always be cleared

Bit 5:4 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.
BC1 BC0 Beep mode with fOSC=16MHz
0 0 Off
0 1 ~2-KHz
Output
1 0 ~1-KHz Beep signal
~50% duty cycle
1 1 ~500-Hz

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the
consumption.

Bit 3:2 = Reserved Must always be cleared

Bit 1 = SSM SS mode selection

It is set and cleared by software.
0: Normal mode - SS uses information coming
from the SS pin of the SPI.
1: I/O mode, the SPI uses the information stored
into bit SSI.

Bit 0 = SSI SS internal mode

This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.

Table 11. Miscellaneous Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

MISCR1 IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS

0020h
Reset Value 0 0 0 0 0 0 0 0
MISCR2 BC1 BC0 SSM SSI
0040h
Reset Value 0 0 0 0 0 0 0 0

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6.3 WATCHDOG TIMER (WDG)

6.3.1 Introduction ■ Hardware Watchdog selectable by option byte
The Watchdog timer is used to detect the occur- ■ Watchdog Reset indicated by status flag (in
rence of a software fault, usually generated by ex- versions with Safe Reset option only)
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir- 6.3.3 Functional Description
cuit generates an MCU reset on expiry of a pro- The counter value stored in the CR register (bits
grammed time period, unless the program refresh- T[6:0]), is decremented every 12,288 machine cy-
es the counter’s contents before the T6 bit be- cles, and the length of the timeout period can be
comes cleared. programmed by the user in 64 increments.
6.3.2 Main Features If the watchdog is activated (the WDGA bit is set)
■ Programmable timer (64 increments of 12288 and when the 7-bit timer (bits T[6:0]) rolls over
CPU cycles) from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
■ Programmable reset
500ns.
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 34. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

WDGA T6 T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU CLOCK DIVIDER

÷12288

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WATCHDOG TIMER (Cont’d)

The application program must write in the CR reg- 6.3.7 Register Description
ister at regular intervals during normal operation to CONTROL REGISTER (CR)
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h Read/Write
(see Table 12 .Watchdog Timing (fCPU = 8 MHz)): Reset Value: 0111 1111 (7Fh)
– The WDGA bit is set (watchdog enabled) 7 0
– The T6 bit is set to prevent generating an imme-
diate reset WDGA T6 T5 T4 T3 T2 T1 T0
– The T[5:0] bits contain the number of increments
which represents the time delay before the
Bit 7 = WDGA Activation bit.
watchdog produces a reset.
This bit is set by software and only cleared by
Table 12.Watchdog Timing (fCPU = 8 MHz) hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
CR Register WDG timeout period 0: Watchdog disabled
initial value (ms) 1: Watchdog enabled
Max FFh 98.304 Note: This bit is not used if the hardware watch-
Min C0h 1.536 dog option is enabled by option byte.

Notes: Following a reset, the watchdog is disa- Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
bled. Once activated it cannot be disabled, except These bits contain the decremented value. A reset
by a reset. is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction STATUS REGISTER (SR)
will generate a Reset. Read/Write
Reset Value*: 0000 0000 (00h)
6.3.4 Hardware Watchdog Option 7 0
If Hardware Watchdog Is selected by option byte,
the watchdog is always active and the WDGA bit in - - - - - - - WDOGF
the CR is not used.
Refer to the device-specific Option Byte descrip- Bit 0 = WDOGF Watchdog flag.
tion. This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
6.3.5 Low Power Modes for distinguishing power/on off or external reset
and watchdog reset.
Mode Description 0: No Watchdog reset occurred
WAIT No effect on Watchdog. 1: Watchdog reset occurred
Immediate reset generation as soon as
the HALT instruction is executed if the
HALT * Only by software and power on/off reset
Watchdog is activated (WDGA bit is
set). Note: This register is not used in versions without
LVD Reset.

6.3.6 Interrupts
None.

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WATCHDOG TIMER (Cond’t)

Table 13. Watchdog Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
002Ah
Reset Value 0 1 1 1 1 1 1 1

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6.4 16-BIT TIMER

6.4.1 Introduction 6.4.3 Functional Description
The timer consists of a 16-bit free-running counter 6.4.3.1 Counter
driven by a programmable prescaler. The principal block of the Programmable Timer is
It may be used for a variety of purposes, including a 16-bit free running increasing counter and its as-
pulse length measurement of up to two input sig- sociated 16-bit registers:
nals (input capture) or generation of up to two out- Counter Registers
put waveforms (output compare and PWM).
– Counter High Register (CHR) is the most sig-
Pulse lengths and waveform periods can be mod- nificant byte (MSB).
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU – Counter Low Register (CLR) is the least sig-
clock prescaler. nificant byte (LSB).
Alternate Counter Registers
6.4.2 Main Features – Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
– Alternate Counter Low Register (ACLR) is the
■ Overflow status flag and maskable interrupt least significant byte (LSB).
■ External clock input (must be at least 4 times
These two read-only 16-bit registers contain the
slower than the CPU clock speed) with the choice same value but with the difference that reading the
of active edge ACLR register does not clear the TOF bit (overflow
■ Output compare functions with flag), (see note at the end of paragraph titled 16-bit
– 2 dedicated 16-bit registers read sequence).
– 2 dedicated programmable signals Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
– 2 dedicated status flags
– 1 dedicated maskable interrupt
The timer clock depends on the clock control bits
■ Input capture functions with
of the CR2 register, as illustrated in Table 14 Clock
– 2 dedicated 16-bit registers Control Bits. The value in the counter register re-
– 2 dedicated active edge selection signals peats every 131.072, 262.144 or 524.288 internal
processorclock cycles depending on the CC1 and
– 2 dedicated status flags CC0 bits.
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)

■ One pulse mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 35.

*Note: Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.

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16-BIT TIMER (Cont’d)

Figure 35. Timer Block Diagram

ST7 INTERNAL BUS

fCPU
MCU-PERIPHERAL INTERFACE

8 high 8 low
8-bit 8 8 8 8 8 8 8 8
buffer
high

high

high

high
low

low

low

low
EXEDG

16

16 BIT OUTPUT OUTPUT INPUT INPUT

1/2
FREE RUNNING COMPARE COMPARE CAPTURE CAPTURE
1/4
COUNTER REGISTER REGISTER REGISTER REGISTER
1/8
1 2 1 2
COUNTER
ALTERNATE
REGISTER 16 16

16
CC1 CC0
TIMER INTERNAL BUS
16 16

OVERFLOW
EXTCLK OUTPUT COMPARE EDGE DETECT ICAP1
DETECT
CIRCUIT CIRCUIT1
CIRCUIT

6 EDGE DETECT ICAP2

CIRCUIT2

LATCH1 OCMP1

ICF1 OCF1 TOF ICF2 OCF2 0 0 0

LATCH2 OCMP2
SR

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

CR1 CR2

TIMER INTERRUPT

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16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register). two steps:
Beginning of the sequence 1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
At t0 Read MSB LSB is buffered ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
Other running counter at random times (for example, to
instructions measure elapsed time) without the risk of clearing
the TOF bit erroneously.
Returns the buffered The timer is not affected by WAIT mode.
At t0 +∆t Read LSB LSB value at t0
In HALT mode, the counter stops counting until the
Sequence completed mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
The user must read the MSB first, then the LSB from the reset count (MCU awakened by a Reset).
value is buffered automatically.
This buffered value remains unchanged until the 6.4.3.2 External Clock
16-bit read sequence is completed, even if the
The external clock (where available) is selected if
user reads the MSB several times.
CC0=1 and CC1=1 in CR2 register.
After a complete reading sequence, if only the
The status of the EXEDG bit determines the type
CLR register or ACLR register are read, they re-
of level transition on the external clock pin EXT-
turn the LSB of the count value at the time of the
CLK that will trigger the free running counter.
read.
The counter is synchronised with the falling edge
Whatever the timer mode used (input capture, out-
of the internal CPU clock.
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from At least four falling edges of the CPU clock must
FFFFh to 0000h then: occur between two consecutive active edges of
the external clock; thus the external clock frequen-
– The TOF bit of the SR register is set.
cy must be less than a quarter of the CPU clock
– A timer interrupt is generated if: frequency.
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

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16-BIT TIMER (Cont’d)

Figure 36. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFD FFFE FFFF 0000 0001 0002 0003

OVERFLOW FLAG TOF

Figure 37. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000 0001

OVERFLOW FLAG TOF

Figure 38. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000

OVERFLOW FLAG TOF

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16-BIT TIMER (Cont’d)

6.4.3.3 Input Capture When an input capture occurs:
In this section, the index, i, may be 1 or 2. – ICFi bit is set.
The two input capture 16-bit registers (IC1R and – The ICiR register contains the value of the free
IC2R) are used to latch the value of the free run- running counter on the active transition on the
ning counter after a transition detected by the ICAPi pin (see Figure 40).
ICAP i pin (see figure 5). – A timer interrupt is generated if the ICIE bit is set
MS Byte LS Byte and the I bit is cleared in the CC register. Other-
ICiR ICiHR ICiLR wise, the interrupt remains pending until both
conditions become true.
ICi register is a read-only register. Clearing the Input Capture interrupt request is
The active transition is software programmable done in two steps:
through the IEDGi bit of the Control Register (CRi). 1. Reading the SR register while the ICFi bit is set.
Timing resolution is one count of the free running 2. An access (read or write) to the ICiLR register.
counter: (fCPU/(CC1.CC0) ).
Notes:
Procedure: 2. After reading the ICiHR register, transfer of
To use the input capture function select the follow- input capture data is inhibited until the ICiLR
ing in the CR2 register: register is also read.
– Select the timer clock (CC1-CC0) (see Table 14 3. The ICiR register always contains the free run-
Clock Control Bits). ning counter value which corresponds to the
– Select the edge of the active transition on the most recent input capture.
ICAP2 pin with the IEDG2 bit (the ICAP2 pin 4. The 2 input capture functions can be used
must be configured as floating input). together even if the timer also uses the output
And select the following in the CR1 register: compare mode.
– Set the ICIE bit to generate an interrupt after an 5. In One pulse Mode and PWM mode only the
input capture coming from both the ICAP1 pin or input capture 2 can be used.
the ICAP2 pin 6. The alternate inputs (ICAP1 & ICAP2) are
– Select the edge of the active transition on the always directly connected to the timer. So any
ICAP1 pin with the IEDG1 bit (the ICAP1pin must transitions on these pins activate the input cap-
be configured as floating input). ture process.
7. Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
8. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).

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16-BIT TIMER (Cont’d)

Figure 39. Input Capture Block Diagram

ICAP1 (Control Register 1) CR1

pin
EDGE DETECT EDGE DETECT ICIE IEDG1
ICAP2 CIRCUIT2 CIRCUIT1
pin (Status Register) SR

IC2R Register IC1R Register ICF1 ICF2 0 0 0

(Control Register 2) CR2

16-BIT
16-BIT FREE RUNNING CC1 CC0 IEDG2
COUNTER

Figure 40. Input Capture Timing Diagram

TIMER CLOCK

COUNTER REGISTER FF01 FF02 FF03

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER FF03

Note: Active edge is rising edge.

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16-BIT TIMER (Cont’d)

6.4.3.4 Output Compare
∆t * fCPU
In this section, the index, i, may be 1 or 2.
∆ OCiR =
This function can be used to control an output PRESC
waveform or indicating when a period of time has Where:
elapsed.
∆t = Desired output compare period (in sec-
When a match is found between the Output Com- onds)
pare register and the free running counter, the out-
put compare function: fCPU = Internal clock frequency
– Assigns pins with a programmable value if the PRESC = Timer prescaler factor (2, 4 or 8 de-
OCIE bit is set pending on CC1-CC0 bits, see Table 14
Clock Control Bits)
– Sets a flag in the status register
Clearing the output compare interrupt request is
– Generates an interrupt if enabled done by:
Two 16-bit registers Output Compare Register 1 1. Reading the SR register while the OCFi bit is
(OC1R) and Output Compare Register 2 (OC2R) set.
contain the value to be compared to the free run-
ning counter each timer clock cycle. 2. An access (read or write) to the OCiLR register.
MS Byte LS Byte
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
OCiR OCiHR OCiLR
it is read and the write to the OCiR register:
These registers are readable and writable and are – Write to the OCiHR register (further compares
not affected by the timer hardware. A reset event are inhibited).
changes the OCiR value to 8000h. – Read the SR register (first step of the clearance
Timing resolution is one count of the free running of the OCFi bit, which may be already set).
counter: (fCPU/(CC1.CC0)). – Write to the OCiLR register (enables the output
Procedure: compare function and clears the OCFi bit).
To use the output compare function, select the fol- Notes:
lowing in the CR2 register: 1. After a processor write cycle to the OCiHR reg-
– Set the OCiE bit if an output is needed then the ister, the output compare function is inhibited
OCMPi pin is dedicated to the output compare i until the OCiLR register is also written.
function. 2. If the OCiE bit is not set, the OCMPi pin is a
– Select the timer clock (CC1-CC0) (see Table 14 general I/O port and the OLVLi bit will not
Clock Control Bits). appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
And select the following in the CR1 register:
3. When the clock is divided by 2, OCFi and
– Select the OLVL i bit to applied to the OCMPi pins OCMPi are set while the counter value equals
after the match occurs. the OCiR register value (see Figure 42). This
– Set the OCIE bit to generate an interrupt if it is behaviour is the same in OPM or PWM mode.
needed. When the clock is divided by 4, 8 or in external
When a match is found: clock mode, OCFi and OCMP i are set while the
counter value equals the OCiR register value
– OCFi bit is set. plus 1 (see Figure 43).
– The OCMPi pin takes OLVLi bit value (OCMPi 4. The output compare functions can be used both
pin latch is forced low during reset and stays low for generating external events on the OCMPi
until valid compares change it to a high level). pins even if the input capture mode is also
– A timer interrupt is generated if the OCIE bit is used.
set in the CR2 register and the I bit is cleared in 5. The value in the 16-bit OCiR register and the
the CC register (CC). OLVi bit should be changed after each suc-
The OCiR register value required for a specific tim- cessful comparison in order to control an output
ing application can be calculated using the follow- waveform or establish a new elapsed timeout.
ing formula:

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16-BIT TIMER (Cont’d)

Figure 41. Output Compare Block Diagram

16 BIT FREE RUNNING OC1E OC2E CC1 CC0

COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE Latch
OCIE OLVL2 OLVL1 OCMP1
CIRCUIT 1
Pin
16-bit 16-bit
Latch
2
OCMP2
OC1R Register Pin
OCF1 OCF2 0 0 0
OC2R Register
(Status Register) SR

Figure 42. Output Compare Timing Diagram, Internal Clock Divided by 2

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER 2ED3

OUTPUT COMPARE FLAG (OCFi)

OCMPi PIN (OLVLi=1)

Figure 43. Output Compare Timing Diagram, Internal Clock Divided by 4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER 2ED3

COMPARE REGISTER LATCH

OCFi AND OCMPi PIN (OLVLi=1)

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16-BIT TIMER (Cont’d)

6.4.3.5 Forced Compare
In this section i may represent 1 or 2.
One pulse mode cycle
The following bits of the CR1 register are used:
When
event occurs OCMP1 = OLVL2
FOLV2 FOLV1 OLVL2 OLVL1 on ICAP1 Counter is reset
to FFFCh
When the FOLVi bit is set by software, the OLVLi ICF1 bit is set
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when When
it is enabled (OCiE bit=1). The OCFi bit is then not Counter
= OC1R OCMP1 = OLVL1
set by hardware, and thus no interrupt request is
generated.
FOLVLi bits have no effect in both one pulse mode
Then, on a valid event on the ICAP1 pin, the coun-
and PWM mode.
ter is initialized to FFFCh and OLVL2 bit is loaded
6.4.3.6 One Pulse Mode on the OCMP1 pin, the ICF1 bit is set and the val-
One Pulse mode enables the generation of a ue FFFDh is loaded in the IC1R register.
pulse when an external event occurs. This mode is When the value of the counter is equal to the value
selected via the OPM bit in the CR2 register. of the contents of the OC1R register, the OLVL1
The one pulse mode uses the Input Capture1 bit is output on the OCMP1 pin, (See Figure 44).
function and the Output Compare1 function.
Procedure: Notes:
To use one pulse mode: 1. The OCF1 bit cannot be set by hardware in one
1. Load the OC1R register with the value corre- pulse mode but the OCF2 bit can generate an
sponding to the length of the pulse (see the for- Output Compare interrupt.
mula in Section 6.4.3.7). 2. The ICF1 bit is set when an active edge occurs
2. Select the following in the CR1 register: and can generate an interrupt if the ICIE bit is
set.
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse. 3. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
– Using the OLVL2 bit, select the level to be ap- PWM mode is the only active one.
plied to the OCMP1 pin during the pulse.
4. If OLVL1=OLVL2 a continuous signal will be
– Select the edge of the active transition on the seen on the OCMP1 pin.
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input). 5. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
3. Select the following in the CR2 register: input capture (ICF2 can be set and IC2R can be
– Set the OC1E bit, the OCMP1 pin is then ded- loaded) but the user must take care that the
icated to the Output Compare 1 function. counter is reset each time a valid edge occurs
– Set the OPM bit. on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
– Select the timer clock CC1-CC0 (see Table 14
Clock Control Bits). 6. When the one pulse mode is used OC1R is
dedicated to this mode. Nevertheless OC2R
and OCF2 can be used to indicate a period of
time has been elapsed but cannot generate an
output waveform because the level OLVL2 is
dedicated to the one pulse mode.

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Figure 44. One Pulse Mode Timing Example

COUNTER
.... FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD
2ED3

ICAP1

OLVL2 OLVL1 OLVL2

OCMP1
compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 45. Pulse Width Modulation Mode Timing Example

34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC

COUNTER

OCMP1
OLVL2 OLVL1 OLVL2
compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

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16-BIT TIMER (Cont’d)

6.4.3.7 Pulse Width Modulation Mode The Output Compare 2 event causes the counter
Pulse Width Modulation (PWM) mode enables the to be initialized to FFFCh (See Figure 45).
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation cycle
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R When
register, and so these functionality can not be Counter OCMP1 = OLVL1
used when the PWM mode is activated. = OC1R
Procedure
To use pulse width modulation mode: When OCMP1 = OLVL2
1. Load the OC2R register with the value corre- Counter Counter is reset
sponding to the period of the signal. = OC2R to FFFCh
2. Load the OC1R register with the value corre- ICF1 bit is set
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
Notes:
3. Select the following in the CR1 register:
1. After a write instruction to the OCiHR register,
– Using the OLVL1 bit, select the level to be ap-
the output compare function is inhibited until the
plied to the OCMP1 pin after a successful
OCiLR register is also written.
comparison with OC1R register.
Therefore the Input Capture 1 function is inhib-
– Using the OLVL2 bit, select the level to be ap- ited but the Input Capture 2 is available.
plied to the OCMP1 pin after a successful
2. The OCF1 and OCF2 bits cannot be set by
comparison with OC2R register.
hardware in PWM mode therefore the Output
4. Select the following in the CR2 register: Compare interrupt is inhibited.
– Set OC1E bit: the OCMP1 pin is then dedicat- 3. The ICF1 bit is set by hardware when the coun-
ed to the output compare 1 function. ter reaches the OC2R value and can produce a
– Set the PWM bit. timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Select the timer clock (CC1-CC0) (see Table
14 Clock Control Bits). 4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
If OLVL1=1 and OLVL2=0 the length of the posi-
nected to the timer. The ICAP2 pin can be used
tive pulse is the difference between the OC2R and
to perform input capture (ICF2 can be set and
OC1R registers.
IC2R can be loaded) but the user must take
If OLVL1=OLVL2 a continuous signal will be seen care that the counter is reset each period and
on the OCMP1 pin. ICF1 can also generates interrupt if ICIE is set.
The OCiR register value required for a specific tim- 5. When the Pulse Width Modulation (PWM) and
ing application can be calculated using the follow- One Pulse Mode (OPM) bits are both set, the
ing formula: PWM mode is the only active one.
t * fCPU
OCiR Value = -5
PRESC
Where:
t = Desired output compare period (in sec-
onds)
fCPU = Internal clock frequency
PRESC = Timer prescaler factor (2, 4 or 8 de-
pending on CC1-CC0 bits, see Table 14
Clock Control Bits)

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16-BIT TIMER (Cont’d)

6.4.4 Low Power Modes
Mode Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
HALT reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.

6.4.5 Interrupts
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Input Capture 1 event/Counter reset in PWM mode ICF1 Yes No
ICIE
Input Capture 2 event ICF2 Yes No
Output Compare 1 event (not available in PWM mode) OCF1 Yes No
OCIE
Output Compare 2 event (not available in PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).

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16-BIT TIMER (Cont’d)

6.4.6 Register Description Bit 4 = FOLV2 Forced Output Compare 2.
Each Timer is associated with three control and This bit is set and cleared by software.
status registers, and with six pairs of data registers 0: No effect on the OCMP2 pin.
(16-bit values) relating to the two input captures, 1: Forces the OLVL2 bit to be copied to the
the two output compares, the counter and the al- OCMP2 pin, if the OC2E bit is set and even if
ternate counter. there is no successful comparison.

CONTROL REGISTER 1 (CR1) Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.
Read/Write 0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h) 1: Forces OLVL1 to be copied to the OCMP1 pin, if
7 0
the OC1E bit is set and even if there is no suc-
cessful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable. This bit is copied to the OCMP2 pin whenever a
0: Interrupt is inhibited. successful comparison occurs with the OC2R reg-
1: A timer interrupt is generated whenever the ister and OCxE is set in the CR2 register. This val-
ICF1 or ICF2 bit of the SR register is set. ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited. Bit 1 = IEDG1 Input Edge 1.
1: A timer interrupt is generated whenever the This bit determines which type of level transition
OCF1 or OCF2 bit of the SR register is set. on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF Bit 0 = OLVL1 Output Level 1.
bit of the SR register is set. The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

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16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2) Bit 4 = PWM Pulse Width Modulation.
Read/Write 0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Reset Value: 0000 0000 (00h) programmable cyclic signal; the length of the
7 0
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC1-CC0 Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.
The value of the timer clock depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com- Table 14. Clock Control Bits
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E Timer Clock CC1 CC0
bit, the Output Compare 1 function of the timer re- fCPU / 4 0 0
mains active. fCPU / 2 0 1
0: OCMP1 pin alternate function disabled (I/O pin fCPU / 8 1 0
free for general-purpose I/O).
External Clock (where
1: OCMP1 pin alternate function enabled. 1 1
available)

Bit 6 = OC2E Output Compare 2 Enable.

This bit is used only to output the signal from the Bit 1 = IEDG2 Input Edge 2.
timer on the OCMP2 pin (OLV2 in Output Com- This bit determines which type of level transition
pare mode). Whatever the value of the OC2E bit, on the ICAP2 pin will trigger the capture.
the Output Compare 2 function of the timer re- 0: A falling edge triggers the capture.
mains active. 1: A rising edge triggers the capture.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O). Bit 0 = EXEDG External Clock Edge.
1: OCMP2 pin alternate function enabled. This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
Bit 5 = OPM One Pulse Mode. free running counter.
0: One Pulse Mode is not active. 0: A falling edge triggers the free running counter.
1: One Pulse Mode is active, the ICAP1 pin can be 1: A rising edge triggers the free running counter.
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.

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16-BIT TIMER (Cont’d)

STATUS REGISTER (SR) Bit 2-0 = Reserved, forced by hardware to 0.
Read Only INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Reset Value: 0000 0000 (00h) Read Only
The three least significant bits are not used. Reset Value: Undefined
7 0 This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
ICF1 OCF1 TOF ICF2 OCF2 0 0 0 input capture 1 event).
7 0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value). MSB LSB
1: An input capture has occurred or the counter
has reached the OC2R value in PWM mode. To
clear this bit, first read the SR register, then read
or write the low byte of the IC1R (IC1LR) regis- INPUT CAPTURE 1 LOW REGISTER (IC1LR)
ter. Read Only
Reset Value: Undefined
Bit 6 = OCF1 Output Compare Flag 1. This is an 8-bit read only register that contains the
0: No match (reset value). low part of the counter value (transferred by the in-
1: The content of the free running counter has put capture 1 event).
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read 7 0
or write the low byte of the OC1R (OC1LR) reg-
ister. MSB LSB

Bit 5 = TOF Timer Overflow.

0: No timer overflow (reset value). OUTPUT COMPARE 1 HIGH REGISTER
1: The free running counter rolled over from FFFFh (OC1HR)
to 0000h. To clear this bit, first read the SR reg- Read/Write
ister, then read or write the low byte of the CR Reset Value: 1000 0000 (80h)
(CLR) register. This is an 8-bit register that contains the high part
Note: Reading or writing the ACLR register does of the value to be compared to the CHR register.
not clear TOF.
7 0

Bit 4 = ICF2 Input Capture Flag 2. MSB LSB

0: No input capture (reset value).
1: An input capture has occurred.To clear this bit,
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register. OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Bit 3 = OCF2 Output Compare Flag 2. Read/Write
0: No match (reset value). Reset Value: 0000 0000 (00h)
1: The content of the free running counter has
matched the content of the OC2R register. To This is an 8-bit register that contains the low part of
clear this bit, first read the SR register, then read the value to be compared to the CLR register.
or write the low byte of the OC2R (OC2LR) reg- 7 0
ister.
MSB LSB

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16-BIT TIMER (Cont’d)

OUTPUT COMPARE 2 HIGH REGISTER ALTERNATE COUNTER HIGH REGISTER
(OC2HR) (ACHR)
Read/Write Read Only
Reset Value: 1000 0000 (80h) Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part This is an 8-bit register that contains the high part
of the value to be compared to the CHR register. of the counter value.
7 0 7 0

MSB LSB MSB LSB

OUTPUT COMPARE 2 LOW REGISTER ALTERNATE COUNTER LOW REGISTER

(OC2LR) (ACLR)
Read/Write Read Only
Reset Value: 0000 0000 (00h) Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of This is an 8-bit register that contains the low part of
the value to be compared to the CLR register. the counter value. A write to this register resets the
counter. An access to this register after an access
7 0 to SR register does not clear the TOF bit in SR
register.
MSB LSB
7 0

COUNTER HIGH REGISTER (CHR) MSB LSB

Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value. Read Only
Reset Value: Undefined
7 0 This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
MSB LSB Input Capture 2 event).
7 0

COUNTER LOW REGISTER (CLR) MSB LSB

Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of INPUT CAPTURE 2 LOW REGISTER (IC2LR)
the counter value. A write to this register resets the
counter. An access to this register after accessing Read Only
the SR register clears the TOF bit. Reset Value: Undefined
This is an 8-bit read only register that contains the
7 0 low part of the counter value (transferred by the In-
put Capture 2 event).
MSB LSB
7 0

MSB LSB

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16-BIT TIMER (Cont’d)

Table 15. 16-Bit Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

Timer A: 32 CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Timer B: 42 Reset Value 0 0 0 0 0 0 0 0
Timer A: 31 CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer B: 41 Reset Value 0 0 0 0 0 0 0 0
Timer A: 33 SR ICF1 OCF1 TOF ICF2 OCF2 - - -
Timer B: 43 Reset Value 0 0 0 0 0 0 0 0
Timer A: 34 ICHR1 MSB LSB
- - - - - -
Timer B: 44 Reset Value - -

Timer A: 35 ICLR1 MSB LSB

- - - - - -
Timer B: 45 Reset Value - -

Timer A: 36 OCHR1 MSB LSB

- - - - - -
Timer B: 46 Reset Value - -

Timer A: 37 OCLR1 MSB LSB

- - - - - -
Timer B: 47 Reset Value - -

Timer A: 3E OCHR2 MSB LSB

- - - - - -
Timer B: 4E Reset Value - -

Timer A: 3F OCLR2 MSB LSB

- - - - - -
Timer B: 4F Reset Value - -

Timer A: 38 CHR MSB LSB

Timer B: 48 Reset Value 1 1 1 1 1 1 1 1

Timer A: 39 CLR MSB LSB

Timer B: 49 Reset Value 1 1 1 1 1 1 0 0

Timer A: 3A ACHR MSB LSB

Timer B: 4A Reset Value 1 1 1 1 1 1 1 1

Timer A: 3B ACLR MSB LSB

Timer B: 4B Reset Value 1 1 1 1 1 1 0 0

Timer A: 3C ICHR2 MSB LSB

- - - - - -
Timer B: 4C Reset Value - -

Timer A: 3D ICLR2 MSB LSB

- - - - - -
Timer B: 4D Reset Value - -

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6.5 SERIAL PERIPHERAL INTERFACE (SPI)

6.5.1 Introduction 6.5.3 General description
The Serial Peripheral Interface (SPI) allows full- The SPI is connected to external devices through
duplex, synchronous, serial communication with 4 alternate pins:
external devices. An SPI system may consist of a – MISO: Master In Slave Out pin
master and one or more slaves or a system in
which devices may be either masters or slaves. – MOSI: Master Out Slave In pin
The SPI is normally used for communication be- – SCK: Serial Clock pin
tween the microcontroller and external peripherals – SS: Slave select pin
or another microcontroller.
Refer to the Pin Description chapter for the device- A basic example of interconnections between a
specific pin-out. single master and a single slave is illustrated on
Figure 46.
6.5.2 Main Features The MOSI pins are connected together as are
■ Full duplex, three-wire synchronous transfers MISO pins. In this way data is transferred serially
between master and slave (most significant bit
■ Master or slave operation
first).
■ Four master mode frequencies
When the master device transmits data to a slave
■ Maximum slave mode frequency = fCPU/2.
device via MOSI pin, the slave device responds by
■ Four programmable master bit rates sending data to the master device via the MISO
■ Programmable clock polarity and phase pin. This implies full duplex transmission with both
■ End of transfer interrupt flag
data out and data in synchronized with the same
clock signal (which is provided by the master de-
■ Write collision flag protection vice via the SCK pin).
■ Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 49) but master and slave
must be programmed with the same timing mode.
Figure 46. Serial Peripheral Interface Master/Slave

MASTER SLAVE

MSBit LSBit MSBit LSBit

MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI
SCK SCK
CLOCK
GENERATOR
SS +5V SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 47. Serial Peripheral Interface Block Diagram

Internal Bus

Read
DR

Read Buffer IT
request
MOSI
SR
MISO 8-Bit Shift Register
SPIF WCOL - MODF - - - -

Write

SPI
STATE
SCK
CONTROL
SS

CR

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER
CONTROL

SERIAL
CLOCK
GENERATOR

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SERIAL PERIPHERAL INTERFACE (Cont’d)

6.5.4 Functional Description In this configuration the MOSI pin is a data output
Figure 46 shows the serial peripheral interface and to the MISO pin is a data input.
(SPI) block diagram.
This interface contains 3 dedicated registers: Transmit sequence
– A Control Register (CR) The transmit sequence begins when a byte is writ-
– A Status Register (SR) ten the DR register.
– A Data Register (DR) The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
Refer to the CR, SR and DR registers in Section and then shifted out serially to the MOSI pin most
6.5.7for the bit definitions. significant bit first.

6.5.4.1 Master Configuration When data transfer is complete:

In a master configuration, the serial clock is gener- – The SPIF bit is set by hardware
ated on the SCK pin.
– An interrupt is generated if the SPIE bit is set
Procedure and the I bit in the CCR register is cleared.
– Select the SPR0 & SPR1 bits to define the se- During the last clock cycle the SPIF bit is set, a
rial clock baud rate (see CR register). copy of the data byte received in the shift register
– Select the CPOL and CPHA bits to define one is moved to a buffer. When the DR register is read,
of the four relationships between the data the SPI peripheral returns this buffered value.
transfer and the serial clock (see Figure 49). Clearing the SPIF bit is performed by the following
– The SS pin must be connected to a high level software sequence:
signal during the complete byte transmit se- 1. An access to the SR register while the SPIF bit
quence. is set
– The MSTR and SPE bits must be set (they re- 2. A write or a read of the DR register.
main set only if the SS pin is connected to a
high level signal). Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

6.5.4.2 Slave Configuration When data transfer is complete:
In slave configuration, the serial clock is received – The SPIF bit is set by hardware
on the SCK pin from the master device. – An interrupt is generated if SPIE bit is set and
The value of the SPR0 & SPR1 bits is not used for I bit in CCR register is cleared.
the data transfer. During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
Procedure is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– For correct data transfer, the slave device
must be in the same timing mode as the mas- Clearing the SPIF bit is performed by the following
ter device (CPOL and CPHA bits). See Figure software sequence:
49. 1. An access to the SR register while the SPIF bit
– The SS pin must be connected to a low level is set.
signal during the complete byte transmit se- 2. A write or a read of the DR register.
quence.
– Clear the MSTR bit and set the SPE bit to as- Notes: While the SPIF bit is set, all writes to the
sign the pins to alternate function. DR register are inhibited until the SR register is
In this configuration the MOSI pin is a data input read.
and the MISO pin is a data output. The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
Transmit Sequence the second SPIF bit in order to prevent an overrun
condition (see Section 6.5.4.6).
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle Depending on the CPHA bit, the SS pin has to be
and then shifted out serially to the MISO pin most set to write to the DR register between each data
significant bit first. byte transfer to avoid a write collision (see Section
6.5.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

6.5.4.3 Data Transfer Format The master device applies data to its MOSI pin-
During an SPI transfer, data is simultaneously clock edge before the capture clock edge.
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn- CPHA bit is set
chronize the data transfer during a sequence of
eight clock pulses. The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
The SS pin allows individual selection of a slave set) is the MSBit capture strobe. Data is latched on
device; the other slave devices that are not select- the occurrence of the first clock transition.
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Clock Phase and Clock Polarity Figure 48).
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits. CPHA bit is reset
The CPOL (clock polarity) bit controls the steady The first edge on the SCK pin (falling edge if CPOL
state value of the clock when no data is being bit is set, rising edge if CPOL bit is reset) is the
transferred. This bit affects both master and slave MSBit capture strobe. Data is latched on the oc-
modes. currence of the second clock transition.
The combination between the CPOL and CPHA This pin must be toggled high and low between
(clock phase) bits selects the data capture clock each byte transmitted (see Figure 48).
edge.
To protect the transmission from a write collision a
Figure 49, shows an SPI transfer with the four low value on the SS pin of a slave device freezes
combinations of the CPHA and CPOL bits. The di- the data in its DR register and does not allow it to
agram may be interpreted as a master or slave be altered. Therefore the SS pin must be high to
timing diagram where the SCK pin, the MISO pin, write a new data byte in the DR without producing
the MOSI pin are directly connected between the a write collision.
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.

Figure 48. CPHA / SS Timing Diagram

MOSI/MISO Byte 1 Byte 2 Byte 3

Master SS

Slave SS
(CPHA=0)

Slave SS
(CPHA=1)
VR02131A

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 49. Data Clock Timing Diagram

CPHA =1
CPOL = 1

CPOL = 0

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO
(from master)

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MOSI
(from slave)

SS
(to slave)
CAPTURE STROBE

CPHA =0

CPOL = 1

CPOL = 0

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter. VR02131B

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SERIAL PERIPHERAL INTERFACE (Cont’d)

6.5.4.4 Write Collision Error When the CPHA bit is reset:
A write collision occurs when the software tries to Data is latched on the occurrence of the first clock
write to the DR register while a data transfer is tak- transition. The slave device does not have any
ing place with an external device. When this hap- way of knowing when that transition will occur;
pens, the transfer continues uninterrupted; and therefore, the slave device collision occurs when
the software write will be unsuccessful. software attempts to write the DR register after its
Write collisions can occur both in master and slave SS pin has been pulled low.
mode. For this reason, the SS pin must be high, between
Note: a ”read collision” will never occur since the each data byte transfer, to allow the CPU to write
received data byte is placed in a buffer in which in the DR register without generating a write colli-
access is always synchronous with the MCU oper- sion.
ation.
In Slave mode In Master mode
When the CPHA bit is set: Collision in the master device is defined as a write
The slave device will receive a clock (SCK) edge of the DR register while the internal serial clock
prior to the latch of the first data transfer. This first (SCK) is in the process of transfer.
clock edge will freeze the data in the slave device The SS pin signal must be always high on the
DR register and output the MSBit on to the exter- master device.
nal MISO pin of the slave device.
The SS pin low state enables the slave device but WCOL bit
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock The WCOL bit in the SR register is set if a write
edge. collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 50).

Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SR Read SR
1st Step
OR
THEN
THEN SPIF =0
2nd Step Read DR SPIF =0 Write DR WCOL=0 if no transfer has started
WCOL=0 WCOL=1 if a transfer has started
before the 2nd step

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SR
1st Step

THEN
Note: Writing in DR register in-
2nd Step Read DR WCOL=0 stead of reading in it do not reset
WCOL bit

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6.5.4.5 Master Mode Fault may be restored to their original state during or af-
Master mode fault occurs when the master device ter this clearing sequence.
has its SS pin pulled low, then the MODF bit is set. Hardware does not allow the user to set the SPE
Master mode fault affects the SPI peripheral in the and MSTR bits while the MODF bit is set except in
following ways: the MODF bit clearing sequence.
– The MODF bit is set and an SPI interrupt is In a slave device the MODF bit can not be set, but
generated if the SPIE bit is set. in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph- The MODF bit indicates that there might have
eral. been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
– The MSTR bit is reset, thus forcing the device set or default system state using an interrupt rou-
into slave mode. tine.

Clearing the MODF bit is done through a software 6.5.4.6 Overrun Condition
sequence:
An overrun condition occurs, when the master de-
1. A read or write access to the SR register while vice has sent several data bytes and the slave de-
the MODF bit is set. vice has not cleared the SPIF bit issuing from the
2. A write to the CR register. previous data byte transmitted.
In this case, the receiver buffer contains the byte
Notes: To avoid any multiple slave conflicts in the sent after the SPIF bit was last cleared. A read to
case of a system comprising several MCUs, the the DR register returns this byte. All other bytes
SS pin must be pulled high during the clearing se- are lost.
quence of the MODF bit. The SPE and MSTR bits This condition is not detected by the SPI peripher-
al.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

6.5.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems: For more security, the slave device may respond
– Single Master System to the master with the received data byte. Then the
master will receive the previous byte back from the
– Multimaster System slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
Single Master System
Other transmission security methods can use
A typical single master system may be configured,
ports for handshake lines or data bytes with com-
using an MCU as the master and four MCUs as
mand fields.
slaves (see Figure 51).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control A multi-master system may also be configured by
the four SS pins of the slave devices. the user. Transfer of master control could be im-
plemented using a handshake method through the
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at I/O ports or by an exchange of code messages
through the serial peripheral interface system.
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
Note: To prevent a bus conflict on the MISO line in the SR register.
the master allows only one slave device during a
transmission.
Figure 51. Single Master Configuration

SS SS SS SS
SCK SCK SCK SCK
Slave Slave Slave Slave
MCU MCU MCU MCU

MOSI MISO MOSI MISO MOSI MISO MOSI MISO

MOSI MISO
SCK
Ports

Master
MCU

5V SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

6.5.5 Low Power Modes
Mode Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
HALT In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.

6.5.6 Interrupts

Enable Exit Exit

Event
Interrupt Event Control from from
Flag
Bit Wait Halt
SPI End of Transfer Event SPIF Yes No
SPIE
Master Mode Fault Event MODF Yes No

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

6.5.7 Register Description
CONTROL REGISTER (CR)
Read/Write Bit 3 = CPOL Clock polarity.
Reset Value: 0000xxxx (0xh) This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
7 0 CPOL bit affects both the master and slave
modes.
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software. Bit 2 = CPHA Clock phase.
0: Interrupt is inhibited This bit is set and cleared by software.
1: An SPI interrupt is generated whenever SPIF=1 0: The first clock transition is the first data capture
or MODF=1 in the SR register edge.
1: The second clock transition is the first capture
Bit 6 = SPE Serial peripheral output enable. edge.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0 Bit 1:0 = SPR[1:0] Serial peripheral rate.
(see Section 6.5.4.5 Master Mode Fault). These bits are set and cleared by software.Used
0: I/O port connected to pins with the SPR2 bit, they select one of six baud rates
1: SPI alternate functions connected to pins to be used as the serial clock when the device is a
The SPE bit is cleared by reset, so the SPI periph- master.
eral is not initially connected to the external pins. These 2 bits have no effect in slave mode.
Table 16. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable.
this bit is set and cleared by software and it is Serial Clock SPR2 SPR1 SPR0
cleared by reset. It is used with the SPR[1:0] bits to fCPU/2 1 0 0
set the baud rate. Refer to Table 16. fCPU/8 0 0 0
0: Divider by 2 enabled
fCPU/16 0 0 1
1: Divider by 2 disabled
fCPU/32 1 1 0
fCPU/64 0 1 0
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also fCPU/128 0 1 1
cleared by hardware when, in master mode, SS=0
(see Section 6.5.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.

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STATUS REGISTER (SR) DATA I/O REGISTER (DR)
Read Only Read/Write
Reset Value: 0000 0000 (00h) Reset Value: Undefined
7 0 7 0

SPIF WCOL - MODF - - - - D7 D6 D5 D4 D3 D2 D1 D0

Bit 7 = SPIF Serial Peripheral data transfer flag. The DR register is used to transmit and receive
This bit is set by hardware when a transfer has data on the serial bus. In the master device only a
been completed. An interrupt is generated if write to this register will initiate transmission/re-
SPIE=1 in the CR register. It is cleared by a soft- ception of another byte.
ware sequence (an access to the SR register fol- Notes: During the last clock cycle the SPIF bit is
lowed by a read or write to the DR register). set, a copy of the received data byte in the shift
0: Data transfer is in progress or has been ap- register is moved to a buffer. When the user reads
proved by a clearing sequence. the serial peripheral data I/O register, the buffer is
1: Data transfer between the device and an exter- actually being read.
nal device has been completed.
Warning:
Note: While the SPIF bit is set, all writes to the DR
register are inhibited. A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value lo-
Bit 6 = WCOL Write Collision status. cated in the buffer and not the contents of the shift
This bit is set by hardware when a write to the DR register (See Figure 47 ).
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 50).
0: No write collision occurred
1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF Mode Fault flag.

This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 6.5.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected

Bits 3-0 = Unused.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 17. SPI Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

SPIDR MSB LSB

0021h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0022h
Reset Value 0 0 0 0 x x x x

SPISR SPIF WCOL MODF

0023h
Reset Value 0 0 0 0 0 0 0 0

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6.6 SERIAL COMMUNICATIONS INTERFACE (SCI)

6.6.1 Introduction 6.6.3 General Description
The Serial Communications Interface (SCI) offers The interface is externally connected to another
a flexible means of full-duplex data exchange with device by two pins (see Figure 53):
external equipment requiring an industry standard – TDO: Transmit Data Output. When the transmit-
NRZ asynchronous serial data format. The SCI of- ter is disabled, the output pin returns to its I/O
fers a very wide range of baud rates using two port configuration. When the transmitter is ena-
baud rate generator systems. bled and nothing is to be transmitted, the TDO
6.6.2 Main Features pin is at high level.
■ Full duplex, asynchronous communications – RDI: Receive Data Input is the serial data input.
■ NRZ standard format (Mark/Space) Oversampling techniques are used for data re-
■ Dual baud rate generator systems
covery by discriminating between valid incoming
data and noise.
■ Independently programmable transmit and
receive baud rates up to 250K baud. Through this pins, serial data is transmitted and re-
ceived as frames comprising:
■ Programmable data word length (8 or 9 bits)
– An Idle Line prior to transmission or reception
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags – A start bit
■ Two receiver wake-up modes: – A data word (8 or 9 bits) least significant bit first
– Address bit (MSB) – A Stop bit indicating that the frame is complete.
– Idle line This interface usestwo types of baud rate generator:
■ Muting functionfor multiprocessor configurations – A conventional type for commonly-used baud
■ Separate enable bits for Transmitter and rates,
Receiver – An extended type with a prescaler offering a very
■ Three error detection flags: wide range of baud rates even with non-standard
– Overrun error oscillator frequencies.
– Noise error
– Frame error
■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 52. SCI Block Diagram

Write Read (DATA REGIST ER) DR

Transmit Data Register (TDR) Received Data Register (RDR)

TDO

Transmit Shift Register Received Shift Register

RDI

CR1
R8 T8 - M WAKE - - -

WAKE
TRANSMIT UP RECEIVE R RECEIVER
CONTROL UNIT CONTROL CLOCK

CR2 SR
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE -

SCI
INTERRUPT
CONTROL

TRANSMIT TER
CLOCK

TRANS MITTER RATE

CONTROL
fCPU
/16 /2 /PR
BRR
SCP1 SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVEN TIONAL BAUD RATE GENERATOR

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

6.6.4 Functional Description 6.6.4.1 Serial Data Format
The block diagram of the Serial Control Interface, Word length may be selected as being either 8 or 9
is shown in Figure 52. It contains 6 dedicated reg- bits by programming the M bit in the CR1 register
isters: (see Figure 52).
– Two control registers (CR1 & CR2) The TDO pin is in low state during the start bit.
– A status register (SR) The TDO pin is in high state during the stop bit.
– A baud rate register (BRR) An Idle character is interpreted as an entire frame
– An extended prescaler receiver register (ERPR) of “1”s followed by the start bit of the next frame
which contains data.
– Anextendedprescalertransmitter register (ETPR)
A Break character is interpreted on receiving “0”s
Refer to the register descriptions in Section for some multiple of the frame period. At the end of
6.6.7for the definitions of each bit. the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 53. Word length programming

9-bit Word length (M bit is set)

Possible Next Data Frame
Parity
Data Frame Bit Next
Start
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Stop Start
Bit
Bit Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

8-bit Word length (M bit is reset)

Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

6.6.4.2 Transmitter When a frame transmission is complete (after the
The transmitter can send data words of either 8 or stop bit or after the break frame) the TC bit is set
9 bits depending on the M bit status. When the M and an interrupt is generated if the TCIE is set and
bit is set, word length is 9 bits and the 9th bit (the the I bit is cleared in the CCR register.
MSB) has to be stored in the T8 bit in the CR1 reg- Clearing the TC bit is performed by the following
ister. software sequence:
Character Transmission 1. An access to the SR register
2. A write to the DR register
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode, Note: The TDRE and TC bits are cleared by the
the DR register consists of a buffer (TDR) between same software sequence.
the internal bus and the transmit shift register (see Break Characters
Figure 52). Setting the SBK bit loads the shift register with a
Procedure break character. The break frame length depends
– Select the M bit to define the word length. on the M bit (see Figure 53).
– Select the desired baud rate using the BRR and As long as the SBK bit is set, the SCI send break
the ETPR registers. frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
– Set the TE bit to assign the TDO pin to the alter- the last break frame to guarantee the recognition
nate function and to send a idle frame as first of the start bit of the next frame.
transmission.
Idle Characters
– Access the SR register and write the data to
send in the DR register (this sequence clears the Setting the TE bit drives the SCI to send an idle
TDRE bit). Repeat this sequence for each data to frame before the first data frame.
be transmitted. Clearing and then setting the TE bit during a trans-
Clearing the TDRE bit is always performed by the mission sends an idle frame after the current word.
following software sequence: Note: Resetting and setting the TE bit causes the
1. An access to the SR register data in the TDR register to be lost. Therefore the
2. A write to the DR register best time to toggle the TE bit is when the TDRE bit
The TDRE bit is set by hardware and it indicates: is set i.e. before writing the next byte in the DR.
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

6.6.4.3 Receiver Overrun Error
The SCI can receive data words of either 8 or 9 An overrun error occurs when a character is re-
bits. When the M bit is set, word length is 9 bits ceived when RDRF has not been reset. Data can
and the MSB is stored in the R8 bit in the CR1 reg- not be transferred from the shift register to the
ister. TDR register as long as the RDRF bit is not
Character reception cleared.
During a SCI reception, data shifts in least signifi- When a overrun error occurs:
cant bit first through the RDI pin. In this mode, DR – The OR bit is set.
register consists in a buffer (RDR) between the in- – The RDR content will not be lost.
ternal bus and the received shift register (see Fig-
ure 52). – The shift register will be overwritten.
Procedure – An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Select the M bit to define the word length.
The OR bit is reset by an access to the SR register
– Select the desired baud rate using the BRR and followed by a DR register read operation.
the ERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit. Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
When a character is received: and noise.
– The RDRF bit is set. It indicates that the content When noise is detected in a frame:
of the shift register is transferred to the RDR.
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register. – Data is transferred from the Shift register to the
DR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re- – No interrupt is generated. However this bit rises
ception. at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by: The NF bit is reset by a SR register read operation
followed by a DR register read operation.
1. An access to the SR register
Framing Error
2. A read to the DR register.
A framing error is detected when:
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun – The stop bit is not recognized on reception at the
error. expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SPI han-
dles it as a framing error. When the framing error is detected:
Idle Character – the FE bit is set by hardware
When a idle frame is detected, there is the same – Data is transferred from the Shift register to the
procedure as a data received character plus an in- DR register.
terrupt if the ILIE bit is set and the I bit is cleared in – No interrupt is generated. However this bit rises
the CCR register. at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram

EXTE NDED PRESCALER TRANSMITTE R RATE CONTROL

ETPR
EXTE NDED TRANS MITTER PRESCALE R REGISTER

ERPR
EXTE NDED RECEIVER PRESCALER REGISTER

EXTE NDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

fCPU TRANSMI TTER

CLOCK

TRANSMIT TER RATE

CONTROL
/16 /2 /PR
BRR
SCP1 SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER
CLOCK

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

6.6.4.4 Conventional Baud Rate Generation than zero. The baud rates are calculated as fol-
The baud rate for the receiver and transmitter (Rx lows:
and Tx) are set independently and calculated as
follows: fCPU fCPU
Tx = Rx =
fCPU fCPU 16*ETPR 16*ERPR
Tx = Rx =
(32*PR)*TR (32*PR)*RR
with:
with: ETPR = 1,..,255 (see ETPR register)
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) ERPR = 1,.. 255 (see ERPR register)
TR = 1, 2, 4, 8, 16, 32, 64,128 6.6.4.6 Receiver Muting and Wake-up Feature
(see SCT0, SCT1 & SCT2 bits) In multiprocessor configurations it is often desira-
RR = 1, 2, 4, 8, 16, 32, 64,128 ble that only the intended message recipient
(see SCR0,SCR1 & SCR2 bits) should actively receive the full message contents,
thus reducing redundant SCI service overhead for
All this bits are in the BRR register. all non addressed receivers.
Example: If fCPU is 8 MHz (normal mode) and if The non addressed devices may be placed in
PR=13 and TR=RR=1, the transmit and receive sleep mode by means of the muting function.
baud rates are 19200 baud.
Setting the RWU bit by software puts the SCI in
Note: the baud rate registers MUST NOT be sleep mode:
changed while the transmitter or the receiver is en-
abled. All the reception status bits can not be set.
6.6.4.5 Extended Baud Rate Generation All the receive interrupt are inhibited.
The extended prescaler option gives a very fine A muted receiver may be awakened by one of the
tuning on the baud rate, using a 255 value prescal- following two ways:
er, whereas the conventional Baud Rate Genera- – by Idle Line detection if the WAKE bit is reset,
tor retains industry standard software compatibili- – by Address Mark detection if the WAKE bit is set.
ty.
Receiver wakes-up by Idle Line detection when
The extended baud rate generator block diagram the Receive line has recognised an Idle Frame.
is described in the Figure 54. Then the RWU bit is reset by hardware but the
The output clock rate sent to the transmitter or to IDLE bit is not set.
the receiver will be the output from the 16 divider Receiver wakes-up by Address Mark detection
divided by a factor ranging from 1 to 255 set in the when it received a “1” as the most significant bit of
ERPR or the ETPR register. a word, thus indicating that the message is an ad-
Note: the extended prescaler is activated by set- dress. The reception of this particular word wakes
ting the ETPR or ERPR register to a value other up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

6.6.5 Low Power Modes
Mode Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

6.6.6 Interrupts
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Transmit Data Register Empty TDRE TIE Yes No
Transmission Complete TC TCIE Yes No
Received Data Ready to be Read RDRF Yes No
RIE
Overrrun Error Detected OR Yes No
Idle Line Detected IDLE ILIE Yes No

The SCI interrupt events are connected to the These events generate an interrupt if the corre-
same interrupt vector (see Interrupts chapter). sponding Enable Control Bit is set and the I-bit in
the CC register is reset (RIM instruction).

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

6.6.7 Register Description Note: The IDLE bit will not be set again until the
STATUS REGISTER (SR) RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
Read Only ceiver wakes up from wake-up mode.
Reset Value: 1100 0000 (C0h)
7 0 Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
TDRE TC RDRF IDLE OR NF FE - being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
Bit 7 = TDRE Transmit data register empty. ister. It is cleared by hardware when RE=0 by a
This bit is set by hardware when the content of the software sequence (an access to the SR register
TDR register has been transferred into the shift followed by a read to the DR register).
register. An interrupt is generated if the TIE =1 in 0: No Overrun error
the CR2 register. It is cleared by a software se- 1: Overrun error is detected
quence (an access to the SR register followed by a
write to the DR register).
0: Data is not transferred to the shift register Note: When this bit is set RDR register content will
1: Data is transferred to the shift register not be lost but the shift register will be overwritten.
Note: data will not be transferred to the shift regis- Bit 2 = NF Noise flag.
ter as long as the TDRE bit is not reset. This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
Bit 6 = TC Transmission complete. the SR register followed by a read to the DR regis-
This bit is set by hardware when transmission of a ter).
frame containing Data, a Preamble or a Break is 0: No noise is detected
complete. An interrupt is generated if TCIE=1 in 1: Noise is detected
the CR2 register. It is cleared by a software se- Note: This bit does not generate interrupt as it ap-
quence (an access to the SR register followed by a pears at the same time as the RDRF bit which it-
write to the DR register). self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
Bit 5 = RDRF Received data ready flag. This bit is set by hardware when a de-synchroniza-
This bit is set by hardware when the content of the tion, excessive noise or a break character is de-
RDR register has been transferred into the DR tected. It is cleared by hardware when RE=0 by a
register. An interrupt is generated if RIE=1 in the software sequence (an access to the SR register
CR2 register. It is cleared by hardware when followed by a read to the DR register).
RE=0 or by a software sequence (an access to the 0: No Framing error is detected
SR register followed by a read to the DR register). 1: Framing error or break character is detected
0: Data is not received Note: This bit does not generate interrupt as it ap-
1: Received data is ready to be read pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
Bit 4 = IDLE Idle line detect. being transferred causes both frame error and
This bit is set by hardware when a Idle Line is de- overrun error, it will be transferred and only the OR
tected. An interrupt is generated if the ILIE=1 in bit will be set.
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the Bit 0 = Unused.
SR register followed by a read to the DR register).
0: No Idle Line is detected
1: Idle Line is detected

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (CR1) 1: An SCI interrupt is generated whenever TC=1 in
Read/Write the SR register
Reset Value: Undefined
Bit 5 = RIE Receiver interrupt enable.
7 0 This bit is set and cleared by software.
0: interrupt is inhibited
R8 T8 - M WAK E - - - 1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received Bit 4 = ILIE Idle line interrupt enable.
word when M=1. This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
Bit 6 = T8 Transmit data bit 8. in the SR register.
This bit is used to store the 9th bit of the transmit-
ted word when M=1. Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
Bit 4 = M Word length.
cleared by software.
This bit determines the word length. It is set or
0: Transmitter is disabled, the TDO pin is back to
cleared by software.
the I/O port configuration.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: Transmitter is enabled
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
Bit 3 = WAKE Wake-Up method. current word.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line Bit 2 = RE Receiver enable.
1: Address Mark This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
CONTROL REGISTER 2 (CR2) OR, NF and FE bits of the SR register.
Read/Write 1: Receiver is enabled and begins searching for a
start bit.
Reset Value: 0000 0000 (00h)
7 0 Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
TIE TCIE RIE ILIE TE RE RWU SBK not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
Bit 7 = TIE Transmitter interrupt enable. 0: Receiver in active mode
This bit is set and cleared by software. 1: Receiver in mute mode
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register. Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
Bit 6 = TCIE Transmission complete interrupt ena- 0: No break character is transmitted
ble 1: Break characters are transmitted
This bit is set and cleared by software. Note: If the SBK bit is set to “1” and then to “0”, the
0: interrupt is inhibited transmitter will send a BREAK word at the end of
the current word.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (DR) Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write These 3 bits, in conjunction with the SCP1 & SCP0
Reset Value: Undefined bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
Contains the Received or Transmitted data char- al Baud Rate Generator mode.
acter, depending on whether it is read from or writ-
ten to. TR dividi ng factor SCT2 SCT1 SCT0
1 0 0 0
7 0
2 0 0 1
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 4 0 1 0
8 0 1 1
The Data register performs a double function (read 16 1 0 0
and write) since it is composed of two registers, 32 1 0 1
one for transmission (TDR) and one for reception
(RDR). 64 1 1 0
The TDR register provides the parallel interface 128 1 1 1
between the internal bus and the output shift reg-
ister (see Figure 52). Note: this TR factor is used only when the ETPR
The RDR register provides the parallel interface fine tuning factor is equal to 00h; otherwise, TR is
between the input shift register and the internal replaced by the ETPR dividing factor.
bus (see Figure 52).
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
BAUD RATE REGISTER (BRR)
These 3 bits, in conjunction with the SCP1 & SCP0
Read/Write bits define the total division applied to the bus
Reset Value: 00xx xxxx (XXh) clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
7 0
RR dividi ng factor SCR2 SCR1 SCR0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 1 0 0 0
2 0 0 1
Bit 7:6= SCP[1:0] First SCI Prescaler 4 0 1 0
These 2 prescaling bits allow several standard
8 0 1 1
clock division ranges:
16 1 0 0
PR Prescaling factor SCP1 SCP0
32 1 0 1
1 0 0 64 1 1 0
3 0 1
128 1 1 1
4 1 0
13 1 1 Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ERPR) REGISTER (ETPR)
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit. sion factor for the transmit circuit.
7 0 7 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres- Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register. caler Register.
The extended Baud Rate Generator is activated The extended Baud Rate Generator is activated
when a value different from 00h is stored in this when a value different from 00h is stored in this
register. Therefore the clock frequency issued register. Therefore the clock frequency issued
from the 16 divider (see Figure 54) is divided by from the 16 divider (see Figure 54) is divided by
the binary factor set in the ERPR register (in the the binary factor set in the ETPR register (in the
range 1 to 255). range 1 to 255).
The extended baud rate generator is not used af- The extended baud rate generator is not used af-
ter a reset. ter a reset.

Table 18. SCI Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

SCISR TDRE TC RDRF IDLE OR NF FE

0050h
Reset Value 1 1 0 0 0 0 0 0
SCIDR MSB LSB
0051h
Reset Value x x x x x x x x
SCIBRR SOG VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV
0052h
Reset Value 0 0 x x x x x x
SCICR1 R8 T8 M WAKE
0053h
Reset Value x x 0 x x 0 0 0
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
0054h
Reset Value 0 0 0 0 0 0 0 0
SCIPBRR MSB LSB
0055h
Reset Value 0 0 0 0 0 0 0 0
SCIPBRT MSB LSB
0057h
Reset Value 0 0 0 0 0 0 0 0

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6.7 8-BIT A/D CONVERTER (ADC)

6.7.1 Introduction 6.7.3 Functional Description

The on-chip Analog to Digital Converter (ADC) pe- 6.7.3.1 Analog Power Supply
ripheral is a 8-bit, successive approximation con- VDDA and VSSA are the high and low level refer-
verter with internal sample and hold circuitry. This ence voltage pins. In some devices (refer to device
peripheral has up to 16 multiplexed analog input pin out description) they are internally connected
channels (refer to device pin out description) that to the VDD and VSS pins.
allow the peripheral to convert the analog voltage
levels from up to 16 different sources. Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
The result of the conversion is stored in a 8-bit loaded or badly decoupled power supply lines.
Data Register. The A/D converter is controlled
through a Control/Status Register. Figure 55. Recommended Ext. Connections
6.7.2 Main Features
■ 8-bit conversion VDD VDDA
■ Up to 16 channels with multiplexed input 0.1pF
VSSA
■ Linear successive approximation

■ Data register (DR) which contains the results ST7

■ Conversion complete status flag RAIN
■ On/off bit (to reduce consumption) VAIN Px.x/AINx
The block diagram is shown in Figure 56.

Figure 56. ADC Block Diagram

fCPU fADC
DIV 2

COCO 0 ADON 0 CH3 CH2 CH1 CH0 ADCCSR

AIN0
HOLD CONTROL

AIN1 RADC
ANALOG ANALOG TO DIGITAL
MUX CONVERTER

AINx
CSAMPLE

ADCDR D7 D6 D5 D4 D3 D2 D1 D0

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8-BIT A/D CONVERTER (ADC) (Cont’d)

6.7.3.2 Digital A/D Conversion Result The analog input ports must be configured as in-
The conversion is monotonic, meaning that the re- put, no pull-up, no interrupt. Refer to the «I/O
sult never decreases if the analog input does not ports» chapter. Using these pins as analog inputs
and never increases if the analog input does not. does not affect the ability of the port to be read as
a logic input.
If the input voltage (VAIN) is greater than or equal
to VDDA (high-level voltage reference) then the In the CSR register:
conversion result in the DR register is FFh (full – Select the CH[3:0] bits to assign the analog
scale) without overflow indication. channel to convert.
If input voltage (VAIN ) is lower than or equal to ADC Conversion
VSSA (low-level voltage reference) then the con- In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
The A/D converter is linear and the digital result of and to start the first conversion. From this time
the conversion is stored in the ADCDR register. on, the ADC performs a continuous conver-
The accuracy of the conversion is described in the sion of the selected channel.
Electrical Characteristics Section. When a conversion is complete
RAIN is the maximum recommended impedance – The COCO bit is set by hardware.
for an analog input signal. If the impedance is too – No interrupt is generated.
high, this will result in a loss of accuracy due to – The result is in the DR register and remains
leakage and sampling not being completed in the valid until the next conversion has ended.
alloted time. A write to the CSR register (with ADON set) aborts
6.7.3.3 A/D Conversion Phases the current conversion, resets the COCO bit and
The A/D conversion is based on two conversion starts a new conversion.
phases as shown in Figure 57:
Figure 57. ADC Conversion Timings
■ Sample capacitor loading
[duration: tLOAD]
During this phase, the VAIN input voltage to be ADON
measured is loaded into the CSAMPLE sample ADCCSR WRITE
capacitor. tCONV OPERATION

■ A/D conversion
[duration: tCONV] HOLD
During this phase, the A/D conversion is CONTROL
computed (8 successive approximations cycles)
and the CSAMPLE sample capacitor is
disconnected from the analog input pin to get COCO BIT SET
tLOAD
the optimum A/D conversion accuracy.
While the ADC is on, these two phases are contin- 6.7.4 Low Power Modes
uously repeated. Note: The A/D converter may be disabled by re-
At the end of each conversion, the sample capaci- setting the ADON bit. This feature allows reduced
tor is kept loaded with the previous measurement power consumption when no conversion is need-
load. The advantage of this behaviour is that it ed and between single shot conversions..
minimizes the current consumption on the analog Mode Description
pin in case of single input channel measurement.
WAIT No effect on A/D Converter
6.7.3.4 Software Procedure
A/D Converter disabled.
Refer to the control/status register (CSR) and data
After wakeup from Halt mode, the A/D
register (DR) in Section 6.7.6 for the bit definitions
and to Figure 57 for the timings. HALT Converter requires a stabilisation time
before accurate conversions can be
ADC Configuration performed.
The total duration of the A/D conversion is 12 ADC
clock periods (1/fADC=2/fCPU). 6.7.5 Interrupts
None

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8-BIT A/D CONVERTER (ADC) (Cont’d)

6.7.6 Register Description
CONTROL/STATUS REGISTER (CSR) DATA REGISTER (DR)
Read/Write Read Only
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)

7 0 7 0

COCO 0 ADON 0 CH3 CH2 CH1 CH0 D7 D6 D5 D4 D3 D2 D1 D0

Bit 7 = COCO Conversion Complete

This bit is set by hardware. It is cleared by soft- Bit 7:0 = D[7:0] Analog Converted Value
ware reading the result in the DR register or writing This register contains the converted analog value
to the CSR register. in the range 00h to FFh.
0: Conversion is not complete
1: Conversion can be read from the DR register Note: Reading this register reset the COCO flag.

Bit 6 = Reserved. must always be cleared.

Bit 5 = ADON A/D Converter On

This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on

Bit 4 = Reserved. must always be cleared.

Bit 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin* CH3 CH2 CH1 CH0
AIN0 0 0 0 0
AIN1 0 0 0 1
AIN2 0 0 1 0
AIN3 0 0 1 1
AIN4 0 1 0 0
AIN5 0 1 0 1
AIN6 0 1 1 0
AIN7 0 1 1 1
AIN8 1 0 0 0
AIN9 1 0 0 1
AIN10 1 0 1 0
AIN11 1 0 1 1
AIN12 1 1 0 0
AIN13 1 1 0 1
AIN14 1 1 1 0
AIN15 1 1 1 1

*Note: The number of pins AND the channel selection var-

ies according to the device. Refer to the device pinout.

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8-BIT A/D CONVERTER (ADC) (Cont’d)

Table 19. ADC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

ADCDR D7 D6 D5 D4 D3 D2 D1 D0
0070h
Reset Value 0 0 0 0 0 0 0 0
ADCCSR COCO ADON CH3 CH2 CH1 CH0
0071h
Reset Value 0 0 0 0 0 0 0 0

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7 INSTRUCTION SET

7.1 ST7 ADDRESSING MODES so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups: – Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
Addressing Mode Example however it uses more bytes and more CPU cy-
Inherent nop cles.
Immediate ld A,#$55 – Short addressing mode is less powerful because
it can generally only access page zero (0000h -
Direct ld A,$55 00FFh range), but the instruction size is more
Indexed ld A,($55,X) compact, and faster. All memory to memory in-
Indirect ld A,([$55],X) structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
Relative jrne loop INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Bit operation bset byte,#5 The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 20. ST7 Addressing Mode Overview
Pointer Pointer
Destination/ Length
Mode Syntax Address Size
Source (Bytes)
(Hex.) (Hex.)
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X register)
No Offset Direct Indexed ld A,(X) 00..FF
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF +2
Short Indirect ld A,[$10] 00..FF 00..FF byte +2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2
Relative Direct jrne loop PC-128/PC+127 1) +1
Relative Indirect jrne [$10] PC-128/PC+127 1) 00..FF byte +2
Bit Direct bset $10,#7 00..FF +1
Bit Indirect bset [$10],#7 00..FF 00..FF byte +2
Bit Direct Relative btjt $10,#7,skip 00..FF +2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.

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ST7 ADDRESSING MODES (Cont’d)

7.1.1 Inherent 7.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent Instruction Function modes:
NOP No operation Direct (short)
TRAP S/W Interrupt The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
Wait For Interrupt (Low Power ing space.
WFI
Mode)
Direct (long)
Halt Oscillator (Lowest Power
HALT The address is a word, thus allowing 64 Kbyte ad-
Mode)
dressing space, but requires 2 bytes after the op-
RET Sub-routine Return
code.
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask
7.1.4 Indexed (No Offset, Short, Long)
RIM Reset Interrupt Mask
In this mode, the operand is referenced by its
SCF Set Carry Flag memory address, which is defined by the unsigned
RCF Reset Carry Flag addition of an index register (X or Y) with an offset.
RSP Reset Stack Pointer The indirect addressing mode consists of three
sub-modes:
LD Load
Indexed (No Offset)
CLR Clear
There is no offset, (no extra byte after the opcode),
PUSH/POP Push/Pop to/from the stack
and allows 00 - FF addressing space.
INC/DEC Increment/Decrement
Indexed (Short)
TNZ Test Negative or Zero
The offset is a byte, thus requires only one byte af-
CPL, NEG 1 or 2 Complement ter the opcode and allows 00 - 1FE addressing
MUL Byte Multiplication space.
SLL, SRL, SRA, RLC, Indexed (long)
Shift and Rotate Operations
RRC The offset is a word, thus allowing 64 Kbyte ad-
SWAP Swap Nibbles dressing space and requires 2 bytes after the op-
code.
7.1.2 Immediate
Immediate instructions have two bytes, the first 7.1.5 Indirect (Short, Long)
byte contains the opcode, the second byte con- The required data byte to do the operation is found
tains the the operand value.
by its memory address, located in memory (point-
Immediate Instruction Function er).
LD Load The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP Compare
Indirect (short)
BCP Bit Compare
The pointer address is a byte, the pointer size is a
AND, OR, XOR Logical Operations
byte, thus allowing 00 - FF addressing space, and
ADC, ADD, SUB, SBC Arithmetic Operations requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

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ST7 ADDRESSING MODES (Cont’d)

7.1.6 Indirect Indexed (Short, Long) 7.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed This addressing mode is used to modify the PC
addressing modes. The operand is referenced by register value, by adding an 8-bit signed offset to
its memory address, which is defined by the un- it.
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point- Available Relative Direct/
Function
er address follows the opcode. Indirect Instructions

The indirect indexed addressing mode consists of JRxx Conditional Jump

two sub-modes: CALLR Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space, The relative addressing mode consists of two sub-
and requires 1 byte after the opcode. modes:
Relative (Direct)
Indirect Indexed (Long) The offset is following the opcode.
The pointer address is a byte, the pointer size is a Relative (Indirect)
word, thus allowing 64 Kbyte addressing space, The offset is defined in memory, which address
and requires 1 byte after the opcode. follows the opcode.
Table 21. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Addition/subtrac-
ADC, ADD, SUB, SBC
tion operations
BCP Bit Compare

Short Instructions Only Functio n

CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC,
Shift and Rotate Operations
RRC
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine

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7.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in
consisting of 63 instructions. The instructions may the following table:
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Code Condition Flag modification SIM RIM SCF RCF

Using a pre-byte
The instructions are described with one to four These prebytes enable instruction in Y as well as
bytes. indirect addressing modes to be implemented.
In order to extend the number of available op- They precede the opcode of the instruction in X or
codes for an 8-bit CPU (256 opcodes), three differ- the instruction using direct addressing mode. The
ent prebyte opcodes are defined. These prebytes prebytes are:
modify the meaning of the instruction they pre- PDY 90 Replace an X based instruction
cede. using immediate, direct, indexed, or inherent ad-
The whole instruction becomes: dressing mode by a Y one.
PC-2 End of previous instruction PIX 92 Replace an instruction using di-
rect, direct bit, or direct relative addressing mode
PC-1 Prebyte to an instruction using the corresponding indirect
PC opcode addressing mode.
It also changes an instruction using X indexed ad-
PC+1 Additional word (0 to 2) according
dressing mode to an instruction using indirect X in-
to the number of bytes required to compute the ef-
dexed addressing mode.
fective address
PIY 91 Replace an instruction using X in-
direct indexed addressing mode by a Y one.

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with Carry A=A+M+ C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL Jump if ext. interrupt = 0
JRH Jump if H = 1 H= 1?
JRNH Jump if H = 0 H= 0?
JRM Jump if I = 1 I=1?
JRNM Jump if I = 0 I=0?
JRMI Jump if N = 1 (minus) N= 1?
JRPL Jump if N = 0 (plus) N= 0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C= 1?
JRNC Jump if C = 0 C= 0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z

MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0

NEG Negate (2’s compl) neg $10 reg, M N Z C

NOP No Operation

OR OR operation A=A+M A M N Z

POP Pop from the Stack pop reg reg M

pop CC CC M H I N Z C

PUSH Push onto the Stack push Y M reg, CC

RCF Reset carry flag C=0 0

RET Subroutine Return

RIM Enable Interrupts I=0 0

RLC Rotate left true C C <= Dst <= C reg, M N Z C

RRC Rotate right true C C => Dst => C reg, M N Z C

RSP Reset Stack Pointer S = Max allowed

SBC Subtract with Carry A=A-M-C A M N Z C

SCF Set carry flag C=1 1

SIM Disable Interrupts I=1 1

SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C

SLL Shift left Logic C <= Dst <= 0 reg, M N Z C

SRL Shift right Logic 0 => Dst => C reg, M 0 Z C

SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C

SUB Subtraction A=A-M A M N Z C

SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z

TNZ Test for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1

WFI Wait for Interrupt 0

XOR Exclusive OR A = A XOR M A M N Z

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8 ELECTRICAL CHARACTERISTICS

8.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices for protecting the in- Power Considerations. The average chip-junc-
puts against damage due to high static voltages, tion temperature, TJ, in Celsius can be obtained
however it is advisable to take normal precautions from:
to avoid applying any voltage higher than the TJ = TA + PD x RthJA
specified maximum rated voltages. Where: TA = Ambient Temperature.
For proper operation it is recommended that VI RthJA =Package thermal resistance
and VO be higher than VSS and lower than V DD. (junction-to ambient).
Reliability is enhanced if unused inputs are con- PD = PINT + PPORT.
nected to an appropriate logic voltage level (VDD PINT = IDD x VDD (chip internal power).
or VSS). PPORT =Port power dissipation
determined by the user)
Symbol Ratings Value Unit
VDD - VSS Supply voltage 6.5 V
Analog reference voltage
VDDA - VSSA 6.5 V
VDDA > VSS
|VDD_i - VDD_j|
Max. variations (power line) 50 mV
|V DD_i - VDDA|
|VSS_i - VSS_j|
Max. variations (ground line) 50 mV
|VSS_i - VSSA|
VIN Input voltage VSS - 0.3 to VDD + 0.3 V
VOUT Output voltage VSS - 0.3 to VDD + 0.3 V
ESD ESD susceptibility 2000 V
IVDD_i Total current into VDD_i (source) 150
mA
IVSS_i Total current out of VSS_i (sink) 150

Note:
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.

General Warning:
Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is
generated or the program counter is corrupted (by an expected change to the I/O configuration). To guarantee safe op-
eration, this connection has to be done through a pull-up or pull-down resistor (10KΩ typical).

Thermal Characteristics
Symbol Ratings Value Unit
Package thermal resistance TQFP64 60
SDIP56 TBD
RthJA °C/W
TQFP44 TBD
SDIP42 TBD
T Jmax Max. junction temperature 150 °C
TSTG Storage temperature range -65 to +150 °C
PD Power dissipation 500 mW

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8.2 RECOMMENDED OPERATING CONDITIONS

GENERAL

Symbol Parameter Conditi ons Min Typ Max Unit

VDD Supply voltage see Figure 58 3.0 5.5 V
VDD ≥ 3.5V 1 16
Resonator oscillator frequency
VDD ≥ 3.0V 1 8
fOSC MHz
VDD ≥ 3.5V 0 2) 16
External clock source
VDD ≥ 3.0V 0 2) 8
1 Suffix Version 0 70
6 Suffix Version -40 85
TA Ambient temperature range °C
7 Suffix Version -40 105
3 Suffix Version -40 125

Figure 58. fOSC Maximum Operating Frequency Versus VDD Supply Voltage 3)

FUNCTIONALI TY NOT GUARAN TEED IN THIS AREA FUNCTIONA LITY GUARANTEED IN THIS AREA

fOSC FUNCT IONALITY NOT GUARAN TEED IN THIS AREA

[MHz] FOR TEMPERATU RE HIGHER THAN 85°C

16

1
0 SUPPLY VOLTAGE [V]
2.5 3 3.5 4 4.5 5 5.5

FUNCTI ONALITY NOT GUARANTEED IN THIS AREA WITH RESONA TOR

Notes:
1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2) A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
3) Operating conditions TA=-40 to +85°C. The shaded area is outside the recommended operating range; device func-
tionality is not guaranteed under these conditions.

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8.3 DC ELECTRICAL CHARACTERISTICS

Recommended operating conditions with TA=-40 to +85oC, VDD-VSS=5V unless otherwise specified.
Symbol Parameter Conditio ns Min Typ 1) Max Unit
fOSC = 4 MHz, fCPU = 2 MHz
Supply current in RUN mode 2) fOSC = 8 MHz, fCPU = 4 MHz TBD
fOSC = 16 MHz, fCPU = 8 MHz
fOSC = 4 MHz, fCPU = 125 kHz
Supply current in SLOW mode 2) fOSC = 8 MHz, fCPU = 250 kHz TBD
fOSC = 16 MHz, fCPU = 500 kHz
mA
IDD fOSC = 4 MHz, fCPU = 2 MHz
Supply current in WAIT mode 3) fOSC = 8MHz, f CPU = 4 MHz TBD
fOSC = 16MHz, fCPU = 8 MHz
fOSC = 4 MHz, fCPU = 2 MHz
Supply current in SLOW WAIT mode 3) fOSC = 8 MHz, fCPU = 250 kHz TBD
fOSC = 16 MHz, fCPU = 500 kHz
Supply current in HALT mode 4) ILOAD = 0mA (current on I/Os) TBD µA
V RM Data retention mode 5) HALT mode 2 V

8.4 GENERAL TIMING CHARACTERISTICS

Symbol Parameter Conditi ons Min Typ Max Unit

tINST Instruction time 2 12 tCPU
t IRT Interrupt reaction time tIRT = ∆t INST + 10 6) 10 22 tCPU

Notes:
1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2) CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS, all peripherals switched
off; clock input (OSC1) driven by external square wave.
3) All I/O pins in input mode with a static value at VDD or VSS, all peripherals switched off; clock input (OSC1) driven by
external square wave.
4) All I/O pins in input mode with a static value at VDD or VSS, LVD disabled.
5) Data based on characterization results, not tested in production.
6) ∆tINST is the number of tCPU to finish the current instruction execution.

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8.5 I/O PORT CHARACTERISTICS

Recommended operating conditions
with TA =-40 to +85oC and 4.5V<VDD-VSS<5.5V unless otherwise specified.
I/O PORT PINS

Symbol Parameter Conditions Min Typ 1) Max Unit

2)
VIL Input low level voltage 0.3xVDD
V
V IH Input high level voltage 2) 3V<V DD-VSS<5.5V 0.7xVDD
VHYS Schmitt trigger voltage hysteresis 3) 400 mV
Output low level voltage I=-5mA 1.3
for Standard I/O port pins I=-2mA 0.5
VOL
Output low level voltage I=-20mA 1.3
V
for high sink I/O port pins I=-8mA 0.5
I=-5mA VDD-2.0
VOH Output high level voltage
I=-2mA VDD-0.8
VIN > VIH 20 35 50
RPU Pull-up equivalent resistor kΩ
V IN < VIL 60 100 140
IL Input leakage current VSS<VPIN<VDD 1
2) µA
ISV Static current consumption Floating input mode 200
Positive 5): VEXT>VDD 5
IPINJ Single pin injected current
Negative 6): VEXT<VSS -5
mA
Total injected current 7) Positive: V EXT>VDD tbd
IINJ
(sum of all I/O and control pins) Negative: VEXT<V SS tbd
tOHL Output high to low level fall time 14.8 4) 25 45.6 4)
Cl=50pF ns
tOLH Output low to high rise time 14.4 4) 25 45.9 4)
tITEXT External interrupt pulse time 8) 1 tCPU

Notes:
1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2) Data based on design simulation and/or technology characteristics, not tested in production.
3) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4) Data based on characterization results, not tested in production.
5) Positive injection (IINJ+)
The IINJ+ is performed through protection diodes insulated from the substrate of the die.
The true open-drain pins do not accept positive injection. In this case the maximum voltage rating must be respected.
6) ADC accuracy reduced by negative injection (IINJ- )
The IINJ- is performed through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small
leakage (a few µA) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital
structure, but it acts on the analog line depending on the impedance versus a leakage current of a few µA (if the MCU
has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals
applied to the component must have a maximum impedance close to 50KΩ.
Location of the negative current injection:
- Pins with analog input capability are the most sensitive. IINJ- maximum is 0.8 mA (assuming that the impedance of the
analog voltage is lower than 25KΩ)
- Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog
input pins.
7) When several inputs are submitted to a current injection, the maximum IINJ is the sum of the positive (or negative) cur-
rents (instantaneous values). These results are based on characterisation with IINJ maximum current injection on four I/
O port pins of the device.
8) To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

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8.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS

8.6.1 Supply Manager
Recommended operating conditions
with TA =-40 to +85oC and voltage are referred to VSS unless otherwise specified.
LOW VOLTAG E DETECTOR (LVD)

Symbol Parameter Condition s Min Typ 1) Max Unit

High Threshold 4.30 4.50
Reset release threshold
VLVDr Med. Threshold (fOSC≤16MHz) 3.90 4.05
(VDD rise)
Low Threshold (fOSC≤8MHz) 3.35 3.45
V
High Threshold 3.85 4.05 4.25
Reset generation threshold
VLVDf Med. Threshold (fOSC≤16MHz) 3.50 3.65 3.80
(VDD fall)
Low Threshold (fOSC≤8MHz) 3.00 3.10 3.20
VLVDhyst VLVD Hysteresis 2) VLVDr - VLVDf 250* mV
IDD LVD Supply Current HALT mode 100 150 3) µA

8.6.2 Reset Sequence Manager

Recommended operating conditions
with TA =-40...+85oC and 4.5V<VDD-VSS<5.5V unless otherwise specified.
RESET SEQUENCE MANAGER (RSM)

Symbol Parameter Condition s Min Typ 4) Max Unit

VIN > VIH 5 10 20
R ON Reset weak pull-up resistance kΩ
VIN < VIL 40 80 160
Reset delay for external and 6 1/fSFOSC
tDELAYmin
watchdog reset sources 30 µs
tPULSE External RESET pin Pulse time 20 µs

8.6.3 Multi-Oscillator, Clock Security System

Recommended operating conditions
with TA =-40 to +85oC and voltage are referred to VSS unless otherwise specified.
EXTERNAL CLOCK SOURCE

Symbol Parameter Condition s Min Typ Max Unit

VOSC1h OSC1 input pin high level voltage Square wave signal 0.7xVDD VDD
V
VOSC1l OSC1 input pin low level voltage with ~50% Duty Cycle VSS 0.3xVDD

Notes:
1) LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2) The VLVDhyst hysteresis is constant.
3) Data based on characterization results, not tested in production.
4) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.

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SUPPLY, RESET AND CLOCK CHARACTERISTICS (Cont’d)

CRYSTAL AND CERAMIC RESONATOR OSCILLATORS

Symbol Parameter Condition s Min Typ 1) Max Unit

Low speed resonator 1 2
2) Medium-low speed resonator >2 4
fOSC Oscillator Frequency MHz
Medium-high speed resonator >4 8
High speed resonator >8 16
Low speed RSmax=200Ω 3) 38 4) 47 56 4)
Load Medium-low speed RSmax=200Ω 3) 32 4) 39 46 4)
C Li pF
Capacitance Medium-high speed RSmax=200Ω 3) 18 4) 22 26 4)
High speed RSmax=100Ω 3) 15 4) 18 21 4)

Low speed 150 700 5)

Supply Medium-low speed 200 700 5)
IDD µA
Current Medium-high speed 400 750 5)
High speed 700 1100 5)

tSTART Oscillator start-up time Depends on resonator quality. A typical value is 10ms

EXTERNAL RC OSCILLATO R

Symbol Parameter Condition s Min 4) Typ 1) Max Unit

fOSC External RC Oscillator Frequency 1 14 4) MHz
R EX Oscillator External Resistance V DD=5V 10 33 47 4) kΩ
C EX Oscillator External Capacitance 0 6) 47 470 4) pF
IDD Supply Current 525 750 5) µA

INTERNAL RC OSCILLATOR

Symbol Parameter Condition s Min Typ 1) Max Unit

V DD=5.5V 3.50 4.25 5.00
fOSC Internal RC Oscillator Frequency MHz
V DD=3.0V 3.35 4.10 4.85
IDD Supply Current 500 750 5) µA

CLOCK SECURITY SYSTEM (CSS)

Symbol Parameter Conditions Min Typ 1) Max Unit

VDD=5.5V 250 340 430
fSFOSC Safe Oscillator Frequency kHz
VDD=3.0V 190 260 330
fCFL Clock Filter Frequency limitation 30 MHz
IDD Supply Current 150 350 5) µA

Notes:
1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2) These data are based on typical RSmax. The oscillator selection can be optimized in terms of supply current with high
quality resonator.
3) RSmax is the equivalent serial resistance of the crystal or ceramic resonator.
4) Data based on design simulation and/or technology characteristics, not tested in production.
5) Data based on characterization results, not tested in production.
6) In this condition, the capacitor to be considered is the global parasitic capacitor. In this case, the RC oscillator frequen-
cy tuning has to be done by trying out several resistor values.

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8.7 MEMORY AND PERIPHERAL CHARACTERISTICS

Recommended operating conditions
with TA =-40 to +85oC and 3V<VDD-VSS<5.5V unless otherwise specified.
FLASH Program Memory
Symbol Parameter Conditions Min Typ 1) Max Unit
t ISPPROG Typical programming time 8 or 16kBytes FLASH 2.1 6.4 sec
tRET Data retention TA=55°C 20 years
N RW Write erase cycles 1000 cycles

Data-EEPROM
Symbol Parameter Conditi ons Min Typ Max Unit
tPROG Programming time 25 ms
tRET Data retention 10 Years
NRW Write erase cycles 100 000 Cycles

WATCHDOG
Symbol Parameter Conditions Min Typ Max Unit
12,288 786,432 tCPU
tDOG Watchdog time-out
fCPU = 8MHz 1.54 98.3 ms

Note:
1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.

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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)

SPI Serial Peripheral Interface
Value 1)
Ref. Symbol Parameter Condition Unit
Min Max
Master 1/128 1/4
fSPI SPI frequency fCPU
Slave dc 1/2
Master 4
1 tSPI SPI clock period tCPU
Slave 2
2 tLead Enable lead time Slave 120 ns
3 tLag Enable lag time Slave 120 ns
Master 100
4 tSPI_H Clock (SCK) high time ns
Slave 90
Master 100
5 tSPI_L Clock (SCK) low time ns
Slave 90
Master 100
6 tSU Data set-up time ns
Slave 100
Master 100
7 tH Data hold time (inputs) ns
Slave 100
Access time (time to data active
8 tA 0 120 ns
from high impedance state)
Slave
Disable time (hold time to high im-
9 tDis 240 ns
pedance state)
Master (before capture edge) 0.25 tCPU
10 tV Data valid
Slave (after enable edge) 120 ns
Master (before capture edge) 0.25 tCPU
11 tHold Data hold time (outputs)
Slave (after enable edge) 0 ns
Rise time Outputs: SCK,MOSI,MISO 100 ns
12 tRise
(20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS 100 µs
Fall time Outputs: SCK,MOSI,MISO 100 ns
13 tFall
(70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS 100 µs

Figure 59. SPI Master Timing Diagram CPHA=0, CPOL=0 2)

SS
(INPUT) 1
13 12
SCK
(OUTPUT)
4 5
MISO D7-IN D6-IN
(INPUT) D0-IN
6 7
MOSI D7-OUT D6-OUT D0-OUT
(OUTPUT)
10 11
VR000109

Notes:
1) Data based on characterization results, not tested in production.
2) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram.

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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)

Figure 60. SPI Master Timing Diagram CPHA=0, CPOL=1 1)

SS
(INPUT) 1
13 12
SCK
(OUTPUT) 5 4
MISO
(INPUT) D7-IN D6-IN D0-IN
6 7
MOSI D7-OUT D6-OUT D0-OUT
(OUTPU T)
10 11
VR000110
1)
Figure 61. SPI Master Timing Diagram CPHA=1, CPOL=0
SS
(INPUT) 1
13 12
SCK
(OUTPUT)
4 5
MISO D7-OUT D6-OUT
(INPUT) D0-OUT
6 7
MOSI D7-IN D6-IN D0-IN
(OUTPU T)
10 11
VR000107

Figure 62. SPI Master Timing Diagram CPHA=1, CPOL=1 1)

SS
(INPUT) 1
12 13
SCK
(OUTPUT) 5 4
MISO D7-IN D6-IN
(INPUT) D0-IN
6 7
MOSI
D7-OUT D6-OUT D0-OUT
(OUTPUT)
10 11
VR000108

Note:
1) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram.

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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)

Measurement points are VOL, VOH, VIL and VIH in the SPI Timing Diagram

Figure 63. SPI Slave Timing Diagram CPHA=0, CPOL=0 1)

SS
(INPUT)
2 1
13 12 3
SCK
(INPUT) 4 5
MISO HIGH-Z
(OUTPU T) D7-OUT D6-OUT D0-OUT
8 10 11 9
MOSI
D7-IN D6-IN D0-IN
(INPUT)
7
6
VR000113

Figure 64. SPI Slave Timing Diagram CPHA=0, CPOL=1 1)

SS
(INPUT)
2 1
12 13 3
SCK
(INPUT)
5 4
MISO HIGH-Z
(OUTPU T) D7-OUT D6-OUT D0-OUT
8 10 11 9
MOSI
D7-IN D6-IN D0-IN
(INPUT) 7
6
VR000114

Figure 65. SPI Slave Timing Diagram CPHA=1, CPOL=0 1)

SS
(INPUT)
2 1 13 12 3
SCK
(INPUT)
4 5
HIGH-Z
MISO D7-OUT D6-OUT D0-OUT
(OUTPUT)
8 10 11 9
MOSI
(INPUT) D7-IN D6-IN D0-IN
6 7
VR000111

Figure 66. SPI Slave Timing Diagram CPHA=1, CPOL=1 1)

SS
(INPUT)
2 1 12 13 3
SCK
(INPUT)
5 4
HIGH-Z
MISO D7-OUT D6-OUT D0-OUT
(OUTPUT)
8 10 11 9
MOSI
(INPUT) D7-IN D6-IN D0-IN
6 7
VR000112

Note:
1) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram.

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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)

SCI Serial Communication Interface

Symbol Parameter Conditions Typ 1) Unit

Standard Mode
TR (resp.RR)=64, PR=13 ~300.48
TR (resp.RR)=16, PR=13 ~1201.92
TR (resp.RR)= 8, PR=13 ~2403.84
Communication frequency TR (resp.RR)= 4, PR=13 ~4807.69
fTx or fRx fCPU=8MHz TR (resp.RR)= 2, PR=13 ~9615.38 Hz
(precision vs. standard ~0.16%)
TR (resp.RR)= 8, PR= 3 ~10416.67
TR (resp.RR)= 1, PR=13 ~19230,77
Extended Mode
ETPR (resp.ERPR) = 13 ~38461.54
See “STANDARD I/O PORT PINS” description for more details.

Note:
1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.

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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)

ADC Analog to Digital Converter (8-bit)

Symbol Parameter Conditions Min Typ 1) Max Unit

fADC Analog control frequency VDD=VDDA=5V 4 2) MHz

4)
|TUE| Total unadjusted error 1
4)
OE Offset error -0.5 0.5
TA=25°C,VDD=VDDA=5V, 3)
GE Gain Error 4) -0.5 0.5 LSB
fCPU=8MHz,fADC=4MHz
4)
|DLE| Differential linearity error 0.5
|ILE| Integral linearity error 4) 0.5
VAIN Conversion range voltage VSSA VDDA V
IADC A/D conversion supply current 1 mA
tSTAB Stabilization time after ADC enable 1 µs
fCPU =8MHz, fADC=4MHz 1 µs
tLOAD Sample capacitor loading time VDD=VDDA=5V 4 1/fADC
2 µs
tCONV Hold conversion time
8 1/fADC
R AIN External input resistor 15 2) kΩ
R ADC Internal input resistor 1.5 kΩ
C SAMPLE Sample capacitor 6 pF

Notes:
1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2) Data based on characterization results, not tested in production.
3) Tested in production at TA=25°C, characterized over the whole temperature range.
4) ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.

Digital Result ADCDR GE

(1) Example of an actual transfer curve
255
(2) The ideal transfer curve
254 V –V (3) End point correlation line
DDA S SA
1LS B = ----------------------------------------
-
253 i deal 256

(2)
TUE=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
7 TUE (3) OE=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
GE=Gain Error: deviation between the last ideal
5 transition and the last actual one.
OE ILE DLE=Differential Linearity Error: maximum devia-
4 tion between actual steps and the ideal one.
3 ILE=Integral Linearity Error: maximum deviation
DLE between any actual transition and the end point
2 correlation line.
1 LSB (ideal)
1
Vin (LSBideal)
0
1 2 3 4 5 6 7 253 254 255 256
VSSA VDDA

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 ST72334J/N, ST72314J/N, ST72124J

9 GENERAL INFORMATION

9.1 PACKAGES
9.1.1 Package Mechanical Data
Figure 67. 64-Pin Thin Quad Flat Package

mm inches
Dim
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.30 0.37 0.45 0.012 0.015 0.018
C 0.09 0.20 0.004 0.008
D 16.00 0.630
D1 14.00 0.551
D3 12.00 0.472
E 16.00 0.630
E1 14.00 0.551
E3 12.00 0.472
e 0.80 0.031
K 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 L1 1.00 0.039
L
Number of Pins
N 64 ND 16 NE 16
K

Figure 68. 56-Pin Shrink Plastic Dual In-Line Package, 600-mil Width

mm inches
Dim.
Min Typ Max Min Typ Max
A 6.35 0.250
A1 0.38 0.015
A2 3.18 4.95 0.125 0.195
b 0.41 0.016
b2 0.89 0.035
C 0.20 0.38 0.008 0.015
D 50.29 53.21 1.980 2.095
E 15.01 0.591
E1 12.32 14.73 0.485 0.580
e 1.78 0.070
eA 15.24 0.600
eB 17.78 0.700
L 2.92 5.08 0.115 0.200
PDIP56S Number of Pins
N 56

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PACKAGES (Cont’d)
Figure 69. 44-Pin Thin Quad Flat Package

mm inches
Dim
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.30 0.37 0.45 0.012 0.015 0.018
c 0.09 0.20 0.004 0.008
b
D 12.00 0.472
D1 10.00 0.394
D3 8.00 0.315
E 12.00 0.472
E1 10.00 0.394
c E3 8.00 0.315
e 0.80 0.031
K 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 L1 1.00 0.039
L
Number of Pins
N 44
K

Figure 70. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width

mm inches
Dim.
Min Typ Max Min Typ Max
A 5.08 0.200
A1 0.51 0.020
A2 3.05 3.81 4.57 0.120 0.150 0.180
b 0.46 0.56 0.018 0.022
b2 1.02 1.14 0.040 0.045
C 0.23 0.25 0.38 0.009 0.010 0.015
D 36.58 36.83 37.08 1.440 1.450 1.460
E 15.24 16.00 0.600 0.630
E1 12.70 13.72 14.48 0.500 0.540 0.570
e 1.78 0.070
eA 15.24 0.600
eB 18.54 0.730
eC 0.00 1.52 0.000 0.060
PDIP42S L 2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N 42

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PACKAGES (Cont’d)
9.1.2 User-supplied TQFP64 Adaptor / Socket ■ Direct TQFP64 soldering
To solder the TQFP64 device directly on the appli- ■ YAMAICHI IC149-064-008-S5* socket
cation board, or to solder a socket for connecting soldering to plug either the emulator probe or an
the emulator probe, the application board should adaptor board with an TQFP64 clamshell
provide the footprint described in Figure 71. This socket.
footprint allows both configurations: * Not compatible with TQFP64 package.

Figure 71. TQFP64 Device And Emulator Probe Compatible Footprint

SK
mm inches
E Dim
E1 Min Typ Max Min Typ Max
E3 B 0.35 0.45 0.50 0.014 0.018 0.020

E 20.80 0.819

e E1 14.00 0.551

E3 11.90 12.00 12.10 0.468 0.472 0.476

B e 0.75 0.80 0.85 0.029 0.031 0.033

E1
E3
SK
E

SOCKET
SK* 26 1.023
DETAIL
Number of Pins

N 64 (4x16)

* SK: Plastic socket overall dimensions.

Table 22. Suggested List of TQFP64 Socket Types

Package / Probe Adaptor / Socket Reference Socket type
ENPLAS OTQ-64-0.8-02 Open Top
TQFP64
YAMAICHI IC51-0644-1240.KS-14584 Clamshell
EMU PROBE YAMAICHI IC149-064-008-S5 SMC

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ST72334J/N, ST72314J/N, ST72124J

PACKAGES (Cont’d)
9.1.3 User-supplied TQFP44 Adaptor / Socket ■ Direct TQFP44 soldering
To solder the TQFP44 device directly on the appli- ■ YAMAICHI IC149-044-*52-S5 socket soldering
cation board, or to solder a socket for connecting to plug either the emulator probe or an adaptor
the emulator probe, the application board should board with an TQFP44 clamshell socket.
provide the footprint described in Figure 72. This
footprint allows both configurations:
Figure 72. TQFP44 Device And Emulator Probe Compatible Footprint

SK
mm inches
E Dim
E1 Min Typ Max Min Typ Max
E3 B 0.35 0.45 0.50 0.014 0.018 0.020

E 13.40 0.527

e E1 10.00 0.394

E3 7.95 8.00 8.05 0.313 0.315 0.317

B e 0.75 0.80 0.85 0.029 0.031 0.033

E1
E3
SK
E

SOCKET
SK* 24.2 0.953
DETAIL
Number of Pins

N 44 (4x11)

* SK: Plastic socket overall dimensions.

Table 23. Suggested List of TQFP44 Socket Types

Package / Probe Adaptor / Socket Reference Socket type
ENPLAS OTQ-44-0.8-04 Open Top
TQFP44
YAMAICHI IC51-0444-467-KS-11787 Clamshell
TQFP44
YAMAICHI IC149-044-*52-S5 SMC
EMU PROBE

120/125
 ST72334J/N, ST72314J/N, ST72124J

9.2 DEVICE CONFIGURATION AND ORDERING USER OPTION BYTE 2

INFORMATION
7 0
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory WDG WDG
CFC OSC2 OSC1 OSC0 LVD1 LVD0
coded versions (ROM). HALT SW
FLASH devices are shipped to customers with a
default content (FFh), while ROM factory coded Bit 7 = CFC Clock filter control on/off
parts contain the code supplied by the customer. This option bit enables or disables the clock filter
This implies that FLASH devices have to be con- (CF) features.
figured by the customer using the Option Bytes 0: Clock filter enabled
while the ROM devices are factory-configured. 1: Clock filter disabled
9.2.1 Option Bytes
The two Option Bytes allow the hardware configu- Bit 6:4 = OSC[2:0] Oscillator selection
ration of the microcontroller to be selected. These three option bits can be used to select the
The Option Bytes have no address in the memory main oscillator as shown in Table 24.
map and can be accessed only in programming Table 24. Main Oscillator Configuration
mode (for example using a standard ST7
4programming tool). The default contents of the Selected Oscillator OSC2 OSC1 OSC0
FLASH is fixed to FFh. This means that all the op- External Clock (Stand-by) 1 1 1
tions have “1” as their default value. Internal RC 1 1 0
In masked ROM devices, the Option Bytes are
fixed in hardware by the ROM code. 1 0 1
External RC
1 0 0
USER OPTION BYTE 1
Low Speed Resonator 0 1 1
7 0 Medium-low Speed Resonator 0 1 0
Medium-high Speed Resonator 0 0 1
1 1 1 1 1 1 56/42 FMP High Speed Resonator 0 0 0

Bit 3:2 = LVD[1:0] Low voltage detection selection

Bit 7:2 = Reserved, must always be 1. These option bits enable the LVD block with a se-
lected threshold as shown in Table 25.
Table 25. LVD Threshold Configuration
Bit 1 = 56/42 Package configuration.
This option bit allows to configure the device ac- Configuratio n LVD1 LVD0
cording to the package.
LVD Off 1 1
0: 42 and 44 pin.
1: 56 and 64 pin. Highest Voltage Threshold (VDD~5V) 1 0
Medium Voltage Threshold (fOSC≤16MHz) 0 1
Bit 0 = FMP Full memory protection. Lowest Voltage Threshold (fOSC≤8MHz) 0 0
This option bit enables or disables external access
to the internal program memory (read-out protec- Bit 1 = WDG HALT Watchdog and halt mode
tion). Clearing this bit causes the erasing (to 00h) This option bit determines if a RESET is generated
of the whole memory (including the option byte). when entering HALT mode while the Watchdog is
0: Program memory not read-out protected active.
1: Program memory read-out protected 0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode

Bit 0 = WDG SW Hardware or software watchdog

This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

9.2.2 Transfer Of Customer Code The selected options are communicated to STMi-
Customer code is made up of the ROM contents croelectronics using the correctly completed OP-
and the list of the selected options (if any). The TION LIST appended.
ROM contents are to be sent on diskette, or by The STMicroelectronics Sales Organization will be
electronic means, with the hexadecimal file in .S19 pleased to provide detailed information on con-
format generated by the development tool. All un- tractual points.
used bytes must be set to FFh.
Figure 73. ROM Factory Coded Device Types

TEMP.
DEVICE PACKAGE RANGE / XXX
Code name (defined by STMicroelectronics)

1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +125 °C
3= automotive -40 to +125 °C

B = Plastic DIP
T = Plastic TQFP

ST72334J2, ST72334J4, ST72334N2, ST72334N4,

ST72314J2, ST72314J4, ST72314N2, ST72314N4,
ST72124J2

Figure 74. FLASH User Programmable Device Types

TEMP.
DEVICE PACKAGE RANGE XXX
Code name (defined by STMicroelectronics)

1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +125 °C
3= automotive -40 to +125 °C

B = Plastic DIP
T = Plastic TQFP

ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4,

ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4,
ST72C124J2

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MICROCONTROLLER OPTION LIST

Customer . . ... ... . .. .. . .. .. .. . .. ... . .. .... . ... .. .. .. .. . .. .. .. . .. ... . .. ..

Address . . ... ... . .. .. . .. .. .. . .. ... . .. .... . ... .. .. .. .. . .. .. .. . .. ... . .. ..
Contact . . ... ... . .. .. . .. .. .. . .. ... . .. .... . ... .. .. .. .. . .. .. .. . .. ... . .. ..
Phone No . . ... ... . .. .. . .. .. .. . .. ... . .. .... . ... .. .. .. .. . .. .. .. . .. ... . .. ..
Reference . . ... ... . .. .. . .. .. .. . .. ... . .. .... . ... .. .. .. .. . .. .. .. . .. ... . .. ..

STMicroelectronics references
Device: [ ] ST72334J2 [ ] ST72314J2 [ ] ST72124J2
[ ] ST72334J4 [ ] ST72314J4
[ ] ST72334N2 [ ] ST72314N2
[ ] ST72334N4 [ ] ST72314N4

Package: [ ] TQFP64 [ ] SDIP56

[ ] TQFP44 [ ] SDIP42

Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C

Clock Source Selection: [ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz)

[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] RC Network: [ ] Internal
[ ] External
[ ] External Clock
Clock Security System: [ ] Disabled
[ ] Enabled

Watchdog Selection: [ ] Software Activation

[ ] Hardware Activation
Halt when Watchdog on: [ ] Reset
[ ] No reset

Readout Protection: [ ] Disabled

[ ] Enabled

LVD Reset [ ] Disabled [ ] Enabled: [ ] Highest threshold (4.30V/4.05V)

[ ] Medium threshold (3.90V/3.65V)
[ ] Lowest threshold (3.35V/3.10V)

Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes . . ... ... . .. .. . .. .. .. . .. ... . .. .... . ... .. .. .. .. . .. .. .. . .. ... . .. ....
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . ... ... . .. .. . .. .. .. . .. ... . .. .... . ... .. .. .. .. . .. .. .. . .. ... . .. ....

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10 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision Main changes Date
New chapter to compare ST72334 versus ST72331 (section 2.1 on page 6)
Correction of the address of the CRSR register to 2Bh instead of 25h (Table 4 page 33)
Correction of port A pin name column in Table 9 page 44 (PA2:0 instead of PA3:0)
Correction of MISCR2 register description (section 6.2.3 on page 48)
Correction of the FLASH and data EEPROM programming time (section 8.7 on page 111)
1.0 Sept-99
Correction of the TQFP44 socket proposal (Table 23 page 120)
More information on the FMP option bit (section 9.2.1 on page 121)
Added .S19 format in transfer of Code (section 9.2.2 on page 122)
Correction of the microcontroller option list (section 9.2.2 on page 122)
History page added (section 10 on page 124)

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Notes:

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
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