Introduction to VLSI Design, VLSI I, Fall 2010

10. Interconnects in CMOS Technology 1

mm 40 60 80 100 120

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10. Interconnects in CMOS Technology

J. A. Abraham

Department
60 of Electrical and Computer Engineering
The University of Texas at Austin
EE 382M, VLSI I
Fall 2010
80
October 4, 2010

ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 1 / 33

Introduction to Wires on a Chip

Intel Damascene copper
mm 40 60 80 100 120
Most of chip is wires (interconnect)
Most of the chip is covered by
wires, many layers of wires
Transistors:
40 little things under
wires
Wires as important as transistors
Affect IBM air gap between Cu
60 Speed
Power
Noise
Alternating layers usually run
orthogonally
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 1 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 2

Wire Geometry

mm
Pitch = w +40s 60 80 100 120
Aspect Ratio, AR = t/w
Old processes had AR << 1
Modern processes have AR ≈ 2 to pack in many skinny wires
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 2 / 33

Layer Stack

Number of metal
mm 40 layers has60 been increasing
80 100 120
AMI 0.6 mm process has 3 metal layers
Modern processes use 6-10+ metal layers

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Example: Intel 180 nm
process
M1: thin, narrow (< 3λ)
High density cells
60
M2-M4: thicker
For longer wires
M5-M6: thickest
For VDD , GND, CLK
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 3 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 3

Wire Resistance
ρ = resistivity (Ω ∗ m)
mm 40
ρ l l
R = 60 = R 80 100 120
tw w
R = sheet resistance (Ω/)
 is a dimensionless unit
Count number of squares
40
R = R ∗ (# of squares)

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 4 / 33

Choice of Metals

mm 40 60 80 100 120
Until the 180 nm generation, most wires were aluminum
Modern processes often use copper
Cu atoms diffuse into silicon and damage FETs
40 Must be surrounded by a diffusion barrier
Metal Bulk Resistivity (µΩ ∗ cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold60(Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 5 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 4

Sheet Resistance

mmsheet resistances
Typical 40 60nm process80
in 180 100 120

Layer Sheet Resistance (Ω/)

Diffusion (silicided) 3–10
Diffusion (no silicide) 50–200
40
Polysilicon (silicided) 3–10
Polysilicon (no silicide) 50–400
Metal1 0.08
Metal2 0.05
60
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 6 / 33

Contact Resistance

Contacts and40vias also have

mm 60 2-20 Ω resistance
80 100 120
Use many contacts for lower R
Many small contacts for current crowding around periphery
Multiple contacts also help improve the yield (failure or high
resistance
40 of a contact will have only a small effect on the
overall resistivity)

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 7 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 5

Wire Capacitance

Wire has capacitance per unit length

mm To neighbors
40 60 80 100 120
To layers above and below
Ctotal = Ctop + Cbot + 2Cadj

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 8 / 33

Capacitance Trends

mm 40 60 80 100 120
Parallel plate equation: C = A/d
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
40 Increasing distance (s, h) decreases capacitance
Dielectric Constant
 = k0
0 = 8.85 × 1014 F/cm
k60= 3.9 for SiO2
Processes are starting to use low-k dielectrics
k ≈ 3 (or less) as dielectrics use air pockets

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 9 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 6

M2 Capacitance Data
Typical wires have ≈ 0.2 f F/µm
Compare to 2 f F/µm for gate capacitance
mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 10 / 33

Diffusion and Polysilicon

mm 40 60 80 100 120

Diffusion capacitance is very high (about 2 f F/µm)

Comparable to gate capacitance
40 Diffusion also has high resistance
Avoid using diffusion runners for wires!
Polysilicon has lower C but high R
Use for transistor gates
60 Occasionally for very short wires between gates

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 11 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 7

Lumped Element Models

Wires are a distributed system
mm Approximate
40 with lumped
60 element models
80 100 120

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60

3-segment π-model accurate to 3% in simulation

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L-model needs 100 segments for same accuracy!
Use single segment π-model for Elmore delay
ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 12 / 33

Example

mm
Metal2 wire in
40 180 nm process
60 80 100 120
5 mm long
0.32 µm wide
Construct a 3-segment π-model
40 R = 0.05 Ω/ =⇒ R = 781 Ω
Cpermicron = 0.2f F/µm =⇒ C = 1 pF

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 13 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 8

Wire RC Delay

Estimate the delay of a 10x inverter driving a 2x inverter at

mm
the end of the405mm wire 60 80
from the previous 100
example 120
R = 2.5 kΩ ∗ µm for gates
Unit inverter: 0.36 µm nMOS, 0.72 µm pMOS

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80
tpd = 1.1 ns

ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 14 / 33

Crosstalk

mm 40 60 80 100 120

A capacitor does not like to change its voltage instantaneously

A wire has high capacitance to its neighbor
40 When the neighbor switches from 1→0 or 0→1, the wire tends
to switch too
Called capacitive coupling or crosstalk
Crosstalk effects
60 Noise on nonswitching wires
Increased delay on switching wires

80

ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 15 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 9

Crosstalk Delay
Assume layers above and below on average are quiet
mm Second terminal
40 of capacitor
60 can be80
ignored 100 120
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
Miller Effect
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60

B ∆V Cef f (A) MCF

Constant
80 VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2Cadj 2
ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 16 / 33

Crosstalk Noise

Crosstalk causes noise on nonswitching wires

mm 40 60 80 100 120
If victim is floating:
model as capacitive voltage divider

Cadj
40 ∆Vvictim = ∆Vaggressor
Cgnd−v + Cadj

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 17 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 10

Driven Victims
Usually victim is driven by a gate that fights noise
Noise depends on relative resistances
mm Victim driver
40 is in linear
60region, aggressor
80 100
in saturation 120
If sizes are same, Raggressor = 2 − 4 × Rvictim

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60

Cadj 1
∆Vvictim = ∆Vaggressor
Cgnd−v + Cadj 1 + k
80
τaggressor Raggressor (Cgnd−a + Cadj )
k= =
τvictim Rvictim (Cgnd−v + Cadj )
ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 18 / 33

Coupling Waveforms
Simulated Coupling for Cadj = Cvictim
mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 19 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 11

Noise Implications

mm 40 60 80 100 120

So what if we have noise?

If the noise is less than the noise margin, nothing happens
Static
40 CMOS logic will eventually settle to correct output
even if disturbed by large noise spikes
But glitches cause extra delay
Also cause extra power from false transitions
Dynamic logic never recovers from glitches
60
Memories and other sensitive circuits also can produce the
wrong answer

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 20 / 33

Wire Engineering

Goal:mm
achieve delay,
40 area, power
60 goals with80acceptable100
noise 120

Degrees of
freedom
Width
40
Spacing
Layer
Shielding

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 21 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 12

Repeaters

R and C are proportional to l

RC delay is proportional to 2
mm 40 60 l 80 100 120
Unacceptably great for long wires
Break long wires into N shorter segments
Drive each one with an inverter or buffer
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 22 / 33

Repeater Design

How many repeaters

mm 40 should
60 we use? 80 100 120
How large should each one be?
Equivalent Circuit
Wire length l
40 Wire Capacitance Cw ∗ l, Resistance Rw ∗ l
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C’*W, Resistance R/W

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80

ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 23 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 13

Repeater Results

mm 40 for Elmore60Delay
Write equation 80 100 120
Differentiate with respect to W and N
Set equal to 0, solve

r
40 l 2RC 0
=
N Rw Cw
tpd  √ p
= 2+ 2 RC 0 Rw Cw
60 l
∼ 60–80 ps/mm in 0.18µ process
r
RCw
W =
Rw C 0
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 24 / 33

Clock Distribution

mm 40 60 80 100 120

40
High peak currents to
drive typical clock loads
(≈ 1000 pF)
60
dV
Ipeak = C
dt
2
Pd = CVDD f
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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 25 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 14

H-Trees

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 26 / 33

Matching Delays in Clock Distribution

mm 40 60 80 100 120

Balance delays of paths

Match buffer and wire delays to minimize skew
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Issues
Load of latch (driven by clock) is data-dependent (capacitance
depends on source voltage)
Process variations
60 IR drops and temperature variations
Tools to support clock tree design

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 27 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 15

Clocking in the Itanium Processor

mm 40 60 80 100 120

0.18µ technology
1GHz core clock
20040MHz system clk
Core clocking
260 mm2
1 primary driver
605 repeaters
157,000 clocked
latches

80
Source for the slides on Itanium: Intel/HP
ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 28 / 33

Clock Generation

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 29 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 16

Core Clock Distribution

mm 40 60 80 100 120

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60 

80Adjustable
delay buffer

ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 30 / 33

SLCB

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 31 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
10. Interconnects in CMOS Technology 17

First Level Route Geometry

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 32 / 33

Measured Skew

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 10. Interconnects in CMOS Technology J. A. Abraham, October 4, 2010 33 / 33

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010