Silicon Test & Yield Analysis Whitepaper

Scan Based Testing

At-Speed and Advanced Fault Models

for Achieving High Quality Test
December 2009

Abstract
At-speed scan test is a common practice in most 130 nm and smaller designs as well as larger
fabrication technologies that require very high quality test. This paper describes various methods
of performing at-speed test as well as other advanced fault models that are available to improve
defect detection and lower DPM rates.

Keywords: at-speed test, timing-aware ATPG, on-chip PLL, small delay defect, bridge, multiple
detect, burst mode, pipelined scan enable.

Table of Contents

ABSTRACT..............................................................................................................................I
INTRODUCTION................................................................................................................... 1
HANDLING ON-CHIP CLOCKS ........................................................................................ 1
ACCOUNTING FOR FALSE AND MULTICYCLE PATHS........................................... 3
AT-SPEED TEST OPTIONS ................................................................................................ 4
NEWER FAULT MODELS................................................................................................... 5
MANAGING TEST TIME & DATA VOLUME................................................................. 5
FITTING IN THE MAJOR DESIGN FLOWS ................................................................... 6
REFERENCES........................................................................................................................ 6

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Silicon Test & Yield Analysis Whitepaper

Introduction
Smaller process geometries have driven more companies to adopt at-speed scan test to ensure
acceptable Defects Per Million (DPM) rates. However, since at-speed testing is a relatively new
concept for some in the mainstream market, many companies are learning that at-speed test is
more complicated than traditional stuck-at testing. This paper focuses on some key issues to
consider when adopting an at-speed test approach. In addition, some newer fault models to
target bridging and other manufacturing defects are explained.
There are many at-speed and high quality test methodologies that are supported with Mentor
Graphics’ Tessent™ tools. We present a brief description of our capabilities with consideration
of:
 Accurate clock control: using on-chip PLLs and clock generation logic
 Accurate at-speed test: avoiding test of false and multicycle paths
 Effective compression: dealing with additional at-speed test patterns and X states due to
false and multicycle tests without losing coverage

Handling On-Chip Clocks

More and more designs are including on-chip clocks to supply the high-speed functional clocks
that are required. A common approach is to use a phase locked loop (PLL) with some additional
logic for clock control. For designs with this type of configuration, it makes sense to also use
these on-chip clocks during the scan testing. The benefits include:
 The same clocks will be used in functional and test modes, improving the quality of the
test.
 If the high-speed test clocks are generated on-chip, a less sophisticated (and less
expensive) tester can be use.
 The internal logic of the chip can be designed to operate at the high functional
frequencies while the I/O ports usually operate at lower frequencies.
Our Tessent TestKompress and Tessent FastScan automated test pattern generation (ATPG)
tools offer advanced capabilities to help incorporate the PLL clock logic into the test program.

Figure 1. On-chip PLL Example

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Figure 1 shows a depiction of a PLL on the device. As you can see, several external signals go
into the PLL and clock control logic and two internal chip signals come out of the control logic
to drive the internal clocks throughout the design. Our ATPG tools allow you to simply describe
the behavior and relationship between these external and internal signals to enable the use of the
internal clocks when creating the at-speed test patterns. This description is in the form of named
capture procedures within the test procedure file, which defines how the scan chains and test
logic operate for the device.
Some clock control logic is made programmable by using control registers that change the clock
outputs based on certain control values. The values of those control registers can be specified
with corresponding clocks in named capture procedures. Our tools will automatically load these
values into the device with each scan pattern to produce the desired clocking as depicted in
Figure 2.

PLL
system_clk
CLOCK GATING
LOGIC Gated Clocks
begin_ac CONTROLLER
scan_in 0 0 1 1

procedure capture F1_F3 =

// *** have ATPG load internal registers ***
mode internal =
condition /pll_clk_reg/cell0/q 1;
condition /pll_clk_reg/cell1/q 1;
condition /pll_clk_reg/cell2/q 0;
condition /pll_clk_reg/cell3/q 0;
cycle =
...
end;
… more cycles as needed …
end;
mode external =
...
end;
end;

Figure 2. Programmable Clock Controller and Named Capture Procedure Example

The condition statements are placed in the named capture procedures to ensure that the correct
values get loaded into the control register; in this example the values are 0011. This is a much
more efficient way to supply those register values than from primary input pins or from a special
boundary scan register setup. Note that the scan cells defined within condition statements can be
located anywhere within any scan chain. Condition statements also support scan cells within
Tessent TestKompress designs.

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Accounting for False and Multicycle Paths

The use of static timing analysis (STA) is prevalent in today’s design flows. It is a key step to
analyze or verify the design’s timing and to find the critical paths. A key step of the STA
process is to define the false and multicycle paths in the design, so that these exceptions to the
regular cycle-to-cycle timing are not timing optimized. It is important to do this correctly to
simplify layout and to not process unnecessary timing closure issues.
When creating test patterns in an ATPG tool like Tessent FastScan or Tessent TestKompress, it
is very important to provide the tool with this same timing exception information, especially for
transition test patterns. It doesn’t make sense to try to test paths at-speed if they are not designed
to operate that way in the first place! Failing to account for these timing exceptions when
creating at-speed test patterns can lead to incorrect fails when the patterns are run on the test
equipment against the devices. Good devices could get labeled bad by an incorrect test,
decreasing the yield.
Fortunately, it is easy to bridge this gap between the STA and ATPG tools. The STA tool can
write out all the timing information, including the timing exceptions, in an industry standard file
format called SDC (Synopsys Design Constraints). The SDC file can then be directly read into
either Tessent FastScan or Tessent TestKompress so that the ATPG tool can determine the
correct expected results for each test pattern taking into account the timing exceptions. This is
very important to produce accurate test coverage numbers. It also eliminates simulation
mismatches when the at-speed test patterns are simulated with timing in a functional simulator.
The old method of accounting for false and multicycle paths in at-speed test patterns was to
determine the path source or sink scan cells and then to constrain those cells to an X value during
pattern generation. This method is cumbersome and is overly pessimistic, leading to lower test
coverage and quality. For example, take a look at Figure 3, which shows a sample circuit and a
path defined as multicycle.

Multicycle Path
U1 G1 G3
G5 G6 U5
D Q
D Q
CK
CK

U2
D Q

CK

G4 G7
U3 G2 U6
D Q D Q

CK CK

Figure 3. Multicycle Path Example

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In this example, the only path specified as multicycle is from U1 to U5 across the top of the
diagram. With the old method, an X cell constraint would be placed on cell U5. That results in
lower test coverage because other paths that would use U5 as an observation capture location
would not be testable. This problem is alleviated with the false and multicycle path handling in
our ATPG tools. With our solution, the paths from U2 to U5 and U3 to U5 are still testable,
leading to better test coverage.

At-Speed Test Options

There are many options to perform at-speed tests. Here is a quick summary of various options
that are supported by our tools and their advantages. More details can be found in application
notes.
 Broadside patterns: pattern is loaded then two at-speed pulses are applied in functional
mode (scan enable = 0 for launch and capture cycles). This is a popular approach since
launch and capture are in a functional mode and less likely to over test through non-
functional paths.
 Launch-off-shift patterns: the at-speed launch occurs when the last value is loaded into
the scan cell, so scan enable must turn off between launch and capture. Effective launch-
off-shift usually needs pipelined scan enable to avoid routing it as a clock. It is also
necessary to use SDC false and multicycle path handling to avoid over testing. These
types of patterns are easier for ATPG tools to generate and usually result in a smaller
pattern count than broadside patterns.
 Pipelined scan enable: simple logic is placed between the primary input scan enable and
scan cells. These logic blocks allow scan enable to switch between at-speed launch and
capture cycles.
 Burst-mode ATPG: A technique to refine at-speed launch and capture clock edge
placement by applying several at-speed shift cycles before the launch. This reduces
power droop and may make at-speed edge placement more accurate during capture. It is
a form of pipelined launch-off-shift. False and multicycle path consideration is
necessary.
 MacroTest: applies specific sequences of functional patterns to an internal instance
through scan pattern loads and captures. Typically used for small memory test with
standard algorithms. It can also support at-speed test using on-chip PLLs.
 Test to and from memories: it is important to consider faults that are captured at or
launched from memories. Current ATPG capabilities enable at-speed test to or from
memories as end points.
 Transition fault model: An at-speed test fault model that targets a potential delay at every
gate terminal. ATPG randomly finds a path that propagates through the gate terminal
being tested. This is currently the standard practice for at-speed test.
 Path delay fault model: An at-speed test fault model that targets specific paths known to
have minimum slack and have a potential for subtle timing issues. Fault sites are defined

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from static timing analysis selection of the minimum slack paths. These types of tests are
normally used to access silicon process variations and help with speed binning parts.
 Timing-aware ATPG: this is an at-speed test method that performs a test similar to
transition fault model tests but tries to propagate faults along the longest paths possible
for each fault site. Timing information is read in from a Standard Delay Format (SDF)
file to help the ATPG tool figure out which paths to use. This type of pattern is expected
to detect more small delay defects than traditional transition patterns because it is
creating tests with the smallest slack margins.

Newer Fault Models

Several fault models are available to further improve test quality and detect some defects that
may otherwise escape test. Two of the newer models in our tools include embedded multiple
detect and a 4-way bridging fault model. Both of these fault models target signal-to-signal
bridging types of defects.
For the multiple detect fault model, each fault is detected a number of times. This method
improves test quality without increasing the pattern count and works for stuck-at and at-speed
test patterns too. The user can specify the desired or guaranteed number of detections for each
fault. This is different than regular ATPG, where once a fault is detected by a test pattern, it is
removed from the fault list. By testing the same fault location multiple times with randomly
different test patterns, the probability of detecting bridging defects increases.
An accurate way to target the most probable bridging defects is to extract a list of bridging
candidates from the chip layout and then create test patterns that target the two candidate nets in
all possible combinations. This can be done with our 4-way bridging fault model. The process
is simple with our direct ties into the Mentor Graphics Calibre tools. Special bridging rules
can be extracted from the physical database to identify those design locations that are most likely
to have bridging problems as shown in the examples in Figure 4. Those net pairs are then fed
into Tessent FastScan or Tessent TestKompress to create the bridging test patterns.

Figure 4. Potential Net Pair Bridging Areas

Managing Test Time & Data Volume

The drawback of adding at-speed test or using new fault models is that the test pattern volume
required to keep quality high is expanding many-fold. This is compounded by the fact that the
designs themselves keep getting larger and hence there is more circuitry to test. Over the last
few years, Tessent TestKompress has become the standard test compression approach in the
industry.

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Tessent TestKompress adds a small amount of logic that is only placed between the scan channel
interface and the internal scan chains. It does not alter the core design at all. The solution can
automatically handle unknown values (X states) in the design without having to add special logic
to control them. This also keeps the test coverage high when dealing with at-speed test of false
and multicycle paths.
By using this solution, the highest possible test coverage can be obtained without impacting
tester throughput. It works with at-speed test and PLLs as described in this paper and can handle
all the new and emerging fault models. Tessent TestKompress is very flexible and is used in
many modular and hierarchical design approaches.

Fitting in the Major Design Flows

When choosing silicon test tools, it is important to make sure that they are tested and supported
in the design flow that is used. Both Tessent FastScan and Tessent TestKompress have been
around for a number of years and have been extensively used in all the major design flows on the
most challenging chip designs. The RTL logic created by Tessent TestKompress can be
synthesized in any of the leading synthesis tools available.
Whether you have a customer owned tooling (COT) flow or work with an ASIC provider or a
foundry, the Mentor Graphics silicon test tools fit well into the flow. In fact, the top two chip
foundries, TSMC (Taiwan Semiconductor Manufacturing Corp.) and UMC (United
Microelectronics Corp.), have tested and endorsed the silicon test tools from Mentor Graphics in
their system-on-chip (SoC) design flows.

Conclusion
Implementing at-speed scan test is necessary for today’s deep sub-micron designs to ensure low
DPM rates. Automated handling of timing exceptions is available to provide reliable and high
quality at-speed tests. To help companies reach their high quality test goals, Mentor Graphics
has worked hard to implement key functionality and new capabilities and fault models in our
ATPG products to give you the tools and solutions you need to keep DPM low while also
keeping your cost of test as low as possible. For example, with Tessent TestKompress, you can
get up to and over 100X compression of both test time and test data volume while using on-chip
clocks and all the major fault models. It is an elegant and flexible tool that works with multiple
design types and design flows.
Please check the references for more details and examples.

References
Matthais Beck et.al., Logic Design for On-Chip Test Clock Generation – Implementation Details
and Impact on Delay Test Quality, In proc. of DATE, 2005.
Brady Benware et. al., Impact of Multiple-Detect Test Patterns on Product Quality, In proc. of
ITC, 2003.
Jeroen Geuzebroek et.al., Embedded Multi-Detect ATPG and Its Effect on the Detection of
Unmodeled Defects, In proc. of ITC, 2007.
PLL Control Circuit Example for FastScan/TestKompress, Mentor Graphics Application Note
5202, July 2005.

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At-speed ATPG testing with False and Multicycle Paths, Mentor Graphics Application Note
5201, February 2007.
At-speed ATPG testing using FastScan and TestKompress, Mentor Graphics Application Note
3007, February 2007.
Greg Aldrich and Brady Benware, Good bridge testing needed, EE Times, September 30, 2004.
DFT with Pattern Compression – TestKompress - TSMC Reference Flow Release 6.0, Taiwan
Semiconductor Manufacturing Company, Ltd.

UMC Multi-Vt and DFT Reference Flow Users’ Guide, United Microelectronics Corporation.
Jerry Chang et. al., Test Quality Improvement with Timing-aware ATPG: Screening small delay
defect case study, Poster 23, ITC, 2008.

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