DFT - SCAN INSERTION

Presented by
G Maheswara Murthy
DFT Engineer, Obsidian solutions Pvt. ltd.
 THE IDEA OF SCAN
• SCAN is the idea using which one can control the inputs of the various gates and flip-
flops inside the chip and also observe the outputs from the internal flops in a planned
manner.
• Replace all selected flops with scan flops.
• The chip will initially taken into a special mode, called “scan mode” by setting an input
pin to an appropriate value.
• Connect each scan cell to make into a scan chain.
• One of the primary input pins will feed the input of the first flop in this chain in the scan
mode.
• The output of the very last flop will be taken to a primary output.
 SCAN BENEFITS
• Highly automated process.
• Using scan insertion tools, the process for inserting scan circuitry into a design is highly
automated, thus requiring very little manual effort.

• Highly-effective, predictable method.

• Scan design is a highly-effective, well-understood, and well-accepted method for generating
high test coverage for your design.

• Ease of use.
• Using scan methodology, you can insert both scan circuitry and run ATPG without the aid of a
test engineer.
 MODES OF OPERATION
Scan cells Operated in three modes:
Normal mode
 All test signals are turned off.
 The scan design operates in the circuit’s original functional configuration.

DFT MODE:
 Shift mode
 To shift data into and out of the scan cells.
 Capture mode
 To capture test response into scan cells.
 TYPES OF SCAN CELL DESIGNS
• Muxed – D Scan Cell
 TYPES OF SCAN CELL DESIGNS
• Clocked-Scan Cell
 TYPES OF SCAN CELL DESIGNS
• LSSD SCAN CELL
 COMPARISON OF CELL DESIGNS
Scan cell
Advantages Disadvantages
Type

• Supported by existing automation

• Additional Multiplexer adds
Muxed –D tools
delay
• Compatibility to modern designs

Clocked • No Performance degradation • Additional clock routing

• Insert scan into a latch based design

LSSD • Increase routing complexity
• No clock Skew
 SCAN METHODOLOGY
• Full Scan Methodology
• All sequential cells replaced by corresponding scan counterparts
• Sequential cells not scanned are black box cells
• Combinatorial ATPG Algorithm can be used

• Partial scan Methodology

• Not all sequential cells are replaced by corresponding scan counterparts
• Non-scanned cells are tested by sequential ATPG Algorithm
 WORKING OF SCAN CHAIN
(MUXED -D)
Scan Insertion

Circuit Scan cell

TM SE
Operation mode

Functional Normal 0 0

Shift operation Shift 1 1

Capture
Capture 1 0
operation
 SCAN DESIGN - DISADVANTAGES
• Area Overhead
• Performance degradation
• Long test application time
• Not applicable to all designs
• High power dissipation during testing
SCAN DESIGN FLOW
 GENUS DFT - INPUT AND OUTPUT
FILES
 Input Files  Output Files
RTL Files
• Synthesis Libraries • Gate Level Netlist
Synthesis Constrain
Libraries t File
• RTL Files (.v files) • SDC Constraint for DFT
• SDC Files Inserted Logic
SDC Logic • ScanDEF Files
Constrain Abstract
t
Genus Model
• Scan Abstract Model
DFT
• Logic Abstract Mode

Scan
• Testability analysis
ScanDEF
Abstract
File
Model Files(Reports)
• ATPG Interface (.tcl, Pin-
Testability ATPG
Analysis Interface assign file)
PIN ASSIGN FILE DEFINITIONS
 DFT SCAN DRC
• DFT-301 : DFT Clock Rule Violation.
• Clock signal is not controllable. Affected registers will be excluded from scan design.
Automatic fixing : fix_dft_violations -violations vid_2_async -test_control TM
• DFT-302 : DFT Async Rule Violation.
• DFT-317 : Potential X-source Violation.
• A potential x-source generator exists in the design that could affect ATPG. Insert shadow
logic or use the command 'fix_dft_violations'.
• DFT-415 : Could not connect scan chains.
• DFT-511 : The scan flop mapped for DFT fails the DFT rule checks. The flop is not
included in a scan chain.
 DFT SCAN DRC
• DFT-302 : DFT Async Rule Violation.

TPI

• Flip-flop A requires a 0 to its reset

pin during test mode
• Flip-flops B, C, and D require a 1
 DFT SCAN DRC
• DFT-317 : Potential X-source Violation.
• Violations are fixed for logic abstract models and timing_models whose instances have
known pin directions.
• Violations are not fixed for blackbox models whose instance pins are internally modeled as
bidirectional pins.
 DFT SCAN DRC
• Gated Clock Violation
• The clock pin of the flip-flop is not controllable because it is gated by an internally-generated
enable signal.
• For each group of violations that share logic on the clock path and on the non-clock path, the
Genus-DFT engine attempts to fix the violation by inserting logic on the non-clock path first.

FIX
IMPROVING TESTABILITY IN CLOCK GATING
• Clock gating raises some concerns for ATPG. These concerns involve enabling clock
controllability and scan testing as well as optimizing ATPG results.
 SCAN-ENABLE SIGNAL VERSUS
TEST-MODE SIGNAL
• The scan-enable and test-mode signals differ in the following ways:
• A scan-enable signal is active only during scan mode.
• A test-mode signal is active during the entire test (scan mode and parallel mode)

Test Coverage With Scan-Enable Test Coverage With Test-Mode Signal

Signal
 CLOCK GATING
• It is used to save power dissipation by turning off the clock to the modules that are not in
use.
• A simple AND gate can be used as clock gating. But it will produce glitches
LATCH BASED CLOCK GATING
 LOCK UP LATCH
• Lock-up latches are basic transparent latches (like D latches) used in scan chains.
• They’re inserted between regular flip-flops that have a high chance of failing to hold data
violation due to long clock delays (skew) or mismatched clock domains.
• These latches essentially act as temporary storage points.
• Latches placed by the designer during the design phase typically aren't included in the
scan chain used for testing.
• In contrast, lock-up latches inserted by the Design for Testability (DFT) engineer
specifically to address challenges with mixing clock edges (positive and negative) or clock
domains become part of the scan chain.
 CLOCK - EDGE AND DOMAIN
MIXING
• EDGE Mixing: Keeping both positive edge and negative edge triggered flops in same scan
chain.
1. Positive Positive
2. Negative Negative
3. Negative Positive
4. Positive Negative This will create a Problem

• DOMAIN Mixing: Keeping flops with different scan clocks in same scan chain.
1. CLK A & CLK B arrive at same time
2. CLK B arrive early
3. CLK A arrive early This will create a Problem
 CASE 1 : POS - POS
• Q1 changes to high at the 1st active edge of its clock.
• Q2 changes to high at 2nd active edge of its clock.
 CASE 2 : NEG - NEG
• Q1 changes to high at the 1st active edge of its clock.
• Q2 changes to high at 2nd active edge of its clock.
 CASE 3 : NEG - POS
• Q1 changes to high at the 1st active edge of its clock.
• Q2 changes to high at 2nd active edge of its clock.
 CASE 4 : POS - NEG
• Q1 is becoming high at the 1st active edge of its clock .
• Q2 is also becoming high at 1st active edge of its clock.
• Problem – 2 shifts in the same clock pulse
 CASE 4 : POS – NEG
( RESOLVED )
• Q1 changes to high at the 1st active edge of its clock.
• Q2 changes to high at the 2nd active edge of its clock.
 CASE 1 – CLK A & CLK B
ARRIVES AT SAME TIME
• Q1 changes to high at the 1st active edge of its
clock.
• Q2 changes to high at 2nd active edge of its clock.
 CASE 2 – CLK B ARRIVES EARLY
• Q1 changes to high at the 1st active edge of its clock.
• Q2 changes to high at 2nd active edge of its clock.
 CASE 3 – CLK A ARRIVES AT
EARLY
• Q1 changes to high at the 1st active edge of its clock.
• Q2 also changes to high at 1st active edge of its clock
• This will create a Problem
SOLUTION FOR CASE 3 ISSUE