Q L Question A B C D E Answer

No ev
el
1 A one-to-four line demultiplexer is 1bit 2 BIT 4 bit 8 bit A
to be implemented using a memory.
How many bits must each word have
?
2 PAL refers to ____________ Programmable Programmable Programmable Array Programmable AND C
Array Loaded Logic Array Logic Logic

3 Outputs of the AND gate in PLD is Input lines Output lines Strobe lines Control lines
known as

4 PLA is used to implement A complex A simple A complex A simple C

sequential circuit sequential combinational combinational circuit
circuit circuit
5 Which type of device FPGA are? SLD SROM EPROM PLD D

6 If a PAL has been programmed once Its logic capacity Its outputs are Its outputs are only It cannot be D
is lost only active active LOW reprogrammed
HIGH
7 A demultiplexer is used to Route the data sequential both (a) and (b) Select data from A
from single input logic circuits several inputs and
to one of many route it to single
outputs output
8 The digital multiplexer is basically a AND-AND OR-OR AND-OR OR-AND C
combination logic circuit to perform
the operation
9 A combinational logic circuit which Decoder Multiplexer Encoder Demultiplexer B
generates a particular binary word or
number is
10 Which of the following circuit can Multiplexer Demultiplexer Decoder Digital counter A
be used as parallel to serial converter

11 A > B = 1, A > B = 1, A > B = 1, A > B = 0, B

The binary numbers A =
A< B = 0, A< B = 0, A< B = 1, A < B = 0,
1100 and B = 1001 are A = B =1 A=B=1
A=B=0 A=B=1
applied to the inputs of a
comparator. What are the
output levels?
12 How many data select lines are 1 2 3 4 D
required for selecting 16 inputs?

13 How many input lines are required 1 2 3 4 D

for decoder to get 16 outputs?

14 PLA refers to ____________ Programmable Programmable Programmable Array Programmable Logic B

Loaded Array Logic Array Logic AND

15 A decoder can be used as a typing all enable typing all data- typing all data-select D
using the
demultiplexer by . pins LOW select lines lines HIGH
input lines
LOW
for data
selection and
an enable
line
for data input
16 In PLD, there are provisions to High reliability High The desired logic The desired output C
perform interconnections of the conductivity implementation
gates internally, because of
17 Why antifuses are implemented in a To protect from To increase the To implement the As a switching C
PLD high voltage memory programmes devices
18 How many types of PLD is 2 3 4 5 A

19 Logic circuits can also be designed RAM ROM PLD PLA C

using

20 How memory expansion is done? By increasing By decreasing By connecting By separating C

the supply the supply Memory ICs Memory ICs
voltage of the voltage of the together
Memory ICs Memory ICs
21 How many 16K * 4 RAMs are 2 4 6 8 D
required to achieve a memory with a
capacity of 64K and a word length
of 8 bits?
22 PLD contains a large number of Flip-flops Gates Registers All of the Mentioned D

23 The inputs in the PLD is given NAND gates OR gates NOR gates AND gates D
through

24 PLA contain AND and OR NAND and OR NOT and AND NOR and OR arrays A
arrays arrays arrays

25 For programmable logic functions, PLA PAL CPLD SLD B

which type of PLD should be used

26 The complex programmable logic A language AND/OR Global Field-programmable C

device contains several PLD blocks compiler arrays interconnection switches
and matrix
27 A PLA is similar to a ROM in It has capability It It doesn’t provide It hasn’t capability to C
concept except that to read only hascapability full decoding to the write only
to read or write variables
 operation
28 The difference between a PAL & a PALs and PLAs The PLA has a The PAL has a The PAL has more B
PLA is are the same programmable programmable OR possible product
thing OR plane and a plane and a terms than the PLA
programmable programmable AND
AND plane, plane, while the
while the PAL PLA only has a
only has a programmable AND
programmable plane
AND plane
29 How many address bits are required 4 KB 8 KB 12 KB 16 KB C
to select memory location in
Memory decoder
30 How many 1024 * 1 RAM chips are 4 6 8 12 C
required to construct a 1024 * 8
memory system
31 PLAs, CPLDs, and FPGAs are all SLD PLD EPROM SRAM B
which type of device?

32 The ROM is a ___________ Combinational Sequential Magnetic Circuit Static Circuit A

Circuit Circuit

33 In ROM, each bit is a combination Memory Unit Storage Class Address Memory Word C
of the address variables is called
___________
34 Applications of PLAs are Registered PALs Configurable PAL programming All of the Mentioned D
PALs

35 Which of the following is not a type RAM ROM FPROM EEPROM D

of memory?
36 RAM is also known as RWM ROM MAR MBR A

37 How many types of RAMs are? 2 4 6 3 A

38 ASIC stands for Application Applied Application Specific Applied Specific C

Special Special Integrated Circuits Integrated Circuits
Integrated Integrated
Circuits Circuits
39 A memory is a collection of Unit cells Storage cells Data cells Binary cells B

40 ROM consist of NOR,AND NAND,NOR AND,OR ARRAY NAND.OR ARRAYS D

ARRAYS ARRAYS