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Programmable Logic Devices (PLD’S) • Programmable Advantages and Disadvantages of PLA  Advantages • A Advantages and disadvantages of Flash ADC
logic device is an IC that are user configurable and is PLA can have large N and M permitting implementation of
capable of implementing logic function. • Programmable equations that are impractical for a ROM (because of the
logic devices can be programmed to perform specified number of inputs, N, required • A PLA has all of its product
logic functions and operations by the manufacturer or by terms connectable to all outputs, overcoming the problem
the user. • They are general general purpose purpose chips of the limited inputs to the PAL Ors. • Some PLAs have
for implementing implementing logic circuits circuits which outputs outputs that can be complemented,
contains a collection of logic gates that can be customized complemented, adding POS functions  Disadvantages •
in different ways. • The purpose of a PLD device is to Often, the product term count limits the application of a
permit elaborate digital logic designs to be implemented PLA. • Two-level multiple-output optimization is required
by the user in a single device. • Can be erased electrically to reduce the number of product terms in an
and reprogrammed with a new design,making them very implementation, helping to fit it into a PLA. • Multi-level
well suited for academic and prototyping. circuit capability available in PAL not availaable in PLA. PLA
Advantages of PLD’s • Programmable logic devices use requires external connections to do multi-level circuits
much less board space for an equivalent amount of logic. • 2. Successive approximation ADC • Successive
With programmable logic, designs can be readily changed PLA Example: • So, we require four programmable AND approximation ADC consists of a comparator, Successive
changed without without rewiring rewiring or replacing gates & two programmable OR gates for producing those approximation Register (SAR) and DAC. • A DAC is used to
replacing components components. • A logic design can two functions. The corresponding PLA is shown in the generate approximations of the input voltage. • A
generally be implemented faster and with less cost with following figure. • Each programmable AND gates have the comparator is used to compare Vin and V appr. • In each
programmable logic than with fixed-function logic. • To access of both normal and complemented inputs of cycle SAR finds one output using comparator. • To start
implement small segments of logic, it may be more variables, only the required product terms need to be Example of MOORE MODEL conversion, conversion, set SC= 1 . When conversion
efficient to use fixed-function logic. programmed. • All the formed product terms appear at the conversion ends EOC = 1
input of each programmable OR gate, but only the
Programmable Read Only Memory (PROM) • Read Only required product terms of each function X and Y need to
Memory is a memory device, which stores the binary be programme
information permanently. That means, we can’t change
that stored information by any means later. • If the ROM
has programmable feature, then it is called as
Programmable ROM. The user has the flexibility to
program the binary information electrically once by using
PROM programmer • PROM is a programmable logic Here output Y depends only on the states Q0 and Q1
device that has fixed AND array & Programmable OR array. Example of MEALY MODEL
The block diagram of PROM is shown in the following
figure.

8 Bit SAR ADC

The figure below shows a successive approximation type
Generally Read Only Memories (PROM) have: • n input PAL Vs PLA • PALs have the same limitations as PLAs (small ADC that converts analog signals to 8-bit digital data. • It
lines (Address Lines), • m output lines, and • 2 n decoded number of allowed AND terms) plus they have a fixed OR has an 8-bit Successive Approximation Register (SAR)
plane • less flexibility than PLAs • PALs are simpler to
min terms.  Here, the inputs of AND gates are not of which checks whether each of the 8 bits is a 1 or a 0 by trial
manufacture, easier to program, cheaper, and faster Here output Y depends only on the states Q0, Q1 and A and error
programmable type. So, we have to generate 2 n product
(better performance) • PALs also often have extra circuitry Differences between Mealy and Moore models
terms by using 2 2 n AND gates having n n product terms
connected to the output of each OR gate . The OR gate plus
by using 2 n AND gates having n inputs each.  Here, the
this circuitry is called a macrocell
inputs of OR gates are programmable. That means, we can
program any number of required product terms, since all Implementation of Half adder in Verilog: 1. Gate Level
d. Field Programmable Gate Array (FPGA) • The field-
the outputs of AND gates are applied as inputs to each OR Modelling
programmable gate array (FPGA) is an integrated circuit
gate.  Therefore, the outputs of PROM will be in the form
that consists of internal hardware blocks with user-
of sum of min terms.
programmable interconnects to customize operation for a
Let us implement the following Boolean functions using
specific application. The interconnects can readily be
PROM. • The given two functions are having three
reprogrammed, allowing an FPGA to accommodate
variables. Two functions need to be implemented, so two
changes to a design or even support a new application
OR gates
during the lifetime of the part. • An FPGA is generally
needed
generally more complex complex and has a much higher
density density than a CPLD, although their applications
can sometimes overlap. • As mentioned, the SPLD and the
CPLD are closely related because the CPLD basically
contains a number of SPLDs. • The FPGA, however, has a When the start command is given, the first clock is applied
different internal structure (architecture), as illustrated in and SAR sets b1 to 1 while all other bits are made 0. So the
Figure. • The three basic elements in an FPGA are the logic trail code in SAR become 10000000. • This trial code is
block, the programmable interconnections, and the convert to analog voltage Vr and is compared with input
Vin which the analog signal whose digital equivalent is to Implementation of Half adder in Verilog: 2. Data Flow
input/output (I/O) blocks
be found. If Vin is greater than Vr, it means that trail code Modelling
10000000 is less than the correct digital digital value of Vin.
b. Programmable Array Logic (PAL) • The PAL is the
Comparator Comparator output becomes becomes 1. • In
opposite of the ROM, having a programmable set of ANDs
that case, b1 is retained as 1 and next bit b2 is set to 1, the
combined with fixed ORs. • PAL is a programmable logic
trial code becomes 11000000. The trial code is converted
device that has Programmable AND array & fixed OR
to analog voltage Vr by DAC and is compared with Vin. . If
array. • The PAL structure structure allows any sum-of
Vin is greater than Vr, it means that trail code 11000000 is
products products (SOP) logic expression with a defined
less than the correct digital value of Vin. Comparator
number of variables to be implemente
output becomes 1
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1. Simultaneous or Flash type ADC • A simultaneous or Implementation of Full adder in Verilog
flash type ADC is based on comparing an analog input
voltage with a set of reference voltages . • It is also known
as parallel ADC. • It is the fastest fastest ADC and less
complex complex compared compared to others. • An n bit
flash ADC uses op-amp comparators and resistors. • For
e.g., a 2-bit Flash type ADC requires 3 comparators and 4
resistances to divide the voltage
Here, the inputs of AND gates are programmable. That Simultaneous or Flash type ADC • The block diagram of a
means each AND gate has both normal and complemented 2-bit flash type ADC is shown below, • The non inverting
inputs of variables. So, based on the requirement, we can terminals of all comparators are connected to analog input
program any of those inputs. So, we can generate only the Vin. • The inverting terminals are connected to reference
required product terms by using these AND gates. • Here, voltage V/4, 2V/4, 3V/4
the inputs of OR gates are not of programmable type. So, Bit b1 is retained as 1 and next bit b2 is set to 1, the trial
the number of inputs to each OR gate will be of fixed type. code becomes 11100000. The trial code is converted to
Hence, apply those required product terms to each OR analog voltage Vr by DAC and is compared with Vin.
gate as inputs. Therefore, the outputs of PAL will be in the Suppose that Vin is less than Vr, it means that trail code
form of sum of products form. 11000000 is greater than the correct digital value of Vin.
PAL Example: • Let us implement the following Boolean Comparator output becomes 0. • When comparator
functions using PAL. X = AB + AC’ Y = AB’ + BC’ • There are output is 0, SAR understands that the bit which was set i.e.
4 product terms and 2 sum terms, so PAL requires 4 When the logic blocks are relatively simple, the FPGA b3 should be reset. And the next bit b4 is tested whether it
programmable AND gates and 2 fixed OR gates • The architecture is called fine-grained. • When the logic blocks is 0 or 1 by setting it to 1. The trail code is now 11010000.
programmable AND gates have access to both are larger and more complex, the architecture is called The steps discussed before will be repeated until all bits
complemented complemented and non- completed coarse-grained. • The I/O blocks are on the outer edges of are checked. When all bits are checked, EOC (End of
variables. The the structure and provide individually selectable input, Conversion) is send by SAR and the 8-bit trail code at this
symbol ‘x’ output, or bidirectional bidirectional access to the outside stage is the correct digital data corresponding to analog
indicates outside world. • The distributed programmable input Vin
programmable interconnection matrix provides for interconnection of the
connections • The logic blocks and connection to inputs and outputs. Large
Structural Vs Behavioural Level
inputs of OR gates FPGAs can have tens of thousands of logic blocks in Simultaneous or Flash type ADC • The output of a
are of fixed type. addition to memory and other resource comparator is in positive saturation state when the voltage
So, the necessary An FPGA, then, is much more than an array of gates. It’s an at the non-inverting or +ve terminal is greater than at
product terms are array of carefully designed and interconnected digital inverting or –ve terminal. Else comparator output is in
connected to subcircuits that efficiently implement common functions negative saturation. • When analog input Vin is less than
inputs of each OR while also offering very high levels of flexibility. The digital V/4, comparator C1 output is 0. If Vin is less than V/4, it will
gate. So that the subcircuits are called configurable logic blocks (CLBs), and be surely less than 2V/4 and 3V/4. SO comparators C2 and
OR gates produce they form the core of the FPGA’s programmable-logic C3 output also is 0. • When analog input Vin is between
the respective Boolean functions. The symbol ‘.’ is used for capabilities • The CLBs need to interact with one another V/4 and V/2 comparator C1 output is 1 and C2 and C3
fixed connections. and with external external circuitry circuitry. For these output is 0. When Vin is between V/2 and 3V/4, C1=C2=1
Advantages and Disadvantages of PAL  Advantages of purposes, purposes, the FPGA uses a matrix of and C3=0. When Vin is between 3V/4 and V, C1=C2=C3=1
PAL: • For given internal complexity, a PAL can have larger programmable interconnects and input/output (I/O) Simultaneous or Flash type ADC
N and M • Some PALs have outputs that can be blocks. • An I/O block consists of various components that Since this is a 2-bit ADC, output digital data should have 2
complemented, adding POS functions • No multilevel facilitate communication between the CLBs and other bits, let this be b2 and b1. There are 4 combinations that
circuit implementations in ROM (without external external components on the board. These include pull-up/pull- b2 b1 can take. • The coding circuit converts the Basic Gates
connections connections from output to input). PAL has down resistors,buffers,and inverters. comparator output to 2-bit digital output. That is the
outputs outputs from OR terms as internal inputs to all Advantages and Disadvantages of FPGA coding circuit is a combinational circuitis a combinational
AND terms, making implementation of multi-level circuits circuit made of gates that take C1C2C3 as input and
easier.  Disadvantage of PAL: • ROM guaranteed to outputs b2b1.
implement any M functions of N inputs. PAL may have too 3 bit flash type ADC
few inputs to the OR gates.
PROM vs PLA • PROM: realization of a set of Boolean
functions is based on min term canonical expressions. – No
minimization necessary. • PLA: the AND gates are capable
of generating product product terms that are not
necessarily necessarily minterms minterms. – Realization
using PLA is based on sum-of-product expression that may
not be canonical. – Logic designer is bounded by the Example 1 of a Module in Verilog
number of product terms that are realizable by the AND-
array.Simplification is necessary.
c. Programmable Logic Array (PLA) • Compared to a ROM
and a PAL, a PLA is the most flexible having a
programmable set of ANDs combined with a
programmable set of ORs. • PLA is a programmable logic Applications of FPGA
device that has both programmable AND array and a
programmable OR array. Hence it is very flexible. • The
inputs of AND gates are programmable. Each AND gate has
both normal and complemented inputs of variables. We
can generate only the required required product product
terms by using these AND gates. • The inputs of OR gates
are also programmable. So, we can program any number
of required product terms, since all the outputs of AND
gates are applied as inputs to each OR gate.
The outputs of PAL will be in the form of sum of products
form