ADVANCED DIGITAL SYSTEM DESIGN

UNIT -4 Programmable Logical Devices and Hazards in VHDL

(Theory)

Hazards

An unwanted switching transient that appears at the output of a circuit is called hazards. Hazards
cause the circuit to malfunction. Main cause of hazard is the different propagation delay to different
path. In combinational circuit, false output is produced. In asynchronous sequential circuit, transition
to a wrong state table happens.

Static hazard

Signal is supposed to remain in a particular value when an input variable changes its value, but
instead the signal undergoes a momentary change. It is further classified as static 0 and static 1
hazard.

Static 1 hazard

The output goes 1 when it should remain 0

Static 0 hazard

The output goes 1 when it should remain 0.

Dynamic hazard

Output changes 3 or 4 times when it should change from 1 to 0 or from 0 to 1.

When the output changes numerous times, the value should only move from 1 to 0 or from 0 to 1
once. When the output changes for 2 neighbouring input combinations at the same time, it is
referred to as dynamic hazard. Example; a circuit changes the output state from 1 to 0 but instead
changes the output state from 1 to 0 then 1, before eventually resting at the proper value of 0.

Elimination of dynamic hazards

Use a synchronous design where a clock signal synchronous the circuits operation and stabilizes the
output. Ensure that all prime implicants are included in the circuits realizations which helps to
prevent the emergence of dynamic hazards.

Hazards in sequential circuits

In synchronous sequential circuit, hazards are not of concern. In asynchronous sequential circuit,
hazards may cause the circuit to go to wrong stable state.

Essential hazards

It occurs in asynchronous sequential circuits. It is caused because of unequal delay along 2 or more
paths that originate from same input. This can be eliminated by adjusting the number of delays in
the affected path.

Eliminating essential hazards

A momentary 0 signal applied to the S or R input of a NOR latch will have no effect on the state of
latch. A momentary 1 signal applied to the S or R input of a NAND latch will have no effect on the
state of the latch.

Programmable Logic Device (PLD)

A Programmable Logic Device (PLD) is a type of digital electronic component used to implement
custom logic circuits. Unlike fixed-function logic gates, PLDs can be programmed by the user to
perform specific logic operations, making them highly flexible and suitable for a wide range of digital
applications.

PLDs are widely used in digital system design because they allow for quick prototyping, easy
modification, and integration of complex logic functions without the need for custom hardware
manufacturing.

Types of Programmable Logic Devices

PLDs are broadly classified into the following categories based on their complexity and
programmability:

1. Simple Programmable Logic Devices (SPLDs)

These are basic PLDs with limited logic resources and are typically used for implementing simple
combinational or sequential logic functions.

 Programmable Read-Only Memory (PROM):

o Consists of a fixed AND array and a programmable OR array.

o Mainly used to implement combinational logic using look-up tables.

o Not reprogrammable after initial programming.

  Programmable Logic Array (PLA):

o Both the AND and OR arrays are programmable.

o Offers more flexibility compared to PROM.

o Capable of implementing any combinational logic function.

 Programmable Array Logic (PAL):

o Features a programmable AND array and a fixed OR array.

o Faster and simpler to manufacture than PLAs.

o Commonly used in small-scale logic applications.

2. Complex Programmable Logic Devices (CPLDs)

 CPLDs consist of multiple SPLD-like blocks integrated into a single chip.

 They offer a moderate amount of logic resources and are suitable for medium-complexity
digital designs.

 They are non-volatile, meaning they retain their programmed configuration even after power
is turned off.

 Commonly used for control logic, state machines, and glue logic.

Examples: Xilinx XC9500 series, Altera MAX7000 series.

3. Field Programmable Gate Arrays (FPGAs)

 FPGAs are highly complex PLDs with a large number of logic gates and configurable logic
blocks (CLBs).

 They feature programmable interconnects, logic blocks, and input/output blocks.

 FPGAs are suitable for implementing high-performance, parallel, and complex digital
systems.

 Most FPGAs are volatile and require configuration each time the device is powered on.

Examples: Xilinx Spartan series, Intel (Altera) Cyclone series.

Programmable Read Only Memory

PROM is a type of non-volatile memory and also considered a basic form of a Programmable Logic
Device (PLD). It is primarily used to store combinational logic functions in the form of look-up
tables.

Key Features of PROM:

 Programmable:
The user can program the device once using a special device called a PROM programmer.

 Read-Only:
After programming, the data stored in PROM cannot be changed or erased.
  Non-volatile:
Data is retained even when the power supply is turned off.

Structure of PROM:

PROM consists of two main parts:

 A fixed AND array

 A programmable OR array

The fixed AND array generates all possible combinations of input variables (minterms). The
programmable OR array selects which minterms are used to produce the required output functions.

Working Principle:

1. The inputs are fed to a fixed AND array to generate all possible minterms.

2. The programmable OR array then combines selected minterms to form the required output
logic functions.

3. The user "burns" the desired connections into the OR array during programming.

Applications of PROM:

 Used in implementing simple combinational logic circuits

 Commonly used for storing truth tables, such as for decoders or address translators

 Also used in microprocessor systems for firmware storage

Advantages:

 Simple and cost-effective for small-scale logic functions

 Reliable storage for fixed logic

Limitations:

 Cannot be reprogrammed once written (one-time programmable)

 Not suitable for applications requiring frequent updates

Programmable Logic Array (PLA)

A Programmable Logic Array (PLA) is a type of Programmable Logic Device (PLD) used to implement
combinational logic circuits. It provides a flexible way to realize multiple logic functions in a single
chip by allowing the user to program both the AND and OR logic arrays.

Key Features of PLA:

 Both AND and OR arrays are programmable, making PLAs more flexible than PROMs or PALs.

 Suitable for implementing any arbitrary combinational logic function.

 Typically used in applications where multiple logic functions share input variables.

Structure of PLA:
  Input Lines: Accept external binary inputs.

 AND Array: Programmable to generate selected product terms (minterms).

 OR Array: Programmable to sum the selected product terms to generate output logic
functions.

 Output Lines: Provide the result of logic operations.

Each output in a PLA can be expressed in the Sum of Products (SOP) form.

Working of PLA:

1. Inputs (and their complements) are fed into the programmable AND array, which generates
specific product terms.

2. These product terms are passed to the programmable OR array, which forms the desired
output functions.

3. The resulting logic functions are made available at the output terminals.

Example:

To implement two logic functions like:

 F1 = A·B + A'·C

 F2 = B·C + A·C

A PLA can be programmed to generate these specific product terms in the AND array and combine
them in the OR array to produce the outputs.

Applications of PLA:

 Implementation of custom combinational logic

 Used in control units of processors and digital systems

 Useful in pattern recognition and truth table implementation

Advantages:

 High flexibility due to programmable AND and OR arrays

 Efficient for implementing multiple functions sharing common inputs

 Reduces the need for multiple discrete logic ICs

Limitations:

 More complex and expensive than PROMs and PALs

 Programming is relatively slower

 Not ideal for very large designs (FPGAs or CPLDs are better suited)
Programmable Array Logic (PAL)

Programmable Array Logic (PAL) is a type of Programmable Logic Device (PLD) used for
implementing combinational logic functions. It is designed to be faster and simpler than a
Programmable Logic Array (PLA), making it suitable for small to medium logic designs.

Key Features of PAL:

 Consists of a programmable AND array and a fixed OR array.

 Allows users to program which input combinations (product terms) are generated.

 Outputs are formed by summing selected product terms using a fixed OR array.

 Designed primarily to implement logic functions in Sum of Products (SOP) form.

Structure of PAL:

 Inputs: Binary inputs and their complements are available to the AND array.

 Programmable AND Array: Generates selected product terms (combinations of inputs).

 Fixed OR Array: Combines the outputs of the AND gates to form the final logic functions.

 Outputs: Provide the result of logic operations.

Unlike PLA, only the AND array is programmable in PAL, making it less flexible but faster and easier to
manufacture.

Working of PAL:

1. The inputs are passed into the programmable AND array, where the user can define which
input combinations are required.

2. The resulting product terms are then connected to a fixed OR array, where specific outputs
are formed.

3. Each output line corresponds to a sum of selected product terms.

Example:

To implement logic functions like:

 F1 = A·B + C

 F2 = A·C + B

A PAL can be programmed to generate the required product terms in the AND array, and the fixed OR
array will combine them accordingly to produce the outputs.

Applications of PAL:

 Implementation of medium-complexity logic functions

 Widely used in digital control circuits

 Suitable for replacing multiple logic gate ICs in custom designs

Advantages:
  Faster than PLA due to fixed OR array

 Simpler and cheaper to manufacture

 Well-suited for most general logic applications

Limitations:

 Less flexible than PLA (due to fixed OR array)

 Limited number of product terms per output

 Not suitable for highly complex or large-scale logic functions

Complex Programmable Logic Device (CPLD)

A Complex Programmable Logic Device (CPLD) is a type of Programmable Logic Device (PLD) that
combines multiple logic blocks on a single chip. It is designed to implement medium to large-scale
digital logic circuits and serves as a bridge between Simple PLDs (like PALs and PLAs) and more
complex devices like FPGAs.

Key Features of CPLD:

 Contains multiple programmable logic blocks, also called macrocells, interconnected

through a programmable interconnection matrix.

 Each macrocell can implement one or more logic functions.

 Non-volatile memory (usually EEPROM or Flash) is used for configuration, allowing the
device to retain its logic after power-off.

 Suitable for both combinational and sequential logic designs.

Structure of CPLD:

1. Logic Blocks (Macrocells):

o Each macrocell contains a combination of logic gates, flip-flops, multiplexers, and

sometimes arithmetic units.

o Used to implement logic functions in Sum of Products (SOP) form.

2. Programmable Interconnect Matrix:

o Connects various macrocells and input/output pins.

o Determines how data flows between blocks.

3. Input/Output Blocks (I/O):

o Interface the CPLD with external devices or circuits.

Working Principle:

1. The logic design is written using a Hardware Description Language (HDL) such as VHDL or
Verilog.
 2. The design is synthesized and programmed into the CPLD using electronic design automation
(EDA) tools.

3. On power-up, the CPLD immediately begins operating as programmed due to its non-volatile
configuration.

Applications of CPLD:

 Control units in embedded systems

 Glue logic to interface between different digital components

 State machines and finite state controllers

 Signal processing and protocol decoding

Advantages of CPLD:

 Non-volatile: Retains configuration without needing external memory.

 Fast operation: Deterministic and predictable timing due to a regular internal structure.

 Reprogrammable: Logic functions can be updated multiple times.

 Integrated design: Reduces the need for multiple small ICs, saving space and improving
reliability.

Limitations of CPLD:

 Less logic capacity than Field Programmable Gate Arrays (FPGAs)

 Not suitable for highly complex or parallel processing applications

 Generally slower and less flexible interconnects compared to FPGAs

Field Programmable Gate Array (FPGA)

A Field Programmable Gate Array (FPGA) is a highly flexible and powerful Programmable Logic
Device (PLD) used to implement complex digital circuits. Unlike other PLDs such as PROM, PLA, or
CPLD, an FPGA offers a large number of programmable logic blocks, rich interconnections, and high-
speed performance, making it suitable for high-end digital system design.

Key Features of FPGA:

 Consists of an array of Configurable Logic Blocks (CLBs) or Logic Elements (LEs).

 Includes programmable interconnects for routing signals between logic blocks.

 Supports both combinational and sequential logic.

 Can be reprogrammed multiple times, even after deployment.

 Most FPGAs are volatile, requiring configuration at every power-up (usually loaded from
external memory).

 Supports parallel execution of logic operations.

Structure of FPGA:

1. Configurable Logic Blocks (CLBs):

o Core elements used to implement logic functions.

o Typically consist of look-up tables (LUTs), multiplexers, and flip-flops.

2. Programmable Interconnects:

o Enable custom routing of signals between logic blocks and I/O pins.

3. Input/Output Blocks (I/O):

o Interface between the FPGA and external components or systems.

4. Clock Management and Memory Resources:

o Includes phase-locked loops (PLLs), block RAM (BRAM), and sometimes digital signal
processing (DSP) blocks for advanced applications.

Working of FPGA:

1. A digital logic design is written using a Hardware Description Language (HDL) like VHDL or
Verilog.

2. The design is synthesized and mapped to the available resources of the FPGA.

3. The resulting configuration file (bitstream) is loaded into the FPGA to define its behavior.

4. Once configured, the FPGA operates as a digital circuit implementing the desired functions.

Applications of FPGA:

 Digital Signal Processing (DSP)

 Image and Video Processing

 Embedded Systems

 Communications and Networking

 Prototyping of ASIC designs

 Industrial Control Systems

 AI/ML Hardware Acceleration

Advantages of FPGA:

 Highly flexible: Can be reprogrammed to implement different logic functions.

 Parallel processing: Multiple operations can be executed simultaneously.

 High performance: Suitable for time-critical applications.

 Short development cycle: Ideal for prototyping and testing complex systems.

Limitations of FPGA:

 Typically volatile; requires reconfiguration at every startup.

  More expensive than CPLDs or fixed-function ICs for simple applications.

 Power consumption may be higher for large designs.

 Design complexity requires knowledge of HDL and development tools.

PROM (Programmable PLA (Programmable Logic PAL (Programmable Array

Feature
Read-Only Memory) Array) Logic)

Programmable Programmable OR array Programmable AND and Programmable AND array

Arrays only OR arrays only

Most flexible among the

Flexibility Least flexible Moderate flexibility
three

Suitable for moderate

Complexity of Logic Suitable for simple logic Suitable for complex logic
logic

Slower (due to Faster than PLA (fixed OR

Speed Moderate
programmable OR array) array)

Ease of Design Simple design Complex design process Easier than PLA

One-time programmable Usually OTP (some Usually OTP (some

Reprogrammability
(OTP) rewritable versions exist) rewritable versions exist)

Implementation Truth-table based (look- Sum-of-products (SOP) Sum-of-products (SOP)

Style up tables) logic logic

Higher than PROM and

Cost Lowest Lower than PLA
PAL

Used for ROM-like data Used for implementing Used in digital control and
Usage
storage or decoding custom logic circuits glue logic
Feature CPLD FPGA

Contains a small number of large logic Contains a large number of small logic
Architecture blocks (macrocells) connected via a blocks (CLBs or LEs) connected by a
global interconnect complex interconnect matrix

Limited flexibility; suitable for control- Highly flexible; suitable for complex,
Programmability
dominated designs data-intensive designs

Volatile (SRAM-based); requires

Configuration Non-volatile (typically EEPROM or
reconfiguration at every power-up
Memory Flash)
(unless using Flash-based FPGAs)

Instant-on (retains configuration after Requires boot-loading configuration on

Startup Time
power-off) power-up

Lower logic capacity (typically up to a Higher logic capacity (millions of gates

Logic Density
few thousand gates) possible)

Suitable for moderate-complexity

Design Complexity Suitable for high-complexity designs
designs

Timing and Deterministic timing; predictable Non-deterministic timing due to flexible

Performance delays routing paths

Power Higher power consumption, especially in

Lower power for simple designs
Consumption large designs

Signal processing, high-speed data

Control logic, state machines, glue
Best Suited For processing, custom CPUs, AI/ML
logic
acceleration

More advanced toolchain and simulation

Development Tools Typically simpler
capabilities

Reprogrammable (with limited Reprogrammable (frequent

Reprogramming
endurance) reconfiguration supported)