Operational Analysis and Comparative

Evaluation of Embedded Z-Source Inverters

F. Gao1, P. C. Loh1, F. Blaabjerg2 and C. J. Gajanayake1

1 2
School of Electrical and Electronic Engineering Institute of Energy Technology
Nanyang Technological University Aalborg University
Nanyang Avenue, Singapore 639798 DK-9220 Aalborg East, Denmark
Email: gaof0001@ntu.edu.sg Email: fbl@iet.aau.dk

Abstract− This paper presents various embedded Z-source advantages in realizing voltage buck-boost operations.
(EZ-source) inverters broadly classified as shunt or parallel To date, the Z-source inverters have been well
embedded Z-source inverter. Being different from the designed in voltage-type and current-type topologies with
traditional Z-source inverter, EZ-source inverters are the development of their system modeling, optimal
constructed by inserting dc sources into the X-shaped
modulation schemes and controller design [2], [11]-[13].
impedance network so that the dc input current flows
smoothly during the whole switching period unlike the For multilevel extension, the Z-source concept has been
traditional Z-source inverter. This feature is interesting designed with various multilevel topologies particularly
when PV panels or fuel cells are assumed to power load including the Z-source neutral-point-clamped (NPC)
since the continuous input current flow reduces control inverter, the Z-source DC-link-cascaded (DCLC) inverter
complexity of dc source and system design burden. and the Z-source dual inverter [6]-[10] in order to fulfill
Carefully analyzing the operational principles for the medium and even low voltage applications. A
shoot-through and nonshoot-through switching, it is first common feature in the current Z-source inverters is the
revealed that the shunt-embedded Z-source inverters with chopping operation of dc source when switching states
capacitors partially or fully replaced by dc sources can
alternate. The jumping current flow increases the current
appropriately perform buck-boost operation with rear-end
current source inverter (CSI) circuitry connected instead of rating and the complexity of controlling maximum power
the generic voltage source inverter (VSI) circuitry. Further of clean energy sources. With these problems in view, a
proceeding on to the topological variation, parallel
embedded Z-source inverters are presented with the
detailed analysis of topological configuration and
operational principles showing that they are the superior
options among Z-source variants for clean energy
harnessing without any loss of voltage buck-boost capability
and with the inserted filtering capability for dc source. All
theoretical findings are finally verified by PLECS
simulations and constructed laboratory prototypes.

I. INTRODUCTION Fig. 1. The traditional Z-source inverter.

Among power conversion techniques, power inverters
including both simple two-level and comparatively
complex multilevel topologies have so far been broadly
applied for dc-ac power inversions such as ac motor
drive, renewable energy interfacing and uninterruptable
power supply. In particular, the inverters may need to
provide voltage boosting capability in clean energy (e.g.
fuel cell and solar energy) applications due to the
fluctuating output voltage from the power sources, which
are unavoidably affected by their output current and the (a)
ambient condition. Traditionally, a front-end dc-dc boost
converter is inserted between renewable source and
inverter circuitry to stabilize the output voltage forming a
two-stage power conversion. Such two-stage solution is
definitely not optimally integrated hence the system
complexity and cost may increase since more active
components are used for processing energy. Alternatively,
a single-stage solution, referring to the Z-source inverter,
(b)
is now attracting significant research attentions [1]-[13] Fig. 2. Equivalent circuits of traditional Z-source inverter when in (a)
for its unique passive structure and special inherent nonshoot-through and (b) shoot-through states.

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 new set of Z-source topologies, named as the embedded vL = Vdc − VC ; vi = 2VC − Vdc (1)
Z-source inverters, was proposed in [14], which however During the active interval, the current relationship can
mainly focused on the discussion of buck-boost be obviously derived from the equivalent circuit as listed
impedance network with the detailed analysis of various below:
embedded alternatives left unexplored. In addition, with idc = iL + iC ; ii = iL − iC → idc = 2iL − ii (2)
the topological similarity, [5] proposed voltage-type
Z-source inverter with a partially shunt-embedded battery When operating in a null state ({0, 0, 0} or {1, 1, 1}),
implemented in a fuel cell powered hybrid electric the voltage relationship can also be written as (1) as long
vehicle. Processing the topological modification as as the diode D is conducting. However, ii is zero during
proposed in this paper by replacing the rear-end VSI the null interval causing iL1 = iC2 = iL2 = iC1 = idc/2
circuitry with CSI circuitry can avoid the operational ⇒ idc = 2iL .
constrains of limited voltage-boost range and output When operating in a shoot-through state with the
distortion in the shunt embedded Z-source (SEZ-source) dc-link being short-circuit, the diode D will be
inverters. However, it may not be the optimal option for reverse-biased as shown in Fig. 2(b) where the state
specific applications. Fully investigating the potential of equations can be rewritten as:
embedded characteristic, new variants referring to the vi = 0 ; vL = VC and iL1 = −iC1 ; iL 2 = −iC 2 ; idc = 0 (3)
parallel embedded Z-source (PEZ-source) inverters are Averaging the inductor voltage to be zero, the
proposed in the paper with thorough analysis of their capacitor voltage VC, peak dc-link voltage vˆi and peak ac
topological characteristics and operational principles
presented. Finally, the theoretical findings of embedded output voltage vˆx (x = a, b or c) can be derived as:
Z-source inverters are verified using PLECS simulation ⎧ Vdc (1 − T0 T )
and experimentally constructed laboratory prototypes ⎪VC =
⎪ 1 − 2 T0 T
with captured results for visual confirmation.
⎪⎪ Vdc
II. TRADITIONAL Z-SOURCE INVERTER ⎨vˆi = = BVdc (4)
⎪ 1 − 2 T0 T
Referring to Fig. 1, the first Z-source inverter proposed ⎪ M MVdc MBVdc
in [1] employs a symmetrical LC impedance network to ⎪vˆx = vˆi = =
⎪⎩ 2 2(1 − 2 T0 T ) 2
replace the dc-link capacitor in traditional VSI.
Furthermore, with the help of series diode D embedded Where, M refers to the conventional modulation index,
in the source side, the input dc source can be effectively B represents the boost factor induced by shoot-through
disconnected from the Z-source network by naturally operation and T0/T < 0.5 defines the shoot-through duty
reverse-biasing the diode D during the unique ratio. It is preferred to set B be unity for voltage-buck
shoot-through interval, which can be initiated by (e.g.) operation to reduce the unnecessary voltage stress across
turning ON all switches of one phase-leg simultaneously. semiconductors and the switching loss of diode D and B
Such special operation provides the ability of voltage > 1 for voltage-boost operation, respectively.
boosting as well as the unidirectional power conversion For optimally controlling the Z-source inverter,
(desired in PV and fuel cell systems) [4, 5]. Alternatively, shoot-through state should be inserted in the traditional
the unidirectional diode can be substituted by a switching sequence without affecting the normalized
controlled switch, such as IGBT, with an appropriate voltage-second average and introducing any additional
switching signal added in order to provide both switching. Although the shoot-through state can be
bidirectional power flow when needed and proper theoretically inserted at any position of the null intervals,
inverter operation under light load conditions [9] the optimal option is to insert shoot-through state at the
regardless of the complex analysis for various Z-source transit of switching state as illustrated in Fig. 3, where
operation statuses [15]. the sinusoidal references of each phase are separated
Although the Z-source inverter has been well horizontally [2] so that SX turns ON earlier and SX’
documented in plenty of literatures, its operational turns OFF with delay to automatically form
principle would also be summarized in this section in shoot-through states. To realize the transit insertion, the
order to clearly show the inherent current and voltage sinusoidal references can be mathematically derived as
relationship in the Z-source network, later used for (5). The optimal modulation principle can then be
operational comparison. Briefly, the operational states of equally used for embedded Z-source inverters presented
Z-source inverter can be classified as shoot-through in later section.
states and nonshoot-through states (six active states and Shoot-through state
two null states). When in an active state, the inverter 000 100 110 111 111 110 100 000
circuitry and load can be treated as a constant current T0/3 T0/3 T0/3
source, as the equivalent circuit shown in Fig. 2(a), Ref. Va(SA)
where the diode D is naturally conducting because of the Ref. Vb(SB) Ref. Va(SA')
capacitor discharging process and the need for powering Ref. Vb(SB')
load from input source resulting in the following voltage Ref. Vc(SC)
relationships among dc source, inductors, capacitors and Ref. Vc(SC')
T
dc-link by assuming C1 = C2 and L1 = L2. Time
Fig. 3. Exampled optimal switching sequence of Z-source inverter.

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 ⎧ Vmax( SX ) = Vmax + Voff ( SVM ) + T1
⎨
⎩Vmax( SX ') = Vmax + Voff ( SVM ) + T2
⎧Vmid ( SX ) = Vmid + Voff ( SVM ) + T2
⎨ (5)
⎩Vmid ( SX ') = Vmid + Voff ( SVM ) − T2
⎧Vmin( SX ) = Vmin + Voff ( SVM ) − T2
⎨
⎩Vmin( SX ') = Vmin + Voff ( SVM ) − T1
Voff ( SVM ) = −0.5(Vmax + Vmin )
T0 T0
T1 =  T2 = ; X = A, B or C
T 3T (a)

III. SHUNT-EMBEDDED Z-SOURCE INVERTERS

It is noted that the jumping current flow of input dc
source as analyzed in (1), (2) and (3) will induce the
input power interruption during shoot-through interval.
Especially for cases, where PV panels or full cells are
used to power load, the jumping current flow will
increase the control complexity for drawing maximum
power and the system design burden. Aiming for finding
more attractive alternatives, embedded Z-source inverters
are therefore developed as following.
A. Partially Shunt-Embedded Z-Source Inverter (b)
First ignoring the front-end input source (indicated as Fig. 5. Simulated waveforms of partially SEZ-source inverter without
front-end dc source with Vdc = 50V and (a) M = 0.8*1.15, T0/T = 0 and
fuel cell) in Fig. 4(a), the topology presented in [5] (Fig. (b) M = 0.8*1.15, T0/T = 0.2.
4(a)) is simplified as a partially shunt-embedded
Z-source (PSEZ-source) VSI whose passive circuit Vdc = −vL1 ; VC1 = −vL 2 and iL1 = −idc ; iL 2 = iC1 (6)
(Z-source network and block diode D) resembles the Comparing (6) to (3), it is noted that null state
current-type Z-source inverter [12]. However, detailed operation of PSEZ-source inverter is similar to the
analysis as stated below reveals that the initially shoot-through operation of traditional Z-source inverter
simplified PSEZ-source VSI can not satisfy buck-boost by changing the shoot-through from right-hand of
operation with acceptable waveform quality and should Z-source to its left-hand. Next, when the inverter
be modified to be current source inverter. switches to the active state whose equivalent circuit is
Proceeding on to the operational analysis of Fig. 4(a), shown in Fig. 4(c), the effective dc-link voltage vi highly
it is observed when the inverter operates in a null state, depends on the operational conditions as
the inductor currents will circulate in the PSEZ-source vi = Vdc − vL 2 (7)
network by conducting the diode D, as the bold and In (7), vL2 can be calculated by averaging the inductor
dashed arrows indicated in Fig. 4(b). Hence,
τ null
voltage to be zero, hence, vL 2 = VC1 and VC1 = Vdc
τ active
by virtually assuming the diode D OFF during the whole
active interval. However, the substitution of dc source Vdc
changes the previous balanced capacitor charging and
+
−

discharging process in the impedance network resulting

in the residual inductor currents flowing through diode D
during active interval, which forces the dc-link voltage vi
τ null
(a) to be Vdc + VC1 = 2Vdc and vL 2 > VC1 . The
Partially SEZ-Source τ active
undesired conduction of D during active intervals
iL1
alternates the effective dc-link voltage vi between 2Vdc
+

Vdc
and Vdc – vL2, which unavoidably distorts the output
−

volt-sec average as illustrated in Fig. 5(a) for clearly

iL2 understanding the invalid voltage-buck operation of
PSEZ-source VSI. On the other hand, when in a
shoot-through state, the induced equivalent circuit is
(b) (c) similar to Fig. 2(b) except of the replacement of capacitor
Fig. 4 (a) Partially shunt-embedded Z-source inverter with front-end
fuel cell source and its equivalent circuit when operating in (b) null
C2 with dc source. Because the dc source continuously
states and (c) active states by ignoring the fuel cell. output power to charge L2, the unsymmetrical structure

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 leads to the overcharge of L2 and undercharge of L1 to make the inverter perform like a traditional CSI.
whose performance is similar as a traditional current Particularly for Fig. 6(a), only Vdc and inductor L2
source inverter operating during null intervals (eventually, actually contribute to the inverter boost operation, whose
iL1 ≈ 0A and VC1 ≈ Vdc). But with a rear-end VSI bridge voltage boost ratio equals to that of a traditional CSI.
connected and its corresponding VSI switching signals Alternatively, when needs voltage-buck operation, an
assumed, the shoot-through operation will again cause open-circuit state should be commanded in the switching
incorrect outputs specifically illustrated as the distorted sequence referring to SX and SX’ (X = A, B or C)
current waveforms shown in Fig. 5(b). switching OFF simultaneously, meanwhile SW turns ON
Adding a front-end dc source V’dc (< Vdc) in Fig. 4(a) to set the effective dc-link voltage be (7). The resulted
as proposed in [5], the output waveform quality can be equivalent circuit is similar to Fig. 4(b). The
improved but with the loss of flexible buck-boost voltage-buck (current-boost) ratio equals to the
operation. To achieve smooth sinusoidal outputs, the traditional current-type Z-source inverter presented in
inverter should be tuned to maintain VC1 = Vdc [12].
V − Vdc' To build a symmetrical X-shaped structure, another dc
mathematically being equivalent to T0 T = dc , source with the same output voltage can be inserted in
2Vdc − Vdc'
the shunt-leg instead of the passive capacitor C1 forming
the peak dc-link voltage is therefore firmed to a fully shunt-embedded Z-source (FSEZ-source) inverter
Vdc' as shown in Fig. 6(b). Doing so, the voltage-buck and
be vi = = 2Vdc − Vdc' . Obviously, the maximum
1 − 2 T0 T -boost capability is still the same as the current-type
dc-link voltage is preset according to the embedded dc PSEZ-source inverter but the current rating of L1 and L2
source voltage Vdc. Since such configuration is not a are significantly reduced because of the equal share of
purely embedded topology, its further exploration will the dc-link current between L1 and L2. A notable problem
not be discussed in the paper. in building current-type FSEZ-source inverter is the
strictly equal input voltage between two dc sources since
B. Current-Type Shunt-Embedded Z-Source Inverter unequal voltage would cause a huge circulating current
Because the configuration with shunt-embedded dc between inductors and sources and a reduced output
source cannot be operated independently, therefore, to amplitude.
fulfill the correct implementation of shunt-embedded A possible solution is to insert another small rated
Z-source concept, the current-type shunt-embedded capacitor in series with one of dc sources to share the
Z-source inverters are then proposed in this subsection, voltage difference. Doing so, the behavior of modified
whose topology is shown in Fig. 6. FSEZ-source inverter, however, is similar to the
As stated above, the PSEZ-source VSI operates like a PSEZ-source inverter. In fact, summarizing above
current source inverter during the shoot-though interval, analysis, it is noted that both current-type SEZ-source
which, therefore, inspires the topological improvement inverters are not the ideal choice for substituting the
on the rear-end inverter circuitry by substituting VSI with traditional Z-source inverter even they can easily smooth
CSI bridge, meaning the change of voltage-type source current. In detail, PSEZ-source inverter leaves one
inversion to current-type inversion. A simple control inductor and one capacitor (e.g. L1 and C1 in Fig. 6(a))
strategy of the front-end switch SW in Fig. 6 for unused when boosting voltage, while FSEZ-source
removing the unwanted conduction of diode D appeared inverter employs an additional dc source without
in Fig. 4 can be implemented as when voltage-boost improving the voltage transfer gain but introducing the
operation is commanded, SW should be turned OFF so as difficulty in maintaining source voltage balance. Also,
both SEZ-source inverters need an additional active
switch SW to guarantee the correct voltage boost
operation. Hence, other variant is necessary to be
developed for substituting the traditional Z-source
+

inverter.
−

IV. PARALLEL EMBEDDED Z-SOURCE INVERTERS

Besides the shunt-embedded Z-source inverters, an
(a)
alternative topology with dc sources inserted into the
X-shaped network is the fully parallel-embedded
Z-source (FPEZ-source) inverter, as shown in Fig. 7(a),
where two isolated dc sources are embedded with each
connecting to an inductor (L1 or L2) in series. Being
+

+
−

similarly, the operational principle of PEZ-source

−

inverter can also be derived by carefully analyzing its

behavior with different switching states during a whole
switching cycle. Consequently, when the inverter is
(b) initially commanded into a nonshoot-through state, the
Fig. 6. Current-type (a) partially and (b) fully shunt-embedded Z-source accurately equivalent circuit with diode D conducting
inverter.

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 can then be represented by that illustrated in Fig. 7(b) Fully PEZ-Source
Vdc/2 vL1
with the mathematical equations as expressed below: iL1 ii
− +
L1
vL = Vdc 2 − VC ; vi = Vdc 2 + VC − vL = Vdc − 2vL = 2VC (7) id iC1
C1 C2
iC2
SA SB SC
Next, when the inverter is commanded into a Va ioa
D VC1 VC2 vi Vb iob
shoot-through state, diode D will be naturally Vc ioc
reverse-biased due to the short-circuit connection of vd
Vdc/2 vL2
dc-rails, as shown in Fig. 7(c). Hence, + −
SA’ SB’ SC’
iL2 L2
vL = Vdc 2 + VC ; vi = 0 (8)
(a)
Averaging the inductor voltage to be zero again in a
Fully PEZ-Source
switching period, the capacitor voltage, peak dc-link Vdc/2 vL1
iL1 ii
voltage and peak ac output voltage can then be derived − +
L1
as: id iC1
C1 C2
iC2

⎧ Vdc 2 Diode D Inverter

⎪VC = Conducting
VC1 VC2 vi and Load
⎪ 1 − 2 T0 T
vd
⎪⎪ Vdc Vdc/2 vL2
⎨vˆi = = BVdc (9) + −
iL2 L2
⎪ 1 − 2 T0 T
⎪ M MVdc MBVdc
(b)
⎪vˆx = vˆi = = Fully PEZ-Source
⎪⎩ 2 2(1 − 2 T0 T ) 2 iL1
Vdc/2 vL1
ii
− +
L1
Some noted features in (9) are the same voltage boost iC1 iC2
C1 C2
capability as the traditional Z-source inverter illustrated
Diode D Shoot
in (4) and the difference between derived capacitor Blocking vd
VC1 VC2 vi Through
voltages in (4) and (9). The comparatively low capacitor
voltage in (9) (since T0/T < 0.5) helps to reduce the Vdc/2 vL2
voltage rating of capacitors in the FPEZ-source inverter + − i L2
L2

because the direct involvement of dc-source shares (c)

dc-link voltage with capacitor and inductor together Fig. 7. (a) Fully parallel-embedded Z-source inverter and its equivalent
circuits for (b) nonshoot-through and (c) shoot-through states.
unlike the traditional Z-source inverter. Also noted is the
conduction of diode D during nonshoot-through intervals
obviously ties the dc-link voltage to be two times
capacitor voltage. Once current id drops to zero, the
inverter will go into some unwanted operational states,
which can be overcame by substituting diode D with a
controlled active switch referring to the same solution
presented in [9] for the light load operation of Z-source
inverter. Comparing FPEZ-source inverter with
FSEZ-source inverter, a significant advantage in
FPEZ-source inverter is that the insertion of second dc Fig. 8. Partially PEZ-source inverter.
source can increase ac output voltage proportionally
without the strict requirement of maintaining source
voltage equal.
In addition to the FPEZ-source inverter with two
isolated dc sources, a reasonable alternative is the
unsymmetrical configuration with single dc source
connected to any inductor in series denominated as the
partially PEZ-source (PPEZ-source) inverter as shown in
Fig. 8.
Again, the unsymmetrical structure leads to unequal
(a)
voltage distribution between capacitor C1 and C2, whose
voltage value can be recalculated by considering the
behavior of equivalent circuits in Fig. 9 for
nonshoot-through and shoot-through states, respectively.
In detail, voltage relationship in nonshoot-through and
shoot-through states can be re-expressed as:
⎧vL1 = Vdc − VC 2
⎪
Nonshoot-through: ⎨vL 2 = −VC1 (10)
⎪v = V + V (b)
⎩ i C1 C2 Fig. 9. Equivalent circuits of partially PEZ-source inverter when in (a)
nonshoot-through and (b) shoot-through states.

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 ⎧vL1 = Vdc + VC1
⎪
Shoot-through: ⎨vL 2 = VC 2 (11)
⎪v = 0
⎩ i
Therefore, the capacitor voltage, peak dc-link voltage
and peak ac output voltage can then be derived according
to (10) and (11) as:
⎧ T0 T
⎪VC1 = Vdc 1 − 2 T T
⎪ 0

⎪ 1 − T0 T
⎪VC 2 = Vdc
⎪ 1 − 2 T0 T
⎨ (12)
⎪vˆ = Vdc
= BVdc
⎪ i 1 − 2 T0 T
⎪ Fig. 10. Simulated waveforms of fully SEZ-source inverter with
⎪vˆ = M vˆ = MVdc
=
MBVdc
M=0.6×1.15 and T0/T=0.
⎪ x i
−
⎩ 2 2(1 2 T0 T ) 2
Comparing (12) to (9), it is observed that the same ac
output voltage can be realized with the same modulation
parameters (M and T0/T) assumed when the total input
source voltage is tuned to be equal between Fig. 7(a) and
Fig. 8 but with the unequal capacitors’ voltage
demonstrated in (12). In addition, both PEZ-source
inverters can be equally controlled using the optimal
modulation scheme stated in §II.
V. COMPARATIVE EVALUATION OF PEZ-SOURCE
INVERTERS
Although the current-type SEZ-source inverters can
perform voltage buck-boost operation without output
waveform distortion, they are not the ideal alternatives Fig. 11. Simulated waveforms of fully PEZ-source inverter with
for substituting the traditional Z-source inverter in terms M=0.7×1.15 and T0/T=0.3.
of the optimization of components and the difficulty of
avoiding circulating current.
Instead, PEZ-source inverters demonstrate the same
voltage boost capability and assume the same component
count as the traditional Z-source inverter but with a
significant advantage of smooth source current. For the
separate dc sources needed in FPEZ-source inverter, they
can be easily acquired in PV applications by just
grouping the PV arrays equally. Moreover, the voltage
rating of shunt capacitors is significantly reduced when
the designed maximum boost-voltage deviates from
infinite as comparing between (4) and (9). Even for
applications where only single dc source is available, the
PPEZ-source inverter still shows its comparative
advantages over the traditional Z-source inverter like
Fig. 12. Simulated waveforms of partially PEZ-source inverter with
TABLE I. COMPARATIVE SUMMARY BETWEEN TRADITIONAL AND
M=0.7×1.15 and T0/T=0.3.
PARALLEL EMBEDDED Z-SOURCE INVERTER.
Traditional
FPEZ-Source PPEZ-Source
Z-Source
Inverter Inverter
Inverter
Source
2iL - ii, 2iL, 0 iL iL
Current
VdcT0 T
Capacitor Vdc (1 − T0 T ) Vdc 2 1 − 2 T0 T
Voltage 1 − 2 T0 T 1 − 2 T0 T Vdc (1 − T0 T )
1 − 2 T0 T
Voltage
Boost Same (see last equation in (4), (9) and (12))
Fig. 13. Experimental waveforms of FPEZ-source inverter with
Capability
M=0.7×1.15 and T0/T=0.3.

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 This paper presents various embedded Z-source
inverters with single or two isolated input dc sources
inserted in the unique X-shaped network. Detailed
analysis reveals that the proper shunt-embedded Z-source
inverters with no optimal use of components perform like
a traditional CSI when boosting voltage. Proceeding to
the circuit duality, the parallel-embedded Z-source
inverters are developed with voltage-type operation.
Operational analysis and mathematical calculations prove
that the PEZ-source inverter can achieve the same
Fig. 14. Experimental waveforms of FPEZ-source inverter with voltage boost capability as the traditional Z-source
M=0.7×1.15 and T0/T=0.
inverter with significantly reduced capacitor rating and
smooth source current and reduced capacitor rating. The current rating of dc source. The filter function of series
tabular summarization of comparative evaluation inductors in the PEZ-source inverters smoothes source
between PEZ-source inverters and the traditional current and ensures the continuously unidirectional
Z-source inverter is presented in Table I. operation, which makes the PEZ-source inverters more
suitable than the traditional Z-source inverter in PV and
VI. SIMULATION AND EXPERIMENTAL VERIFICATIONS fuel cell applications.
To verify the proposed topologies, PLECS simulations
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would not be presented in the paper since SEZ-source [5] F. Z. Peng, M. Shen, and K. Holland, "Application of Z-source
inverters are not the optimal alternatives of traditional inverter for traction drive of fuel cell—battery hybrid electric
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[6] P. C. Loh, S. W. Lim, F. Gao, and F. Blaabjerg, "Three-level
components were selected as L1 = L2 = 2mH and C1 = C2 Z-source inverters using a single LC impedance network," IEEE
= 2200μF for constructing the topologies in Fig. 7(a) and Trans. Power Electron., vol. 22, no. 2, pp. 706-711, Mar. 2007.
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fully and partially PEZ-source inverters with M = of pulsewidth modulation strategies for Z-source
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0.7×1.15 and T0/T = 0.3, respectively. It is noted that the vol. 22, no. 3, pp. 1005-1013, May 2007.
fully and partially PEZ-source inverters demonstrate the [8] P. C. Loh, F. Gao, F. Blaabjerg, S. Y. Feng, and K. N. Soon,
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amplitude of line voltage of BVdc = 150V and line IEEE Trans. Ind. Appl., vol. 43, no. 5, pp. 1295-1308, Sep./Oct.
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currents. However, in Fig. 12, the capacitor voltages are [9] F. Gao, P. C. Loh, F. Blaabjerg, and D. M. Vilathgamuwa, "Dual
unequal in accordance with the operational analysis of Z-source inverter with three-level reduced common-mode
PPEZ-source inverter. In both PEZ-source inverters, the switching," IEEE Trans. Ind. Appl., vol. 43, no. 6, pp. 1579-1608,
phase voltages were measured between the phase-leg Nov./Dec. 2007.
[10] P. C. Loh, F. Gao, P. C. Tan, and F. Blaabjerg, "Three-level
output and cathode of diode D. Hence, the measured AC-DC-AC Z-source converter using reduced passive component
phase voltage in Fig. 12 is unsymmetrical with its count," in Proc. IEEE-PESC’07, 2007, pp. 2691-2697.
positive and negative amplitudes being the voltage of C2 [11] P. C. Loh, D. M. Vilathgamuwa, C. J. Gajanayake, Y. R. Lim, and
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After simulation verifications, the experimental 22, no. 2, pp. 498-507, Mar. 2007.
prototypes were constructed in laboratory with the [12] P. C. Loh, D. M. Vilathgamuwa, C. J. Gajanayake, L. T. Wong,
passive components selected as those used in simulations and C. P. Ang, "Z-source current-type inverters: Digital
and the total input voltage Vdc is tuned to be 60V. Fig. 13 modulation and logic implementation," IEEE Trans. Power
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and Fig. 14 shows the captured experimental waveforms [13] C. J. Gajanayake, D. M. Vilathgamuwa, and P. C. Loh,
of FPEZ-source inverter with modulation parameters set "Modeling and design of multi-loop closed loop controller for
as M = 0.7×1.15, T0/T = 0.3 and M = 0.7×1.15, T0/T = 0, Z-source inverter for Distributed Generation," in Proc.
respectively. The experimental results well verify the IEEE-PESC’06, 2006. pp. 1-7.
[14] P. C. Loh, F. Gao, F. Blaabjerg, and A. L. Goh, "Buck-boost
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the Z-source inverter with small inductance," in Proc.
VII. CONCLUSION IEEE-IAS’05, 2005, pp. 1253-1260.

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