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Problem For Chapter 2

This document outlines 12 problems related to programming languages and VHDL concepts: 1) It asks about the syntax and semantics of programming languages and differences between HDLs and traditional languages like C. 2) It provides code examples in VHDL and C and asks to draw circuit diagrams, describe operations, and discuss differences. 3) It asks to rewrite logic expressions and revise VHDL code accordingly. 4) It asks to draw block diagrams based on given VHDL code. 5) It asks to derive structural VHDL descriptions from given circuit diagrams and code. 6) It asks to discuss differences between VHDL processes and programming language procedures and functions.

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490 views3 pages

Problem For Chapter 2

This document outlines 12 problems related to programming languages and VHDL concepts: 1) It asks about the syntax and semantics of programming languages and differences between HDLs and traditional languages like C. 2) It provides code examples in VHDL and C and asks to draw circuit diagrams, describe operations, and discuss differences. 3) It asks to rewrite logic expressions and revise VHDL code accordingly. 4) It asks to draw block diagrams based on given VHDL code. 5) It asks to derive structural VHDL descriptions from given circuit diagrams and code. 6) It asks to discuss differences between VHDL processes and programming language procedures and functions.

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© © All Rights Reserved
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Problem for chapter 2

2.1 What are the syntax and semantics of a programming language?


2.2 List three major differences between an HDL and a traditional programming
language, such as C.
2.3 In a traditional programming language, such as C, we can write the statement a=!a,
and in VHDL, we can write a concurrent statement as a <= not a after 10 ns;.
(a) Draw the circuit diagram for the VHDL statement.
(b) Describe the operation of the circuit in part (a).
(c) Discuss the differences between the VHDL and C statements.
2.4 For the even-parity detector circuit, rewrite the expression in product-of-sums
format. Revise the code of the sop_arch architecture body according to the new
expression.
2.5 For the VHDL code shown below, treat each concurrent statement as a circuit part
and draw the conceptual block diagram accordingly.
y < = el and e0 ;
e0 < = ( a0 and b0 ) or ( ( not a0 ) and ( not b0 ) ) ;
el <= ( al and bl ) or ( ( not al ) and ( not bl ) ) ;
2.6 A circuit diagram consisting of the xor2 component is shown below. Follow the
code of the str.arch architecture body to derive a structural VHDL description for this
circuit.
2.7 The VHDL structural description of a circuit is shown below. Derive the block
diagram according to the code.
library ieee;
use ieee.std_logic_1164. all ;
entity hundred_counter is
port (
elk , reset : in std. logic ;
en: in std_logic;
q_ten , q_one: out std_logic_vector(3 downto 0);
p_ten: out std. logic
);
end hundred_counter;
architecture str_arch of hundred_counter is
component dec_counter
port (
elk , reset: in std_logic ;
en: in std_logic ;
q: out std_logic_vector(3 downto 0);
pulse: out std. logic
);
end component ;
signal p_one , p_ten: std_logic ;
begin
one_digit : dec_counter
port map (clk=>clk , reset=>reset , en=>en ,
pulse=>p_one , q=>q_one);
ten_digit: dec_counter
port map (clk=>clk , reset=>reset , en=>p_one ,
pulse=>p_ten , q=>q_ten);
end str_arch ;
2.8 From the description of the VHDL process in Section 2.2.3, discuss the differences
between the VHDL process and the traditional programming languages’ procedure and
function.
2.9 We want to change the input of the even-parity detector circuit from 3 bits to4 bits,
i.e., from a(2 downto 0) to a(3 downto 0). Revise the VHDL codes of the five
architecture bodies to accommodate the change.
2.10 If we want to change the input of the even-parity detector circuit from 3 bits to 10
bits, discuss the amount of code modifications needed in each architecture body.
2.11 Explain why VHDL treats the entity declaration and architecture body as two sep-
arate design units.
2.12 Think of two applications that can use the configuration construct of the VHDL.

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