5.

3 Laboratory Steps
In Lab 4, and also in the prelab for this lab, you tested your design in the
manner that most digital design engineers test their initial designs — in
simulation. To recap, you exercised your state machine with a sequence
of values for the inputs (X[0] and X[1]) at appropriate times relative to
a clock signal, and with a reset signal that started active (bringing the
machine to a known state), and then remained inactive for the duration of
the simulation.
By testing every possible transition from each state, you were able to verify
that the state machine behaved correctly, because you also had a “solution”
vector with the correct outputs. Both the input and solution vectors were
provided to shorten the process for you, but you could have figured them
out. Here is how you would do that. Since there are three states, and
each could have any of four possible input combinations applied to them
(00, 01, 10, and 11), there are only 12 (3 times 4) vectors needed, assuming
you do not need additional vectors for the sole purpose of getting to a
particular test state. (A simulation that tests all 12 possibilities in this case
would be said to provide 100% coverage.)
Although simulation makes the design process more efficient by finding
most errors prior to implementation, it can sometimes produce the wrong
answer, particularly if the software models of the actual target hardware
are inaccurate. So testing is never complete until the real hardware — the
device under test (DUT), the circuit under test (CUT), or unit under test
(UUT) —  is exercised. That is what you will be doing in this lab.

SIM SM_VHDL
RESET_SIM RESETN RESETN
Q
CLK_IN CLOCK CLOCK
Z
Q X X

Z P/F

Figure 5.7. The ATE configuration for this lab is a VHDL device called SIM that
generates the same vectors used earlier in simulation and compares the state machines
Q and Z values against correct ones.

102 Lab 5
Hardware is generally tested either manually (verifying that output
signals change as expected) or with automatic test equipment (ATE). Such
equipment will drive all of the input pins with test signals (a “stimulus,”
like the test vectors you have used), and automatically compare the output
pins against expected values (a “response monitor”). The combination of
the stimulus generator, the UUT, and the response monitor is called a
testbench. The automatic test equipment used in this lab is another VHDL
device, predesigned and given to you, that will be programmed into the
Cyclone chip alongside your state machine, as shown in Figure 5.7. In
other words, one device in the FPGA is going to test another device in the
FPGA— your state machine.
The SIM module in Figure 5.7 drives the RESETN, CLOCK, and X inputs
to the circuit designed during the prelab, SM_VHDL.VHD. It can just
as easily be used to test the functionally identical device from Lab 4,
SM_SCHEMATIC.BDF. The outputs of the UUT are then checked by the
SIM module to determine if the state machine has been implemented
correctly. So, the SIM module is functioning as both the stimulus generator
and the response monitor. It also has some extra capability to display
debugging information on the VGA output of the DE2 board, as well as
simple pass/fail LED indicators.
Once the ATE steps of the lab are completed, you will also learn how to
manually verify the state machine operation with a logic analyzer. But
since the state machine still needs to be stimulated for the logic analyzer to
see any outputs change, we will make use of the SIM module once again.
Test engineers will generally use some sort of signal generator (or pattern
generator) for this purpose, so think of SIM as your pattern generator when
you get to that step.

1. Place all of your files into a working directory in the lab computer.
From the class web site, download the file named SM_TESTER.zip
and unpack it to the same directory (do not create a subdirectory).

2. Also from the web site, download the file VECTORS.MIF that is
unique for your section, placing it in the same directory. This
is the same information as the VECTORxxxSOLUTION.TBL
file contained last week, but in a form that can be stored in the
Cyclone chip and accessed by SIM for pattern generation.

3. Start Quartus II and load the project file SM_TESTER.QPF that

was part of the zip file. Open the SM_TESTER.BDF file included as
Lab 5 103
 Table 5.1. State Machine Signals And Header Pin Numbers

GPIO1 header EP2C35F672 EP2C70F896

Signal Color Band
pin (DE2) pin (DE2-70) pin
CLOCK JP2-4 M23 G28
RESETN JP2-5 M19 H27
X1 JP2-6 M20 L24
X0 JP2-7 N20 H28
Z JP2-8 M21 L25
Q1 JP2-9 M24 K27
Q0 JP2-10 M25 L28
GND solid black JP2-12  N/A N/A

the top-level design file in the new project. Note that it includes
a symbol for SM_VHDL. Since your SM_VHDL.VHD is the only
appropriate “SM_VHDL” source file in the directory, it will be
compiled as part of the project. Note also that SIM is reset by
KEY0, and started by KEY1. When first loaded to the board,
SIM starts in the reset state even without pushing the KEY0 reset
button.

You may have to select “View...Show Pin and Location

Assignments” to verify that the pushbuttons are
assigned to the right pins (G26 and N23 on the EP2C35
Hint!

chip.) You can also verify that the pins listed in Table
5.1 were assigned, in order to bring signals out to the
JP2 (GPIO1) header. Pin and location assignments may
not be visible in a schematic until after a compilation.

Also note that SIM drives the LEDs with its PASS and FAIL
signals. You may be able to figure out how the PASS and FAIL
signals drive different LEDs, but it will be clear soon enough,
anyway.

4. Go ahead and compile the project. You should have no errors

if you have all of the other files in the same directory, including
your SM_VHDL.VHD and VECTORS.MIF files.

5. Use the Programmer tool to program the result of the previous

step, SM_TESTER.SOF, to your DE2 board. Press the KEY0

104 Lab 5
 button to reset the circuit. At this point, both the SIM device
and your SM_VHDL device are in the Cyclone chip, and SIM is
waiting to be started. Note that none of the red or green LEDs are
illuminated (but the blue power LED should be lit).

6. Press the KEY1 button to start the process of input pattern

generation and output comparison. If the state machine has
passed, a green LED (LEDG0) will be illuminated. A failure is
indicated by a red LED (LEDR0).

7. Make modifications to your SM_VHDL.VHD file as needed, until

it passes. It should pass the first time, if this is the same design
that you verified in simulation. ()

An earlier sidebar “Note!” (in the prelab) called your

attention to the maximum allowable clock frequency
for your state machine. Now that the state machine is
included within a much larger project, it is much harder
Note!

to find that maximum value, and you may even see

critical warnings about parts of this device that you did
not design (so don’t worry about them). But the earlier
calculation still holds true, so the SIM device should
not clock your state machine any faster than the value
determined earlier. (Again, don’t worry, because it is set
up to clock at a very safe speed).

8. In the block diagram editor, open your SM_SCHEMATIC.BDF

file from Lab 4 (which should be in the same working directory).
Select File => Create/Update => Create Symbol for Current File.
This will make sure that you have a symbol for this file so that you
can use it as part of other projects.

9. Go back to SM_TESTER.BDF. Delete the symbol SM_VHDL

(which invoked your VHDL implementation of the state machine),
and replace it with the symbol SM_SCHEMATIC. (Use the
Symbol tool in the block editor, and get the symbol for
SM_SCHEMATIC that you just created in the previous step.) Note
that the input vector X can be either two signals (X[0] and X[1]) or
a single bus (X[1..0]), and this can occur at different places in the
same schematic. The same is true for the Q vector. Save a screen
grab of this file as a result.

Lab 5 105
 10. Save and compile the project (generating a new SM_TESTER.SOF
in the process).

11. Repeat steps 5-7 for this SCHEMATIC version, instead of the
VHDL version. (Download, get the pass response, and get a
checkoff.) ()

What have you just done? Does it make sense? In the past
two labs, you’ve implemented the same state machine in
Note!

the Cyclone FPGA with two different design methods,

then “dropped” both versions into the same convenient
state machine tester to make sure that they worked.

12. If you have not watched and understood the logic analyzer
tutorial video from the class web site, look at it now (more than
once, if necessary). In the lab, there are two different versions of
the logic analyzer. The newer ones have larger screens, but either

Figure 5.8a. TLA5201B logic analyzer connections. Top left: Two probe pods plugged
into a logic analyzer (the C2/C3 pod on the left and the A2/A3 pod on the right). Top
right: The individual probes break out in two groups on each pod (A2 and A3, here).
Bottom: Each group separates eventually to a ground and eight color-coded signals.
The second group and a separate clock probe are not shown.

106 Lab 5
Figure 5.8b. TLA6401 logic analyzer connections. Left: One probe pod plugged into
a logic analyzer (the A2/A3 pod). Middle: The individual probes break out in two
groups on each pod (A2 and A3, here). Bottom: Each group separates eventually to a
ground and eight color-coded signals. The second group and a separate clock probe
are not shown.
version will work fine for this lab. Turn on the logic analyzer and
prepare to attach the A2 connector’s probes as will be described
below. Use the KVM switch (Keyboard/Video/Mouse switch)
to switch the video display to show the logic analyzer while also
connecting the keyboard and mouse for ease of data entry.

13. The A2 connector head contains eight individual channels, and

is one of two such connector heads on the A2/A3 probe pod,
as shown in Figure 5.8a or 5.8b, depending on the type of logic
analyzer at your workstation. There are separate signal probes for
each individual channel.

For the TLA5201B only, there is a mating connector, which

appears in the middle of the bottom photo of Figure 5.8a.
When reconnecting one of these groups of eight channels
Note!

to the probe pod, you must carefully note which side

contains the eight grounds and which side contains the
eight signals. Look for the embossed label “GROUND”
or “0 — 7” on each side of each connector. Always check
this, especially when using a previously connected probe
head.)

(Figure 5.9 shows approximately where the signal probes will be

connected on the DE2 board. Referring to Table 5.1 for the GPIO1
(or JP2) expansion header pins, start by connecting the solid black
probe to pin JP2-12 (GND signal in Table 5.1).

Lab 5 107
 Figure 5.9. Connection of the logic analyzer to the DE2 board showing the TLA5201B
probes (left) and the TLA6401 probes (right). Specific choices (i.e., colors) are arbitrary,
but must be recorded. These specific locations are important, because SM_TESTER.
BDF directs state machine input and output signals to particular pins on expansion
header JP2.

Some people have trouble recognizing color differences.

Note that the color codes, from least significant to most
significant on each probe, follow the same convention as
resistor color codes: black(0), brown(1), red(2), orange(3),
Hint!

yellow(4), green(5), blue(6), and purple(7). The probes

are assembled in order (with the solid black ground
probe interrupting the sequence near the middle), and
the embossed “0-7” label indicates which end is most
significant. So color recognition is not necessary.

14. Connect all remaining signals in Table 5.1 using any seven of the
eight signal probes on the A2 pod, but keep track of which color
is on the probe connected to each signal. You can record these
colors in the blank column of Table 5.1 for now. This information
will be needed later. Notice that the JP2 expansion header pins
correspond to different pins on the two types of Cyclone II devices
(EP2C35 or EP2C70). In either case, however, the result is that a
particular signal will end up on the same JP2 pin, with either a
DE2 board or a DE2-70 board.

15. The logic analyzer is controlled from a software application called

the TLA Application. The application comes up by default when
108 Lab 5
Figure 5.10. The System window of the TLA application provides a graphical depiction
of the other main windows, including setup, triggering, data listings, and data
waveforms.

the analyzer is rebooted, but can be opened from the Windows

Start Menu, if needed (Start => Programs => Tektronix Logic
Analyzer => TLA Application).

For now, decline the option to use the EasySetup wizard, if it is

offered. Later, you may wish to use it for new measurements.
Instead, start with the System window (Window => System). The
System window provides a convenient means to view the overall
configuration of the system and the data which has been collected,
as shown in Figure 5.10.

If you need to leave the lab at any point during the steps
that follow, you can save your entire logic analyzer
setup to a USB stick. You will have to reconnect the
Hint!

probes when you return, of course. Ask a TA for

assistance if needed, make sure you are saving the
system setup, not just a waveform or image, and make
sure you save to your USB device, not the analyzer’s
hard disk.

16. Logic Analyzer Setup: Click on Setup, either in the graphical

view or in the menu toolbar (Window => Setup). The steps that
follow here allow the analyzer to understand the connections
you have made to your circuit. The Setup window shows the
definitions of individual signals, as well as “groups” of signals,

Lab 5 109
 Figure 5.11. The first step of the setup informs the analyzer that the circuit has a two-
bit vector, or group, named X and connected to specific probes, which will vary based
on your selection of colored probes for each signal. The top image (a) shows the setup
window of the TLA5201B, and the bottom image (b) shows the setup window of the
TLA6401.

which can represent busses or vectors of signals. Furthermore, it

shows how these signals map to the actual probes of the analyzer.

a. Remove any default groups that may appear (under Group

Name). This can be done by selecting a group, right clicking,

110 Lab 5
 and clicking on the Delete Group option.
b. Add a group for the two-bit signal X by simply typing X
under the Group Name heading in the first blank row (for the
TLA5201B) or in the first field below Groups (for the TLA6401).
c. While the X group is still active (highlighted with a box around
it), add the X[1] and X[0] signals to the X group either
• (for the TLA5201B) by clicking on the grey box under the
corresponding color band codes (from Lab step 14) in the
A2 probe’s row, or
• (for the TLA6401) by dragging the channels from the probe
area of the screen that represent the colors you chose (from
Lab step 14) to the region below the group name you just
created.

The TLA5101B will build the group in the order you pick
signals, so be sure to select the most significant bit first. In this
case, it will be the X[1] signal. This will result in something
similar to Figure 5.11, but you may have chosen different
probes (different color bands).
The TLA6401 will allow you to drag the signals between the
MSB and LSB, so that you can reorder them if necessary.

Another hint for the color-impaired is that the color band

Hint!

appears to the right of the numerical value in screens like

that of Figures 5.11 and 5.12.

d. Repeat steps b and c to add signals Q[1] and Q[0] to a Q group.

(Click on the + sign in the Groups area of the TLA6401 to create
a new group pane to work with.)
e. The Z, CLOCK, and RESETN signals are not grouped. Simply
type these names
• (for the TLA5201B) in the white box under the
corresponding color band codes in the A2 row, or
• (for the TLA6401) in place of (i.e., overtyping) the
corresponding A2 signal in the grid of probe names.

Lab 5 111
 Figure 5.12. After setting up both groups and the three individual signals, your setup
window should resemble the top figure (a) on the TLA5201B, or the bottom figure
(b) on the TLA6401. But in either case, it is likely that you made different choices of
probes.
At this point, every used probe now has a name that is relevant
to your circuit. (Specifically, seven of the eight color-coded
signals should have either a name in the A2 row, or they
should have the grey box selected. The eighth signal and the
clock will remain unused.) See Figure 5.12a or 5.12b.
f. Set the logic analyzer is to use its own internal clock:
112 Lab 5
Figure 5.13. The Probe Properties window allows the user to specify voltage threshold levels,
which should be TTL-compatible for this circuit.

• (for the TLA5201B) Under Clocking, set Internal and select

a sampling period of 10 µs. Acquire can be set to Normal,
and the memory depth can be set to 128K. See Figure 5.12a.
• (for the TLA6401) In the Asynchronous tab, drag the
Sample Period to 10 µs. Samples per Signal can be set to
128K, with Options set for “Samples.” See Figure 5.12b.

g. The logic analyzer must be set for the proper logic thresholds,
since it cannot represent 0 and 1 correctly unless you define
logic levels.
• (for the TLA5201B) Click on the Probes drop-down menu
near the top left and select the Thresholds tab. As shown
in Figure 5.13, pick a threshold of 1.5 V for the TTL-
compatible signals of the FPGA. You can set the threshold
for every probe at 1.5 V by using Set All, or just set the
thresholds for probe A2.
• (for the TLA6401) Set the Global Threshold to 1.5 V. See
Figure 5.12b.

h. Power up the DE2 board, then program your state machine

to it. The logic activity of each signal can be viewed on the
logic analyzer. They will be static, because the state machine
is not running. But you can reset the state machine (KEY0)
Lab 5 113
Figure 5.14. Once the “Select Channel” button of the Trigger window has been
activated, it is possible to select RESETN as the desired trigger signal, but it is
necessary to specify that channels should be slected “ByName” (on both types of
logica analyzers).
and press KEY1 to see a short period of activity. Often, this
feature is useful to verify that signals are connected properly:

• (for the TLA5201B) Note the Activity tab that is also a part
of the Probe Properties window. Select it, and you can see
the current logic level of each probe input. Close the Probe
Properties window before continuing.
• (for the TLA6401) The symbol that looks like a circle in
each channel grid location is actually a zero, showing a low
logic level. It will change to a 1 if that signal goes high, or
to a combined 0/1 signal when rapidly changing. (With the
state machine just downloaded, you will see only zeros.)

17. Logic Analyzer Triggering: Now open the Trigger window

(Window => Trigger: LA 1), replacing the Setup window. Here,
you will define conditions which must exist before data is
captured.

a. Click on the Easy Trigger tab, which provides commonly-used

triggers that are customizable for specific needs. Look under
Standard Programs and Simple Events on the TLA5201B, if
necessary.

114 Lab 5
 b. We would like to see what happens during and immediately
after a reset, which occurs when the RESETN signal goes
high. So pick Trigger on channel transition (edge), and note
on the lower half of the screen that you can select both a
channel and an edge direction. Channels are given by their
probe number (which you could provide, of course). But since
you have assigned meaningful names, it is easier to use the
Select Channel button to select RESETN by name, rather than
by probe number, as shown in Figure 5.14. Make sure that
you choose a trigger condition of a rising edge for RESETN
(“Channel RESETN Goes High” is the exact wording of the
desired trigger condition).
c. At this point, the analyzer is ready to enter the “Run” mode,
at which time it will continuously store data until the trigger
condition is met, then stop as soon as the required amount of
data is collected for display and analysis by you, the user.
18. Logic Analyzer Capture

a. Reset the state machine simulator by pressing KEY0.

b. Press the green RUN button at the top of the logic analyzer’s
screen to begin a data capture. The button should become a
red STOP button, which you would use only in the event that
something was wrong, and data is not acquired in the steps
that follow.
c. Now press the KEY1 button to start the state machine simulator.
d. The logic analyzer should soon show a green RUN button
at the top again, because it successfully acquired data and
is available for another acquisition. But do not run it again,
because you instead want to look at the acquired data. The
Waveform window should open automatically, but you can
always bring up one or more waveforms from the Window
menu.
e. Delete any extraneous signals from the waveform. This can be
done by selecting an uwanted signal and pressing the delete
key or by right clicking on the signal and choosing Delete
Waveform. Extra waveforms may include Sample, CK0[], and
magnified views of those same waveforms. You may have
noticed that many items, such as these waveform names, are
Lab 5 115
Figure 5.15. A successful acquisition from the logic analyzer, with all appropriate
waveforms shown.

prefixed with LA 1. This simply reflects the possibility that

multiple logic analyzers could be controlled from a single
application.
f. Add all of the signals to the waveform window that were
displayed in the simulation waveform from the pre-lab steps.
To add a signal, right click on the blank portion of the waveform
window and select Add Waveform. By default, the waveform
selections are probably shown By Group. However, to add a
single ungrouped signal, change the select option to By Name.
Note that you can easily get the same order of signals that you
had in the Quartus simulator, either by adding them in order,
or by dragging them to the correct positions. You can choose
the radix for each group of signals, which should default to
the desired radix of “Binary” (so that the state, for example,
will show as 00, 01, 10).
g. Once all of the signals have been added and properly arranged,
the waveform should look very similar to the one generated
in the pre-lab (and last week), except that this will show
propagation delays. Note that you may have to zoom out
before seeing anything useful. If you zoom out so far that all
acquired data is visible, the entire state machine sequence is
so small that it is barely noticeable. Zoom in, staying centered
at the trigger event, and you should be able to get a display
similar to Figure 5.15.

116 Lab 5
 The reason that our data occupies such a small region

Question...
or the timescale (i.e., the reason that we had to zoom in)
goes back to the step where we chose 128K samples, at a
10 µsec sampling rate. Is there something we could have
done differently, knowing what we do about how fast the
state machine is clocked and how many clock cycles are
needed for all of the test vectors to run?

h. Take a screen capture of the waveform by using one of the two

following methods:
• On either type of logic analyzer, press Alt-Print Screen
on the keyboard to grab the screen. Then open Windows
Paint, select File => New, paste the clipboard into the newly
created file, and save it to a to a USB memory stick (the USB
ports are on the left side of the TLA5201B, near the back, and
on the front of the TLA6401)
• On the TLA5201B, you can alternatively use the “Snag It”
application. Select File => Print, make sure that “Snag It” is
the current printer, follow the instructions, and a Snag It
window will appear with the screen capture. When you
choose File => Finish Output, it gives you the same choice
as if you had chosen File => Save As. Save to a to a USB
memory stick (the USB ports are on the left side of the
TLA5201B, near the back).

In either case, do not save to the analyzer’s hard disk. Instead

save the screen capture to a USB memory stick as described
above and immediately transfer it to the PC. Be sure to verify
that the image is still intact once you have transferred it to the
PC! ()
i. The logic analyzer knows nothing about your state names A,
B, and C, but you can tell it how to interpret the Q bits. This
is accomplished by loading an appropriate symbol definition
file. While you still have your USB stick in the PC, download
the file STATELABELDEFS.TSF from the class web site (saving
to the USB stick), then place the USB stick back into the logic
analyzer. Right-click on the Q label, select Radix => Symbolic

Lab 5 117
 Figure 5.16. After changing the state (Q) radix from binary to symbolic, as defined
by symbols in STATELABELDEFS.TSF, the waveform should be very similar to a
simulated waveform with the A, B, C state names.

=> Other and pick the file STATELABELDEFS.TSF from your

USB stick. The resulting waveform should resemble Figure
5.16. Take another screen capture, as you did in step h. ()
j. Once the screen capture has been saved and verified, shut down
the logic analyzer and disconnect the A2 probe connections.
Be sure to switch the KVM back to showing the PC.
19. Finally, to get one last experience with your protoboard, connect
the CADET power and ground to your discrete logic circuit.
Connect debounced switch PB1 (with a pullup resistor) to the
clock signal of your state machine. Connect debounced switch
PB2 (with a pullup resistor) to the reset signal of your state
machine. Connect two slide switches to your X1 and X0 signals.
Connect your Q1 and Q0 signals to LEDs, and note which one of
them corresponds to “Z.”

20. Press the reset button and make sure that the state machine goes
to state A (00). Try all four switch combinations for the X inputs,
one at a time (resetting the state machine between each test).
When you press the clock pushbutton, you should see the correct
state transition on the LEDs. Show this for a checkoff. ()

21. You do not have to test the remaining state transitions (the ones
from state B and the ones from state C), as long as you at least
verify that all of the transitions from state A work correctly.
(Realize, of course, that had this been a real job, you should find a
way to test them all!)
118 Lab 5
 22. Retain as results the following items:
• the SM_VHDL.VHD file (from prelab step 6, fixed if necessary
in lab step 7, and formatted as required)
• the SM_VHDL.VWF file (from prelab step 16, reopened and
saved as a screen grab, properly formatted)
• schematic after replacement of SM_VHDL with
SM_SCHEMATIC, adding title block and properly formatted
(from lab step 9)
• TWO logic analyzer screen grabs (from lab step 18h and 18i)

Lab 5 119