ECSE 325 – Digital Systems
Winter 2024
Lab 1: Using Quartus and Basics of Mapping VHDL to FPGA Hardware
Overview
The goal of this lab exercise is to become familiar with the Quartus tool, especially dealing with
how compiler maps the design onto the FPGA hardware. This introductory exercise contains a
step-by-step tutorial on getting started.
After completing this exercise, you should know how to:
Start the Altera Quartus II software
Create the framework for a new project
Write a VHDL description of a logic circuit
Understand logic utilization within the FPGA board
Understand the floorplan and RTL viewer of a circuit
Lab Exercise Details
OPTIONAL: If you wish, you can also download the Quartus and ModelSim/Questa software
from the Intel website and run them on your home computer (Windows and Linux only, there is
no Mac version, nor is there any version that can run on mobile devices).
If you want to use the version that is closest to that in the Trottier labs, choose Quartus Prime
version 17.1 (Lite):
https://www.intel.com/content/www/us/en/software-kit/669444/intel-quartus-prime-lite-
edition-design-software-version-17-1-for-windows.html
You can also choose the most recent version (v22.1.2) if you wish, the labs will work just the
same, although some of the screenshots may look different.
https://www.intel.com/content/www/us/en/software-kit/785086/intel-quartus-prime-lite-
edition-design-software-version-22-1-2-for-windows.html
You only need to install device support for the Cyclone V device.
Tool Startup and Project Creation
You can start the Quartus tool by selecting the icon on the Windows start menu:
You should be using version 16.1 as it supports the DE1-SoC lab kits the best.
On startup, you should see the following window (it might slightly differ in your case) for an
empty project.
Project Creation
You have to first create a project by selecting File->New Project Wizard.
You should then go through a series of windows to create the project, starting with the following
In the second window you should give the project the name: gNN lab1 where NN is replaced with
your 2-digit group number. The working directory for your project will be different than that
shown here since you should use your network drive for all project files.
Since you do not have a project template, you can proceed with the Empty Project selection
You will add files later, so you should just select “Next>”
You should select the Cyclone V device 5CSEMA5F31C6. This is the type of FPGA that is on the
Terasic DE1-SoC board.
You should also include Modelsim-Altera as a third-party tool used in the project
On the last page, you should check whether the project was created properly
You are now ready to create a new VHDL file
The VHDL Editor window should open next, where you can type in your code.
Design of a Synchronous Dual Rate Counter in VHDL
You need to create a synchronous 16-bit up-counter with the following characteristics:
• Asynchronous reset
• Maximum count value is set by the input “max_count”
• When the count value is at the maximum, the count should go to 0 on the next
rising clock
• Counting-by-twos mode (default is to count up by 1 on each rising clock)
• Count Enable
The library and entity declarations are:
-- put the designers’ names here (commented out)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gNN_lab1 is
Port ( clk : in std_logic;
countbytwo : in std_logic;
rst : in std_logic;
enable : in std_logic;
max_count : in std_logic_vector(15 downto 0));
output : out std_logic_vector(15 downto 0));
end gNN_lab1;
where “NN” is replaced by your group number.
You will then add the Architecture section with your own code, describing the functionality of
your counter. Use a process block and arithmetic operations to describe the circuit. Remember
to transform between std_logic_vector and integer signal types as needed.
Once you have completed your sequential circuit, you can compile your design with Processing-
>Start Compilation selection. Once your code is free of errors and compiles well, all the tasks
should be available (turn green on the display)
Chip Planner
By selecting Tools-> Chip Planner, you can observe the FPGA utilization and the layout of your
circuit.
RTL Viewer
A very useful and powerful tool is available at Tools->Netlist Viewers->RTL Viewer that will show
you the logic schematic of your circuit. The figure below is included for illustration purposes, as
you should analyze your schematic and identify the parts corresponding to your code.
Lab Report
No lab report is required for this lab experience, as this is merely an exercise to get you used to
the design tools.
