Digital Electronics - FPGA
Practice 1 :
Getting started with QUARTUS II
and DE2-70 development board
OBJECTIVES:
Learn how to
- design and compile a digital circuit using Qartus II software
- simulate a digital circuit using the embedded simulation software of Quartus II
- simulate a digital circuit using ModelSim-Altera software
- program a FPGA using Quartus II software
EQUIPMENT:
- Quartus II 9.1 Web Edition, (free licence)
- ModelSim-Altera Edition v6.5e for Quartus II v9.1 (free licence)
- Terasic (www.terasic.com) DE2-70 Development Board based on Cyclone II Altera
FPGA (DE2_70_user_manual)
PREPARATORY WORK:
1- AND Gate
- Assuming ideal gate and connections, draw the values of X in the following
chronogram.
- Assuming a 10ns pin to pin propagation delay (A to X and B to X), draw the values
of X in the following chronogram.
2- 7 segments display decoder
According to the information given below in §B, determine the equation of seg4, seg5
and seg6.
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A- Getting started: implementing an AND gate
QUARTUS, as all CAD software, works with project management. Each application
developed under QUARTUS is a project. All files associated with each project will be
located in a specific folder.
Create a working folder where will be stored all your projects: working_folder
Under this folder, create the folder dedicated to your first project: Exemple0
In this introduction, we will develop and test a very basic application in combinatorial
logic: a AND gate.
1. Start the QUARTUS II software
2. Create a new project : File New Project Wizard
After reading the introduction page, open the following one (next)
Page 1/5
Choose the project folder
Choose the name of the project
(same name than the folder is recommended)
Keep the name of the top level entity associated with the project
(by default the name of the project)
Page 2/5
This page allows to add to the project existing files. We will use this functionality later.
Page 3/5
QUARTUS allows programming all the
components from ALTERA.
Select the Cyclone II family
and the reference EP2C70F896C6
Page 4/5
Here are defined the EDA (Electronic Design
Automation) tools associated with QARTUS. We will
use the Simulation Software ModelSim-Altera with
VHDL format.
Page 5/5
This page shows all the setting that we have
chosen for our project
Leave the New Project wizard by selecting "Finish"
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3. Create a Block Diagram File
QUARTUS allows building digital circuits using schematic (block diagram) or VHDL
description. For this project, we will use schematic.
File New
In the "New windows" open "Design File" and select (double click) "Block
Diagram/Schematic File"
A drawing window is available.
Save this file as "Exemple0": File Save As. The schematic file Exemple0.bdf is
created
4. Select the components and draw the digital circuit
To access to the component libraries:
- Double click in the drawing window.
The "Symbol" window appears.
- Select the needed component in the left
part of window: AND2 is in the sub-
library "primitives/logic"
- Click OK: the component is now
available in the drawing window.
Proceed in the same way for the inputs
(sub-library "primitives/pin") and the output.
A double click on input or output ports allows renaming the ports.
5. Save the file
6. Check the project
Processing Start Compilation
The compiler verifies and analyses the
schematic file.
Compiler Database files (.cdb) and report
files are generated.
Some warnings indicate that the pin
assignment is not yet performed (the
compiler has chosen a default assignment),
that our project doesn't use any clock, or
that some files needed by specific simulators
are not available.
Observe the compilation report.
7. Assign the I/O
QUARTUS is able to assign automatically the I/O to the FPGA pins. But, for application
running with the DE2 development board, the connections between components are
already made. The assignment tables are given in the DE2 User Manual. (See annexe 1
for the I/O assignments used in this workshop).
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To test our project, we will connect inputs A and B to switches SW[0] an SW[1], which
are connected to FPGA pins AA23 and AB26, respectively. The output X will be
connected to the red LED LEDR[0], which is connected to the FPGA pin AJ6.
Assignments Pin Planner: the "Pin Planner" window is available.
Enter the reference numbers of the pins associated to the I/O in the "location" column.
Close the "Pin Planner" window. The assignments are now shown on the schematic file:
8. Compile the project
Processing Start Compilation
Some warnings indicate that our project doesn't use any clock, or that some files needed
by specific simulators are not available.
This step generates the file .sof (SRAM Object File) that will be used for programming the
FPGA. It generates also, in the folder Exemple0/simulation/modelsim, the files .vho
(VHDL Output File) and .sdo (Standard Delay Format Output File) that will be used by
ModelSim for timing simulations
9. Simulate the project using the QUARTUS II ‘s embedded simulator
The Waveform Editor allows applying signals to the inputs.
- Creating the simulation file
File New : select "Vector Waveform File" in "Verification/Debugging Files"
The Waveform window is available.
Save this file as "Exemple0".The schematic file Exemple0.vwf is created
- Defining the time scale
Edit End Time… allows choosing the time of simulation (for example 200 ns)
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Right click in the window Zoom Fit in Window allows to display the whole simulation
interval time.
- Selecting the signals
Edit Insert Insert Node or Bus
In the "Insert Node or Bus" window select "Node Finder"
In the "Node Finder" window, select the filter "Pin:all", then click "List" and select the
suitable signals (here all the signals).
Click "OK" in the "Node Finder" window and in the "Insert Node or Bus" window.
- Setting the stimuli
Edit Grid size… allows adjusting the grid of the wave window.
Tools options for waveform editor allows selecting grid snapping or not.
Using the setting tools, define the values of the inputs during simulation time (see
preparatory work
- Save the waveform file
- Functional Simulation
Processing Simulator Tool
Select "Functional" Mode
Check that the waveform file is the right one
Adjust the end of simulation time
Select the overwrite option to see the result of
simulation in the waveform window.
Click "Generate Functionnal Simulation
Netlist"
Click "Start"
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Go back to the waveform window, (accept the modification of this window). The
waveform window is updated with the simulation results:
- Timing Simulation
Open the Simulator Tool windows, select "Timing" as Simulation mode and click "Start".
The simulation results take into account the propagation time in the FPGA:
Add cursors (“time bars”) and “zoom in” to precisely adjust it on the rising and falling
edges of X. Measure the propagation delays.
Compare with the values available in the compilation report (tpd)
The embedded simulator will not be longer supported by the next versions of QUARTUS.
So it is useful to become familiar with a most powerful simulator software.
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10.Simulate the project using ModelSim-Altera
10.1 Generate (if necessary) the VHDL design entry.
ModelSim needs a VHDL description (.vhd) of the design file. If it is not the case (as in
this project where we have chosen a Block Diagram entry (.bdf)), a translation of the
current entry in VHDL file has to be done:
File -> Create/Update -> Create HDL File from Current File: VHDL
10.2 Start ModelSim
10.3 Edit the stimuli file
The file Exemple.do describes the actions performed by the simulator. See ModelSim
Reference Manual for commands and syntax.
File -> New -> Source -> Do
Save the file as Exemple0.do
The file has to be saved in the directory Exemple0 for Functional Simulation and in the
directory Exemple0/simulation/modelsim for Timing Simulation
10.4 Functional Simulation
Functional simulation doesn’t take into account the
propagation delays into the FPGA.
- Select the project directory: File -> Change
Directory : C:/…/Exemple0
- Create the working library: File -> New -> Library
Select “a new library and a logical mapping to it”
Type “work” in the Library Name fields (if it isn’t
already entered automatically)
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- Compile the design unit
Compile -> Compile
Select the library work and the file Exemple0.vhd
from the folder Exeemple0.
Click Compile, then Done
ModelSim generates an Entity Exemple0 into the
library work
- Start the functional simulation
Simulate -> Start Simulation
In the Design tab of the Start Simulation window,
select Exemple0 in the library work
Click OK
An empty wave window appears:
- Run the functional simulation
In the Transcript windows (prompt VSIM >) type do Exemple0.do.
ModelSim will run the simulation script defined in 9.2.
Right click in the wave window, select Zoom Full to adjust the scale to the simulation time.
- Exit the simulation : VSIM >quit –sim
10.5 Timing Simulation
Timing simulation takes into account the propagation delays into the FPGA.
- Select the project directory:
File -> Change Directory:
C:/…/Exemple0/ simulation/modelsim
- Create the working library: File -> New -> Library
Select “a new library and a logical mapping to it”
Type “work” in the Library Name fields
- Compile the design unit
Compile -> Compile
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Select the library work and the file Exemple0.vho from the folder
Exemple0/simulation/modelsim.
Click Compile, then Done
ModelSim generates an Entity Exemple0 into the library
work
- Start the Timing Simulation
Simulate -> Start Simulation
Select the SDF (Standard Delay File)
tab.
Click Add.
In the Add SDF Entry dialog box, click
Browse.
In the Select SDF File dialog box,
Select, in the directory modelsim, the
Standard Delay Format Output File
(.sdo) Click Open.
Click OK.
In the Design tab of the Start Simulation window,
select Exemple0 in the library work
Click OK
An empty wave window appears.
- Run the timing simulation
In the Transcript windows (prompt VSIM >) type do Exemple0.do
(This file has to be saved in the current directory Exemple0/simulation/modelsim)
ModelSim will run the simulation script defined in 9.2.
Right click in the wave window, select Zoom Range … Start 0ns, End 200ns.
Add cursors to measure the propagation times from inputs a and b to output x
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Compare the propagation times to the values available in the Quartus II Compilation report:
- Exit the simulation : VSIM >quit –sim
11. Program the DE2-70 board
Connect the 12V power supply adaptor.
Connect the USB Blaster cable.
Power On the board.
To download the application from the PC directly into the FPGA, put the RUN/PROG
switch into the RUN position
Tools Programmer
Click on "Hardware Setup" and select USB-Blaster in the Hardware Setup window
Select the Program/configure option
Click on "Start"
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It is now possible to test the circuit, using the switches SW[0] and SW[1] and watching
on the red LED LEDR[0].
B- 7 segments display decoder
The DE2-70 Board has eight 7-segment displays. These displays are arranged into two
pairs and a group of four, with the intent of displaying numbers of various sizes. The
seven segments are connected to pins on the Cyclone II FPGA. Applying a low logic
level to a segment causes it to light up, and applying a high logic level turns it off.
Each segment in a display is identified by an index from 0 to 6, with the positions given
in the following figure.
In this section, we will implement a 7 segments decoder in the FPGA. The 7 outputs of
the decoder will be connected to the left-side 7 segments display of the DE2-70 board,
the 4 inputs will be connected to switches SW0, SW1, SW2 and SW3.
The decoder’s true table is given below.
The corresponding equations are:
- Create a folder dec7seg in
the working_folder, copy in this
folder the file dec7seg.bdf.
- Create the project
dec7seg1, including the file
dec7seg1.bdf in the project.
- Open the file dec7seg.bdf: it
is a Block Diagram File
corresponding partially to the
equations of the decoder.
Inputs and outputs are describes
as busses.
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Busses are drawn using the Orthogonal Bus Tool.
N[3..0] names a 4 wires bus. N3, N2, N1 and N0 are
the names of these wires.
To give a name to a bus or a wire, right click on the
item and choose “properties” in the menu.
- Complete the Block Diagram according to equations seg4, seg5 and seg6 (see
preparatory work).
- Compile the project.
- Simulate the project (functional simulation using QUARTUS simulator).
Choose a simulation end time equal to 16s and adjust the grid to 1s.
Select inputs and outputs as busses in the node finder window:
Affect to DATA values from 0 to F, using the “count value” tool.
Compare the simulation results to the expected decoder’s true table.
- Optional: simulate the project (functional simulation) with ModelSim and using
the following simulation script:
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- Assign the pins according to the following table:
- Compile the project
- Program the FPGA
- Test the decoder.
- Create a symbol for further use:
File Create/Update Create Symbol File for Current File. The file
dec7seg1.sym is created and will be used later.
The symbol is stored into the current project folder.
It is available in the symbol window:
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ANNEXE1
DE2-70 pins assignments
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