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Instruction Groups
• The 8051 has 255 instructions
– Every 8-bit opcode from 00 to FF is used except for
A5.
Microcontroller Intel 8051
• The instructions are grouped into 5 groups
– Arithmetic
[Instruction Set] – Logic
– Data Transfer
– Boolean
– Branching
Structure of Assembly Language Arithmetic Instructions
• ADD
– 8-bit addition between the accumulator (A) and a
[ label: ] mnemonic [operands] [ ;comment ] second operand.
• The result is always in the accumulator.
Example: • The CY flag is set/reset appropriately.
• ADDC
MOV R1, #25H ; load data 25H into R1
– 8-bit addition between the accumulator, a second
operand and the previous value of the CY flag.
• Useful for 16-bit addition in two steps.
• The CY flag is set/reset appropriately.
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8051 Assembly Language Arithmetic Instructions
• DA
• Registers – Decimal adjust the accumulator.
• Format the accumulator into a proper 2 digit packed BCD number.
• Operates only on the accumulator.
• Works only after the ADD instruction.
• SUBB
– Subtract with Borrow.
MOV Instruction: • Subtract an operand and the previous value of the borrow (carry)
flag from the accumulator.
MOV destination, source – A A - <operand> - CY.
– The result is always saved in the accumulator.
Example: – The CY flag is set/reset appropriately.
1. MOV A, $55H
2. MOV R0, A
3. MOV A, R3
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Arithmetic Instructions Logical Operations
• INC • RL / RLC / RR / RRC
– Increment the operand by one.
• The operand can be a register, a direct address, an indirect
– Rotate the accumulator.
address, the data pointer. • RL and RR without the carry
• RLC and RRC rotate through the carry.
• DEC
– Decrement the operand by one.
• The operand can be a register, a direct address, an indirect • SWAP A
address.
– Swap the upper and lower nibbles of the accumulator.
• MUL AB / DIV AB
– Multiply A by B and place result in A:B. • No compare instruction.
– Divide A by B and place result in A:B. – Built into conditional branching instructions.
Logical Operations Data Transfer Instructions
• ANL / ORL • MOV
– Work on byte sized operands or the CY flag. – 8-bit data transfer for internal RAM and the SFR.
• ANL A, Rn • MOV A, Rn MOV A, direct
• ANL A, direct • MOV A, @Ri MOV A, #data
• ANL A, @Ri • MOV Rn, A MOV Rn, direct
• ANL A, #data • MOV Rn, #data MOV direct, A
• MOV direct, Rn MOV direct, direct
• ANL direct, A
• MOV direct, @Ri MOV direct, #data
• ANL direct, #data
• MOV @Ri, A MOV @Ri, direct
• ANL C, bit
• MOV @Ri, #data
• ANL C, /bit
Logical Operations Data Transfer Operations
• XRL • MOV
– Works on bytes only. – 1-bit data transfer involving the CY flag
• MOV C, bit
• MOV bit, C
• CPL / CLR
– Complement / Clear.
– Work on the accumulator or a bit. • MOV
• CLR P1.2 – 16-bit data transfer involving the DPTR
• MOV DPTR, #data
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Data Transfer Instructions Data Transfer Instructions
• XCH
• MOVC – Exchange accumulator and a byte variable
– Move Code Byte • XCH A, Rn
• XCH A, direct
• Load the accumulator with a byte from program
• XCH A, @Ri
memory.
• Must use indexed addressing • XCHD
– Exchange lower digit of accumulator with the lower digit of the
memory location specified.
MOVC A, @A+DPTR
• XCHD A, @Ri
MOVC A, @A+PC
• The lower 4-bits of the accumulator are exchanged with the
lower 4-bits of the internal memory location identified
indirectly by the index register.
• The upper 4-bits of each are not modified.
Data Transfer Instructions Boolean Operations
• MOVX • This group of instructions is associated with the single-bit
operations of the 8051.
– Data transfer between the accumulator and a
• This group allows manipulating the individual bits of bit
byte from external data memory. addressable registers and memory locations as well as
• MOVX A, @Ri the CY flag.
• MOVX A, @DPTR – The P, OV, and AC flags cannot be directly altered.
• MOVX @Ri, A
• MOVX @DPTR, A • This group includes:
– Set, clear, and, or complement, move.
– Conditional jumps.
Data Transfer Instructions Boolean Operations
• CLR
• PUSH / POP – Clear a bit or the CY flag.
• CLR P1.1
– Push and Pop a data byte onto the stack. • CLR C
– The data byte is identified by a direct address
from the internal RAM locations. • SETB
– Set a bit or the CY flag.
• SETB A.2
• PUSH DPL • SETB C
• POP 40H
• CPL
– Complement a bit or the CY flag.
• CPL 40H ; Complement bit 40 of the bit
addressable memory
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Boolean Operations Branching Instructions
• ORL / ANL – Absolute Jump – AJMP
– OR / AND a bit with the CY flag. • Uses an 11-bit address.
• ORL C, 20H ; OR bit 20 of bit addressable • 2 byte instruction
; memory with the CY flag The upper 3-bits of the address combine with the 5-bit
opcode to form the 1st byte and the lower 8-bits of the
• ANL C, /34H ; AND complement of bit 34 of bit address form the 2nd byte.
addressable memory with the CY • The 11-bit address is substituted for the lower 11-bits of the
flag. PC to calculate the 16-bit address of the target.
• MOV The location referenced must be within the 2K Byte
– Data transfer between a bit and the CY flag. memory page containing the AJMP instruction.
• MOV C, 3FH ; Copy the CY flag to bit 3F of the
bit addressable memory. – Indirect Jump – JMP
• MOV P1.2, C ; Copy the CY flag to bit 2 of P1. • JMP @A + DPTR
Boolean Operations Branching Instructions
• JC / JNC • The 8051 provides 2 forms for the CALL instruction:
– Jump to a relative address if CY is set / cleared. – Absolute Call – ACALL
• Uses an 11-bit address similar to AJMP
• JB / JNB • The subroutine must be within the same 2K page.
– Jump to a relative address if a bit is set / cleared. – Long Call – LCALL
• JB ACC.2, <label> • Uses a 16-bit address similar to LJMP
• The subroutine can be anywhere.
• JBC
– Jump to a relative address if a bit is set and clear the bit. – Both forms push the 16-bit address of the next instruction
on the stack and update the stack pointer.
Branching Instructions Branching Instructions
• The 8051 provides four different types of • The 8051 provides 2 forms for the return instruction:
– Return from subroutine – RET
unconditional jump instructions:
• Pop the return address from the stack and continue
– Short Jump – SJMP execution there.
• Uses an 8-bit signed offset relative to the 1st byte of the next
– Return from ISV – RETI
instruction.
• Pop the return address from the stack.
– Long Jump – LJMP
• Restore the interrupt logic to accept additional
• Uses a 16-bit address.
interrupts at the same priority level as the one just
• 3 byte instruction capable of referencing any location in the
processed.
entire 64K of program memory.
• Continue execution at the address retrieved from the
stack.
• The PSW is not automatically restored.
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Branching Instructions Branching Instructions
• The 8051 supports 5 different conditional jump instructions. • Decrement and Jump if Not Zero – DJNZ
– ALL conditional jump instructions use an 8-bit signed – Decrement the first operand by 1 and jump to the
offset. location identified by the second operand if the
resulting value is not zero.
– Jump on Zero – JZ / JNZ
• Jump if the A == 0 / A != 0 DJNZ Rn, rel
– The check is done at the time of the instruction DJNZ direct, rel
execution.
• No Operation
– Jump on Carry – JC / JNC
– NOP
• Jump if the C flag is set / cleared.
Branching Instructions Addressing Modes
– Jump on Bit – JB / JNB • Five addressing modes are available:
– Immediate
• Jump if the specified bit is set / cleared.
– Register
• Any addressable bit can be specified. – Direct
– Indirect
– Jump if the Bit is set then Clear the bit – JBC – Indexed
• Jump if the specified bit is set.
• There are three more modes:
• Then clear the bit. – Relative
– Absolute
– Long
These are used with calls, branches and jumps and are handled
automatically by the assembler.
Branching Instructions Immediate Addressing
• Compare and Jump if Not Equal – CJNE • The data is directly specified in the instruction.
• Useful for getting constants into registers.
– Compare the magnitude of the two operands and • Immediate data must be preceded with a “#” sign.
jump if they are not equal.
• The values are considered to be unsigned. • MOV R0, #0F0H ; Load R0 with the value F0H
• The Carry flag is set / cleared appropriately.
– The immediate value is a maximum of 8-bits.
• One exception, when dealing with the DPTR register it can
CJNE A, direct, rel be 16-bits.
CJNE A, #data, rel
CJNE Rn, #data, rel • MOV DPTR, #2000H ; Load the value 2000H into the
CJNE @Ri, #data, rel DPTR register
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Register Addressing Mode Indirect Addressing
• Direct access to eight registers – R0 through R7. • Can also be used for accessing external memory:
• MOV A, R0
• MOV R1, A
– Can use R0 and R1 to point to external memory
• ADD A, R1 locations 00H to FFH.
• Not all combinations are valid. • MOVX A, @R1 ; Move contents of external
– MOV R2, R1 ; Invalid memory location whose address
is in R1 into A
• There are 4 banks of registers accessible through register
addressing. – Can also use DPTR to point to all 64k of external
– Only one bank can be accessed at a time controllable through bit memory.
RS0 and RS1 of the PSW. • MOVX A, @DPTR
• MOV PSW, #00011000B
• Set RS0:RS1 to 11, therefore, accessing register bank 3.
Direct Addressing Indexed Addressing
• Direct addressing can access any on-chip hardware register. • Use a register for storing a pointer to memory
– All on-chip memory locations and registers have 8-bit
addresses. and another register for storing an offset.
– The effective address is the sum of the two:
– Can use the 8-bit address in the instruction. • EA = Pointer + Offset
• MOV A, 4H ; Amem[04H]
• MOVC A, @A+DPTR ; Move byte from memory
– Or can use the register name. located at DPTR+A to A.
• MOV A, R4
– Don’t get confused with Immediate mode.
• No “#” sign.
Indirect Addressing Program Control Instructions
• Unconditional Branch
• R0 and R1 may be used as pointer registers – ajmp addr11 ; absolute jump
– ljmp addr16 ; long jump
where their contents indicate an address in – sjmp rel ; short jump to relative address
internal RAM where the data is to be read or – jmp @A+DPTR ; jump indirect
written.
• Conditional branch
– jz, jnz rel ; short conditional jump to rel. addr
• MOV R1, #40H ; Make R1 point to location 40 – djnz rel ; decrement and jump if not zero
– cjne rel ; compare and jump if not equal
• MOV A, @R1 ; Move the contents of 40H to A • Subroutine Call
– acall addr11 ; absolute subroutine call
• MOV @R0, R1 ; Move contents of R1 into the – lcall addr16 ; long subroutine call
; memory location pointed to by R0. – ret ; return from subroutine call
– reti ; return from ISV
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Target Address Unconditional Jumps
• Target address can be,
• LJMP addr16
– absolute: A complete physical address
• addr16: 16 bit address, anywhere in the 64k – Long jump.
• addr11: 11 bit address, anywhere within 2k page. • Jump to a 2byte target address
– rel: relative (forward or backward) -128 bytes to +127 bytes – 3 byte instruction
from the current code location
• Target address calculation for relative jumps
– PC of next instruction + rel address • SJMP rel
– For jump backwards, drop the carry – Jump to a relative address from PC+127 to PC-128
• PC = 15H, SJMP 0FEH • Jump to PC + 127 (00H – 7FH)
• Address is 15H + FEH = 13H • Jump to PC – 128 (80H – FFH)
• Basically jump to next instruction minus two (current
instruction)
Conditional Jumps Call Instructions
• jz, jnz : Conditional on A=0 • Subroutines:
– Checks to see if A is zero – Reusable code snippets
– jz jumps if A is zero and jnz jumps is A not zero • LCALL addr16
– No arithmetic op need be performed (unlike 8086/8085) – Long call.
• djnz : dec a byte and jump if not equal to zero • 3 byte instruction.
– djnz Rn, rel – Call any subroutine in entire 64k code space
– djnz direct, rel – PC is stored on the stack
• jnc : Conditional on carry CY flag • ACALL addr11
– jc rel – 2 byte instruction
– jnc rel – Call any subroutine within 2k of code space
• cjne : compare and jump if not equal – Other than this, same behavior as LCALL
– cjne A, direct, rel – Saves code ROM for devices with less than 64K ROM
– cjne Rn, #data, rel • RET
– cjne @Rn, #data, rel – Return from a subroutine call, Pops PC from stack
Loop using djnz
• Add 3 to A ten times
mov A, #0 ; clear A
mov R2, #10 ; R2 10, can also say 0AH
AGAIN: add A, #03 ; add 3 to A
djnz R2, AGAIN ; repeat until R2==0
mov R5, A ; save the result in R5
• Loop within loop using djnz
mov R3, #100
loop1: mov R2, #10 ; trying for 1000 loop iterations
loop2: nop ; no operation
djnz R2, loop2 ; repeat loop2 until R2==0
djnz R3, loop1 ; repeat loop1 until R3==0
