Customer Specific Device from ON Semiconductor

PWM Current-Mode
DAP018A/B/C/D/F Controller for High-Power
Universal Off-Line Supplies
Housed in a SO−14 package, the DAP018X represents an • Auto−recovery internal output short−circuit protection
enhanced version of the currently available Speedking for A, B, C and D versions. F is latched
controller, the DAP011. • Adjustable Timer for Improved Short−circuit Protection
With an internal structure operating at a fixed 65 kHz or
• OTP and OVP Inputs for Improved Robustness
100 kHz frequency, the controller directly connects to the
high−voltage rail for a lossless and clean startup sequence. • +500 mA / −800 mA Peak Current Capability
Current−mode control also provides an excellent input • Up to 28 V VCC Operation
audio−susceptibility and inherent pulse−by−pulse control. • Improved Creepage Distance between High−voltage
Internal ramp compensation easily prevents sub−harmonic and Adjacent Pin
oscillations from taking place in continuous conduction • Extremely Low No−load Standby Power
mode designs. On top of these features, the device takes • This is a Pb−Free Device
advantage of the auxiliary winding negative swing to let the
user adjust the maximum power the converter can deliver in
• This Device uses Halogen−Free Molding Compound
high line conditions (OPP). Typical Applications
When the current setpoint falls below a given value, e.g. • High Power ac−dc Converters for TVs, Set−top Boxes etc.
the output power demand diminishes, the IC automatically • Offline Adapters for Notebooks
freezes the peak current and reduces its switching frequency
down to 25 kHz. At this point, if further output power SOIC−14 MARKING
14 D SUFFIX DIAGRAM
reduction occurs, the controller enters skip−cycle. CASE 751A
1
The DAP018X features an efficient protective circuitry
which, in presence of an overcurrent condition, disables the x = Device Version 14
output pulses while the device enters a safe burst mode, A = Assembly Location
WL = Wafer Lot DAP018x
trying to re−start. Once the fault has gone, the device AWLYWWG
Y = Year
auto−recovers. By implementing a timer to acknowledge a WW = Work Week
fault condition, independently from the auxiliary supply, the 1
G = Pb−Free Package
designer’s task is eased when stringent fault mode
conditions need to be met. PIN CONNECTIONS
A dedicated input helps triggering a latch−off circuitry 1 14
OPP HV
which permanently disables output pulses, for instance to 2 13
OVP NC
implement an over voltage protection (OVP). A separate 3 12
input accepts a direct NTC connection to ground for a simple CTimer OTP
4 11
and efficient over temperature protection (OTP). Jittering BO(B&D)
5 10
Features Fold VCC
6 9
• Fixed−frequency 65 kHz (A and B versions) or 100 kHz FB DRV
7 8
(C and D versions) Current−mode Control Operation CS GND
• Internal and Adjustable Over Power Protection (OPP) (Top View)
Circuit
• Frequency Foldback down to 25 kHz and Skip−cycle in ORDERING INFORMATION
See detailed ordering and shipping information in the package
Light Load Conditions dimensions section on page 3 of this data sheet.
• Reduced Internal Bias Currents for Improved Standby
Performance †For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
• Adjustable Brown−out Protection (B and D versions) Packaging Specifications Brochure, BRD8011/D.
• Internal Ramp Compensation *For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
• Internal Fixed 5 ms Soft−Start Mounting Techniques Reference Manual, SOLDERRM/D.
• Adjustable Frequency Jittering for Better EMI Signature

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

July, 2009 − Rev. 0 DAP018/D
 DAP018A/B/C/D/F

Vbulk ROPPU
OVP

*See
1 14
Note
+ Vout
2 13
3 12

ROPPL 4 11 NC /
A&C Gnd
5 10
*This resistor
6 9 prevents from
+
7 8 negatively biasing
the HV pin (14) at
power−off. Typical
value is 4.7 kW.
Ramp +

OTP

Foldback Timer Freq.

Gnd
Adj. Delay Jitter
Figure 1. Typical Application Example

Pin No. Pin Name Function Pin Description

1 OPP Adjust the Over Power Protection A resistive divider from the auxiliary winding to this pin sets the
OPP compensation level.
2 OVP Input voltage to latch comparator This pin offers an over−voltage protection input.
3 CTimer Timer Wiring a capacitor to ground helps selecting the timer duration.
4 Jitter Frequency jittering speed This pin offers a way to adjust the frequency modulation pace.
5 Foldback / skip Frequency foldback / By connecting a resistor to ground, it becomes possible to re-
skip cycle adjustment duce the level at which frequency foldback occurs.
6 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation.
7 CS Current sense + This pin monitors the primary peak current but also offers a
ramp compensation means to introduce ramp compensation.
8 GND − The controller ground.
9 DRV Driver output The driver’s output to an external MOSFET gate.
10 VCC Supplies the controller This pin is connected to an external auxiliary voltage.
11 BO Brown−out, B and D versions For B and D versions, this pin offers a brown−out input.
12 OTP NTC connection This pin connects to a pulldown NTC resistor for over temperat-
ure protection (OTP).
13 NC − Non−connected for improved creepage.
14 HV High−voltage input Connected to the bulk capacitor, this pin powers the internal
current source to deliver a startup current.

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 DAP018A/B/C/D/F

ORDERING INFORMATION
Brown− Short−
Delta Device ON Semiconductor Device Frequency Out Circuit Package Shipping†
DAP018ADR2G SCY99079ADR2G 65 kHz No Auto− SOIC−14 2500 / Tape & Reel
Recovery (Pb−Free)
DAP018BDR2G SCY99079BDR2G 65 kHz Yes Auto− SOIC−14 2500 / Tape & Reel
Recovery (Pb−Free)

DAP018CDR2G SCY99079CDR2G 100 kHz No Auto− SOIC−14 2500 / Tape & Reel
Recovery (Pb−Free)

DAP018DDR2G SCY99079DDR2G 100 kHz Yes Auto− SOIC−14 2500 / Tape & Reel
Recovery (Pb−Free)

DAP018FDR2G SCY99079FDR2G 65 kHz Yes Latched SOIC−14 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 DAP018A/B/C/D/F

OPP 1 VOTP
Soft−start ended? + +
Yes = 1, No = 0 -

Latch 2 +
-

+
Vlatch

20 ms time
from fault constant
in OCP
latched versions 5 V on
Timer 3 IpFlag Fault VDD
VCC Reset 14 HV
S
Q
Q 13 NC
R VCC and Logic IOTP
Management
5 V reset
BO (dble 12 OTP
Power hiccup reset)
BO release +
Vtimfault (B & D) on reset - IC1
+
- +
fault B and D versions
VDD + VCCON
turned
VCC(min)
Itim off when
VCClatch
BO ok
IpFlag + 11 BO
BO ok
-
Power On 20 ms time IBO
Reset constant +
VDD VBO
Jitter 4 VDD
65/100 kHz
Frequency
Clock
iCjit Modulation
S
Q
Q 10 VCC
Clamp
+ R
-
2.iCjit
+
9 Drv
VDD
Frequency
Ifold Foldback
Vfold
Fold 5
+
+ Skip -
+ -
Vskip 5 ms
SS
Rramp IpFlag
The soft−start is activated during:
VDD + − the startup sequence
- − the auto−recovery burst mode
Standby?
RFB /4.2 → bias − a brown−out release (B & D)
reduction
VFB/4.2 > Vset > Vfold/4.2
FB 6

VOPP Vlimit + VOPP

Vfold +

/4.2
CS 7 LEB 8 GND
+
Vlimit
Figure 2. Internal Circuit Architecture

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 DAP018A/B/C/D/F

MAXIMUM RATINGS TABLE

Symbol Rating Value Unit
VCCmax Maximum Power Supply Voltage, VCC Pin, Continuous Voltage −0.3 to 28 V
ICCmax Maximum Current for VCC Pin $30 mA
Maximum Voltage on Low Power Pins (Except Pins 9, 10 and 14) −0.3 to 10 V
IOPP Maximum Injected Negative Current into the OPP Pin (Pin 1) −2 mA
RθJ−A Thermal Resistance Junction−to−Air 120 °C/W
TJMAX Maximum Junction Temperature 150 °C
Storage Temperature Range −60 to +150 °C
ESD Capability, Human Body Model (All pins except HV) 2 kV
ESD Capability, Machine Model 180 V
Maximum Voltage on Pin 14 (HV) −0.3 to 500 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTES:This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000V per JEDEC Standard JESD22−A114E
Machine Model 200V per JEDEC Standard JESD22−A115−A
This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except pin 12.
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
SUPPLY SECTION
VCCON VCC increasing level at which the current source turns−off 10 14 15 16 V
VCC(min) VCC level below which output pulses are stopped 10 8 9 10 V
VCClatch VCC decreasing level at which the latch−off phase ends 10 7.2 7.5 8.0 V
VCCreset Internal latch reset level 10 5 V
resetHyst Minimum voltage difference between VCClatch and VCCreset, TJ > 0°C − 0.8 V
VCCTSD VCC voltage when the TSD is activated (Note 2) − 6.5 7.1 V
ICC1 Internal IC consumption, no output load on pin 9 10 1.9 mA
ICC1light ICC1 for a feedback voltage equal to Vfold (internal bias reduction) 10 1.5 mA
ICC2 Internal IC consumption, 1 nF output load on pin 9 10 2.7 mA
ICC3 Internal IC consumption, latch−off phase 10 0.6 mA
ITSD Current consumption in TSD mode − 400 mA
INTERNAL START−UP CURRENT SOURCE – High−voltage pin biased to 60 Vdc.
Symbol Rating Pin Min Typ Max Unit
IC2 High−voltage current source, VCC = 10 V 14 3 6 9 mA
IC1 High−voltage current source, VCC = 0, TJ = 25°C 14 150 650 1200 mA
VTh VCC transition level for IC1 to IC2 toggling point 14 0.9 V
Ileak Leakage current for the high voltage source, 14 1 15 30 mA
Vpin 14 = 500 Vdc, VCC = 12 V, TJ > 0°C

DRIVE OUTPUT
Symbol Rating Pin Min Typ Max Unit
Tr Output voltage rise−time @ CL = 1 nF, 10−90% of a 12 V output signal 9 − 40 − ns
1. See characterization table for linearity over negative bias voltage.
2. Guaranteed by design.
3. The OTP parameters are selected to cope with a TTC03−474 which offers a resistance of 8.8 kW when heated to a temperature of 110°C.
4. The brown−out circuitry is disabled on versions A & C and operates on versions B & D.

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 DAP018A/B/C/D/F

ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
DRIVE OUTPUT
Symbol Rating Pin Min Typ Max Unit
Tf Output voltage fall−time @ CL = 1 nF, 10−90% of a 12 V output signal 9 − 25 − ns
Isource Source current capability at VDRV = 10.5 V 9 − 500 − mA
Isink Sink current capability at VDRV = 0 V 9 − 800 − mA
VDRVlow DRV pin level at VCC close to VCC(min) with a 33 kW resistor to GND 9 7.6 − − V
VDRVhigh DRV pin level at VCC = 28 V 9 10 15 17 V
CURRENT COMPARATOR
Symbol Rating Pin Min Typ Max Unit
IIB Input Bias Current @ 0.8 V input level on pin 7 7 0.02 mA
VLimit Maximum internal current setpoint – pin1 grounded 7 0.76 0.8 0.84 V
TDEL Propagation delay from current detection to gate off−state 7 100 150 ns
TLEB Leading Edge Blanking Duration 7 140 ns
TSS Internal soft−start duration activated upon startup, auto−recovery and BO − 5 ms
release for versions B & D, pin 1 grounded.

IOPPo Setpoint decrease for pin 1 biased to –300 mV (Note 1) 1 37.5 %

IOOPv Voltage setpoint for pin 1 biased to −300 mV (Note 1) 1 0.46 0.5 0.54 V
IOPPs Setpoint decrease for pin 1grounded 1 0 %
INTERNAL OSCILLATOR
Symbol Rating Pin Min Typ Max Unit
fOSC Oscillation frequency (65 kHz version, A & B) − 60 65 70 kHz
fOSC Oscillation frequency (100 kHz version, C & D) − 92 100 108 kHz
Dmax Maximum duty−cycle − 76 80 84 %
fjitter Frequency jittering in percentage of fOSC − ±5 %
fswing Swing frequency with a 22 nF capacitor to pin 4 4 300 Hz
ICjit Jittering modulator charging current 4 18 mA
VCjitP Jittering capacitor peak voltage 4 2.2 V
VCjitV Jittering capacitor valley voltage 4 0.8 V
FEEDBACK SECTION
Symbol Rating Pin Min Typ Max Unit
Rup Internal pull−up resistor 6 20 kW
RFB Equivalent resistor on FB pin 16 kW
Iratio Pin 6 to current setpoint division ratio − 4.2 kW
FREQUENCY FOLDBACK
Symbol Rating Pin Min Typ Max Unit
Ifold Internal foldback reference current 5 8.5 10 11.5 mA
Vfold Frequency folback level with a 100 kW resistor to ground 5 1 V
Iskip Skip current in percentage of the maximum excursion, for Vfold = 1 V 30 %
Ftrans Transition frequency below which skip−cycle occurs for TJ = 25°C – 21 25 29 kHz
Vskip Skip−cycle level voltage on the feedback pin 6 320 mV
1. See characterization table for linearity over negative bias voltage.
2. Guaranteed by design.
3. The OTP parameters are selected to cope with a TTC03−474 which offers a resistance of 8.8 kW when heated to a temperature of 110°C.
4. The brown−out circuitry is disabled on versions A & C and operates on versions B & D.

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 DAP018A/B/C/D/F

ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
INTERNAL RAMP COMPENSATION
Symbol Rating Pin Min Typ Max Unit
Vramp Internal ramp level @ 25°C (Note 2) 7 3.0 V
Rramp Internal ramp resistance to CS pin (Note 2) 7 20 kW
PROTECTIONS
Symbol Rating Pin Min Typ Max Unit
Vlatch Latching level input 2 2.85 3 3.25 V
Tlatch−del Delay before latch confirmation − 20 ms
VtimFault Timer level completion 3 4.3 V
Itim Timer capacitor charging current 3 12 mA
TimerL Timer length, Ctimer = 0.22 mF typical 3 100 ms
VBO Brown−Out level – B & D versions 11 0.95 1 1.05 V
IBO Hysteresis current, Vpin 11 < VBO – B & D versions, TJ = 25°C 11 9 10 11 mA
IBO Hysteresis current, Vpin 11 < VBO – B & D versions, −25°C < TJ < 25°C 11 8.6 10 11 mA
IBObias Brown−Out input bias current – B & D versions 11 0.02 mA
TBO−del Delay before brown−out confirmation − 20 ms
IOTP Over temperature shutdown current (Note 3) 12 101 113 124 mA
VOTP Over temperature latching voltage (Note 3) 12 0.95 1 1.05 V
TSD Temperature shutdown − 140 °C
TSD_hys Temperature shutdown hysteresis − 40 °C
1. See characterization table for linearity over negative bias voltage.
2. Guaranteed by design.
3. The OTP parameters are selected to cope with a TTC03−474 which offers a resistance of 8.8 kW when heated to a temperature of 110°C.
4. The brown−out circuitry is disabled on versions A & C and operates on versions B & D.

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 DAP018A/B/C/D/F

8 5.1
4.6
7.8
4.1
7.6 3.6
VCC_LATCH (V)

ICC (ma)
3.1
7.4
2.6
7.2 2.1

1.6
7
1.1

6.8 0.6
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 3. VCC_LATCH vs. Temperature Figure 4. ICC2 vs. Temperature

35 160

30 140

120
25
100
20
ILEAK (mA)

TDEL (ns)

80
15
60
10
40
5 20

0 0
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. High−Voltage Leakage Curren vs. Figure 6. Propagation Delay vs. Temperature
Temperature

5.1 0.85
0.84
0.83
4.6
0.82
VTIMFAULT (V)

0.81
VLIMIT (V)

4.1 0.8
0.79
0.78
3.6
0.77
0.76
3.1 0.75
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 7. Fault Timer Level vs. Temperature Figure 8. Current Sense Internal Setpoint vs.
Temperature

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 DAP018A/B/C/D/F

125 73

71
120
69

FOSC (kHz)
115 67
IOTP (mA)

65
110
63

61
105
59

100 57
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. OTP Current vs. Temperature Figure 10. Oscillator Frequency vs.
Temperature

85 15.9
84
83
15.4
82
VCC(ON) (V)

81
DMAX (%)

80 14.9
79
78
14.4
77
76
75 13.9
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. Maximum Duty−Cycle vs. Figure 12. VCC(ON) Voltage vs Temperature
Temperature

9.9 7.9

7.4
9.4
6.9
VCC(LATCH) (V)
VCC(MIN) (V)

8.9 6.4

5.9
8.4
5.4

7.9 4.9
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 13. VCC(MIN) Voltage vs Temperature Figure 14. VCC(LATCH) vs Temperature

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 DAP018A/B/C/D/F

5.9 4.9

4.4
5.4
3.9
4.9

RESETHYST (V)
VCC(RESET) (V)

3.4

4.4 2.9

2.4
3.9
1.9
3.4
1.4

2.9 0.9
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 15. VCC(RESET) vs Temperature Figure 16. VCC(LATCH)−VCCHYST vs
Temperature
5.1 5.1
4.6 4.6
4.1 4.1

3.6 ICC1(LIGHT) (mA) 3.6

ICC1 (ma)

3.1 3.1

2.6 2.6

2.1 2.1

1.6 1.6

1.1 1.1

0.6 0.6
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 17. ICC1 vs Temperature Figure 18. ICC1(LIGHT) vs Temperature

0.54 5

0.44 4

0.34 3
ICC3 (mA)

Vth (V)

0.24 2

0.14 1

0.04 0
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 19. ICC3 vs Temperature Figure 20. Threshold Voltage vs Temperature

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 DAP018A/B/C/D/F

18 18

17
16
16
14
VDRV(LOW) (V)

VDR(HIGH) (V)
15

12 14

13
10
12
8
11

6 10
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 21. VDRV(LOW) vs Temperature Figure 22. Drive Voltage VDRV(HIGH) vs
Temperature
340 3.4

290 2.9
VLSKIP (mV)

VRAMP (V)

240 2.4

190 1.9

140 1.4
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Skip Level vs. Temperature Figure 24. Ramp Level vs. Temperature

21 3.4

19 3.3

3.2
17
RRAMP (kW)

VLATCH (V)

3.1
15
3
13
2.9

11 2.8

9 2.7
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 25. Ramp Resistor Value vs. Figure 26. Latching Level vs. Temperature
Temperature

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 DAP018A/B/C/D/F

1.06 1.06

1.04 1.04

1.02 1.02
VOTP (V)

VBO (V)
1 1

0.98 0.98

0.96 0.96

0.94 0.94
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 27. VOTP Voltage vs. Temperature Figure 28. Brown−out Level vs. Temperature

10.9

10.4
IBO (mA)

9.9

9.4

8.9
−40 −15 −10 35 60 85 110 135
TEMPERATURE (°C)
Figure 29. Brown−out Hysteresis Current vs.
Temperature

8.9 1800
1600
7.9
1400
6.9 1200
IC2 (mA)

IC1 (mA)

1000
5.9
800
4.9 600
400
3.9
200
2.9 0
−40 −15 −10 35 60 85 110 135 −40 −15 −10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 30. IC2 Startup Current vs. Temperature Figure 31. IC1 Startup Current vs. Temperature

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 DAP018A/B/C/D/F

Application Information

Introduction recommend to put it in the vicinity of 1 V or slightly

SpeedKing II implements a standard current mode above.
architecture where the switch−off event is dictated by the • Bias reduction: the controller detects that standby
peak current setpoint. This component represents the ideal mode is entered by monitoring the feedback pin level.
candidate where low part−count is the key parameter, When this occurs, the circuit significantly reduces its
particularly in low−cost ac−dc adapters, open−frame power bias current by shutting down un−necessary blocks.
supplies etc. Thanks to its High−Voltage technology, the This improves the standby power further.
DAP−018X incorporates all the necessary components
• Brown−out: versions B & D include a brown−out (BO)
normally needed in today modern power supply designs,
detector. When the voltage sensed on this pin is below
bringing several enhancements such as an adjustable EMI
the BO level, the controller does not operate. When the
jittering and a fault timer...
voltage reaches the threshold, the controller pulses and
• Current−mode operation with internal ramp open the internal hysteresis current source. By
compensation: implementing peak current mode connecting a divider network between the bulk voltage
control, the DAP−018X offers an internal ramp and the BO pin, the designer has the flexibility to adjust
compensation signal that can easily by summed up to the turn−on and turn−off levels. For versions A & C,
the sensed current. Subharmonic oscillations can thus the brown−out circuitry is disabled and pin 11 is not
be fought via the inclusion of a simple resistor in series internally connected.
with the current−sense information.
• Internal soft−start: a soft−start precludes the main
• Internal OPP: by routing a portion of the negative power switch from being stressed upon start−up. In this
voltage present during the on−time on the auxiliary controller, the soft−start is internally fixed to 5 ms. The
winding to the dedicated OPP pin, the user has a simple soft−start is activated when a) a new startup sequence
and non−dissipative option to alter the maximum peak occurs – fresh startup or during an auto−recovery
current setpoint as the bulk voltage increases. If the pin hiccup b) when the controller recovers from a
is grounded, no OPP compensation occurs. If the pin brown−out condition (B & D versions).
receives a negative voltage down to –300 mV, then a
peak current reduction down to 40% typical can be
• OVP input: the Speedking II includes a latch input that
can be used to sense an overvoltage condition on the
achieved. For an improved performance, the maximum
adapter. If this pin is brought higher than the internal
voltage excursion on the sense resistor is limited to 0.8 V.
reference voltage Vlatch, then the circuit permanently
• Internal high−voltage startup switch: reaching a low latches off. The VCC pin swings up and down, keeping
no−load standby power represents a difficult exercise the controller latched. The latch reset occurs when
when the controller requires an external, lossy, resistor a) the user disconnects the adapter from the mains and
connected to the bulk capacitor. Thanks to an internal lets the VCC falls below the VCCreset value b) for
logic, the controller disables the high−voltage current versions B & D, if the internal BO circuitry senses a
source after startup which no longer hampers the bulk / mains reset, then the controller is also reset. In
consumption in no−load situations. this case, if the controller is within a hiccup cycle: the
• EMI jittering: a dedicated pin offers the ability to vary hiccup cycle is immediately reset and driving pulses
the pace at which the oscillator frequency is modulated. only re−appear on the output when VCC reaches
This helps spreading out energy in conducted noise VCC(on).
analysis. To avoid modulation conflicts, the jittering • OTP input: the controller incorporates an Over
will be disabled as soon as the controller enters Temperature Protection circuitry (OTP) which allows
frequency folback (light load conditions). the direct connection of a Negative Temperature
• Frequency foldback capability: a continuous flow of Coefficient (NTC) sensor from pin 12 to GND. When
pulses in not compatible with no−load standby power the temperature increases, the NTC resistor falls down.
requirements. The controller observes the feedback pin When the NTC reaches a 8.8 kW value (T = 110°C), the
and when it reaches a level determined by pin 5, the voltage developed across its terminal is VOTP. The
peak current freezes. The oscillator then starts to reduce internal comparator trips and latches−off the part. Reset
its switching frequency as the feedback level continues occurs in similar conditions as described in the OVP
to decrease. It can decrease down to 26 kHz (typical). section.
At this point, if the power continues to drop, the • Short−circuit protection: short−circuit and especially
controller enters classical skip−cycle mode at a peak over−load protection are difficult to implement when a
current set by pin 5 level. The point at which the strong leakage inductance between auxiliary and power
foldback occurs can be adjusted to any level, we

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 DAP018A/B/C/D/F

windings affects the transformer (the aux winding level typ.), the source delivers IC1 (around 500 mA typical), then,
does not properly collapse in presence of an output when VCC reaches 1.8 V, the source smoothly transitions to
short). Here, every time the internal 0.8 V maximum IC2 and delivers its nominal value. As a result, in case of
peak current limit is activated, an error flag, IpFlag, is short−circuit between VCC and GND, the power dissipation
asserted and a time period starts, thanks to an adjustable will drop to 370 x 500 m = 185 mW. Figure 33 portrays this
timer. If the timer reaches completion while the error particular behaviour:
flag is still present, the controller stops the pulses and
goes into a latch−off phase, operating in a VCC
low−frequency burst−mode. To limit the fault output
power, a divide−by−two circuitry is installed on the
VCC pin and requires twice a start−up sequence before VCC(on)
another attempt to re−start is. As soon as the fault IC2 min
disappears, the SMPS resumes operation. The latch−off
phase can also be initiated, more classically, when VCC CVCC = 33 mF
drops below VCC(min) (7.9 V typical).
IC1 min
Start−up Sequence Vth
When the power supply is first connected to the mains
outlet, the internal current source is biased and charges up
the VCC capacitor. When the voltage on this VCC capacitor t2
t1
reaches the VCC(on) level (typically 15 V), the current source
turns off, reducing the amount of power being dissipated. At Figure 33. The Startup Source Now Features a
this time, the VCC capacitor only supplies the controller, and Dual−level Startup Current
the auxiliary supply should take over before VCC collapses The first startup period is calculated by the formula C x V
below VCC(min). Figure 32 shows the internal arrangement = I x t, which implies a 22 m x 1.8 / 200 m = 198 ms startup
of this structure: time for the first sequence. The second sequence is obtained
by changing to 2 mA with a delta V of VCC(on) – VTh = 15
14 – 1.8 = 13.2 V, which finally leads to a second startup time
HV
of 13.2 x 22 m / 2m = 145 ms. The total startup time becomes
198 m + 140 m = 343 ms with a worst case condition on the
+
IC1 or 0 startup source only. Please note that this calculation is
-
approximated by the presence of the knee in the vicinity of
the transition.
10
As soon as VCC reaches VCC(on), drive pulses are
delivered on pin 9 and the auxiliary winding increases the
+
voltage on the VCC pin. Because the output voltage is below
+ the target (the SMPS is starting up), the controller smoothly
VCC(on)
ramps up the peak current to Ip,max (0.8 V / Rsense) which is
VCClatch
8 reached after a typical soft−start period. This soft−start
period is internally fixed and lasts typically 5 ms. As soon
as the peak current setpoint reaches its maximum (during the
startup period but also anytime an overload occurs), an
internal error flag is asserted, Ipflag, indicating that the
system has reached its maximum current limit set point (Ip
Figure 32. The Current Source Brings VCC Above = Ip,max). As soon as the error flag gets asserted, the current
15 V (typical) and then Turns Off source on pin 3 is activated and charges up the capacitor
In some fault situations, a short−circuit can purposely connected to this pin. If the error flag is still asserted when
occur between VCC and ground. In high line conditions the timer capacitor has reached the threshold level
(VHV = 370 Vdc) the current delivered by the startup device VtimFault, (which is about 100 ms with a 0.22 mF typically),
will seriously increase the junction temperature. For then the controller assumes that the power supply has really
instance, since IC1 equals 2 mA (the min corresponds to the undergone a fault condition and immediately stops all pulses
highest TJ), the device would dissipate 370 x 2m = 740 mW. to enter a safe burst operation. Figure 34 depicts the VCC
To avoid this situation, the controller includes a novel evolution during a proper startup sequence, showing the
circuitry made of two startup levels, IC1 and IC2. At state of the internal error flag:
power−up, as long as VCC is below a certain level (1.8 V

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 DAP018A/B/C/D/F

VCC
VCC(on)

VCC(min)

VCClatch

VCCreset

VFB Feedback loops

Full power reacts...
User
Powers up!
regulation

Freq. foldback / skip level

Current
setpoint Ip,max

IpFlag
SS = 5 ms

Timer No error has

been confirmed

100ms

Figure 34. An Error Flag gets Asserted

An error flag gets asserted as soon as the current setpoint reaches its upper limit (0.8 V/Rsense). Here the timer lasts 100 ms,
a 0.22 mF capacitor being connected to pin 3.

Short−circuit or Overload Mode fault. However, there are numerous charger

There can be various events that force a fault on the applications where the output voltage shall not go
primary side controller. We can split them in different below a certain limit, even if the current is
situation, each having a particular configuration: controlled. To cope with this situation, the
1. the converter regulates but the auxiliary winding controller features a precise under−voltage lockout
collapses: this is a typical situation linked to the comparator biased to a VCC(min) level. When this
usage of a constant−current / constant−voltage level is crossed, whatever the other pin conditions,
(CC−CV) type of secondary−side controller. If the pulses are stopped and the controller enters the
output current increases, the voltage feedback loop safe hiccup mode, trying to re−start. Figure 35
gives up and the current loop takes over. It means shows how the converter will behave in this
that Vout goes low but the feedback loop is still situation. If the fault goes away, the SMPS
closed because of the output current monitoring. resumes operation.
Therefore, seen from the primary side, there is no

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 DAP018A/B/C/D/F

Can be very
slow...
VCC(on)
VCC
VCC(min)

VCClatch

VCCreset
VFB

Duration given
regulation by aux. cap.

IpFlag

Current loop
action keeps FB
OK (CC operation)

Timer

Drv
< 100ms
< 100ms

Figure 35. First Fault Mode Case

First fault mode case, the auxiliary winding collapses but feedback is still there (0.22 mF timer capacitor)

2. In the second case, the converter operates in to the maximum and the timer starts to count.
regulation, but the output is severely overloaded. Upon completion, all pulses are stopped and
However, due to the bad coupling between the dual−startup hiccup mode is entered. If the fault
power and the auxiliary windings, the controller goes away, the SMPS resumes operation.
VCC does not go low. The peak current is pushed

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 DAP018A/B/C/D/F

Vout is overloaded (aux is alive)

VCC
VCC(on)
VCC(min)
VCClatch
VCCreset

VFB Duration given

by timer
Reg.

IpFlag

Timer

Drv
< 100ms 100ms 100ms

Figure 36. This Case is Similar to a Short−circuit where Vaux does NOT Collapse

3. A third case exists where the short−circuit makes stopped. The double hiccup fault mode is entered
the auxiliary level go below VCC(min). In that case, and the SMPS tries to re−start. When the fault is
the timer length is truncated and all pulses are removed, the SMPS resumes operation.

Vout is shorted (aux is gone)

VCC
VCC(on)
VCC(min)

VCClatch
VCCreset

VFB
Duration given
by aux. cap.
Reg.

IpFlag

Timer

Drv
< 100ms
< 100ms

Figure 37. This Case is Similar to a Short−circuit where Vaux Does Collapse

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 DAP018A/B/C/D/F

The recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the VCC capacitor. Figure 38
details the various time portion a hiccup is made of:

VCC

VCC(on)

t3
VCC(min)

t1 t2 t′1
t′2
VCClatch
VCCreset

Drv

timer timer

Figure 38. The Burst Period is Ensured by the VCC Capacitor

Charge / Discharge Cycle (here a 0.22 mF capacitor on timer)

If by design we have selected a 22 mF VCC capacitor, it Latch−off and Over Voltage Protection
becomes easy to evaluate the burst period and its duty−cycle. Speedking II features a fast comparator that permanently
This can be done by properly identifying all time events on monitors pin 2 level. Figure 39 details how it is internally
Figure 38 and applying the classical formula: arranged:

t + CDV
I
VCCaux
• t1: I = ICC3 = 600 mA, Rupper + aux.
ΔV = 9 – 6.5 = 2.5 V ³ t1 = 91 ms 20 ms
time
• t2: I = 3 mA, ΔV = 15 – 6.5 = 8.5 V ³ t1 = 62 ms 2
constant
+
• t3: I = 600 mA, ΔV = 15 – 6.5 = 8.5 V ³ t1 = 311 ms -
• t′1 = t1 = 91 ms C1
Rlower S Latched
• t′2 = t2 = 62 ms 10 nF + Q Fault
The total period duration is thus the sum of all these events Vlatch Q
which leads to Tfault = 617 ms. If the timer lasts 100 ms, then R
our duty−cycle in auto−recovery burst equals 100/(617 +
100) ≈ 13%, which is good. Should the user like to further
decrease or, to the contrary, increase this duty−cycle, 5 V Reset
changing the VCC capacitor is an easy job. Figure 39. A Comparator Monitors Pin 2 and
Latches−off the Part in Case the Threshold is
Reached

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 DAP018A/B/C/D/F

VCC

VCC(on)
VCC(on)
VCC(min)
VCC(min)

VCClatch
VCCreset

Drv The user has unplugged, reset!

Vlatch

Fault!
Vlatch

Figure 40. The Part is Reset when VCC Reaches 5 V or when BO

Senses the Bulk Capacitor Voltage is Back to Normal

If for any reason the latch pin level grows above Vlatch, the • for B & D versions, a reset can occur if the brown−out
part immediately stops pulsing and stays latched in this circuitry is asserted before the VCC reaches 5 V.
position until the user cycles down the power supply. The
reset actually occurs if VCC drops below 5 V, e.g. if the Soft−start
adapter user disconnects it from the mains. Figure 40 details The Speedking II features an internal soft−start circuit
the operating diagrams in case of a fault. Please note the activated during the power on sequence (PON) but also in
presence of RC time constant on the comparator output, fault recovery (short−circuit protection or brown−out
aimed to filtering any spurious oscillations linked to an release). As soon as VCC reaches VCC(on), the peak current
eventual noise presence. The typical value of this time is gradually increased from nearly zero up to the maximum
constant is 20 ms. clamping level (e.g. 0.8 V/Rsense). The peak current is
On both OVP and OTP events and in the case of a clamped at 0.8 V/Rsense through the entire soft−start period
latched−OCP version, the latch reset occurs in the following until the supply enters regulation. Figure 41 shows a typical
conditions: startup shot.
• a user reset via a mains interruption (unplug and replug
adapter) which is long enough to let the VCC capacitor
discharge to the controller reset level of 5 V.
vss vcc
1.30 Ip(t)
5 ms
900m
vss in volts
Plot1

500m

100m
1
−300m
8.56m 9.23m 9.90m 10.6m 11.2m
13.0 VCC VCC(on)
vcc in volts

12.0
2
Plot2

11.0

10.0

9.00
7.95m 8.95m 9.95m 10.9m 11.9m
time in seconds
Figure 41. Soft−start is Activated During a Start−up Sequence, an
Auto−recovery Burst−mode or when the Brown−out Pin is Released

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 DAP018A/B/C/D/F

The soft−start is activated in the following conditions: In the Speedking II controller, the oscillator ramp features
• Startup sequence: when the user powers the adapter, the a 1.8 V swing. If our clock operates at a 65 kHz frequency,
peak current smoothly ramps−up from a low value then the oscillator slope corresponds to a 120 mV/ms ramp.
towards a maximum value defined by the sense resistor. In our flyback design, let’s assume that our primary
• In auto−recovery burst−mode (e.g. during a inductance Lp is 350 mH, and the SMPS delivers 12 V with
non−latched short−circuit), each new set of pulses starts a Np:Ns ratio of 1:0.1. The off−time primary current slope is
with a soft−start sequence. thus given by:
• When the brown−out pin senses a reset on the bulk N
ǒV out ) V fǓ @ NS
P
voltage, the controller restarts via a soft−start sequence, + 371 mAńms or 37 mVńms
LP
just like a fresh power−on sequence.
* Please note that Speedking II does use implement the when projected over a sense resistor Rsense of 0.1W, for
soft−burst technique as built in the original Speedking circuit. instance. If we select 75% of the downslope as the required
amount of ramp compensation, then we shall inject
Internal Ramp Compensation 27 mV/ms. Our internal compensation being of 120 mV/ms,
Ramp compensation is a known mean to cure the divider ratio (divratio) between Rcomp and the 20 kW is
subharmonic oscillations. These oscillations take place at 0.225. Rcomp can therefore be obtained using the following
half the switching frequency and occur only during value:
Continuous Conduction Mode (CCM) with a duty−cycle R ramp @ divratio 20 k 0.225
greater than 50%. To lower the current loop gain, one usually R comp + + + 5.8 kW
(1 * divratio) 1 * 0.225
injects between 50 and 100% of the inductor downslope.
Figure 42 depicts how internally the ramp is generated. Brown−out Protection
* Please note that the ramp signal will be disconnected from Versions B and D of the controller include a dedicated
the CS pin, during the OFF time. circuitry which permanently monitors the bulk capacitor
level. Figure 43 depicts the comparator arrangement known
1.8 V as a brown−out protection:
0V
bulk
ON

Latch Rupper
Reset 3.3Meg
20 k BO
−
+ L.E.B.
- CS Rcomp Brown Out
+

Rsense Rlower
from FB Setpoint VBO IBO 10k
1V 10 m

Figure 42. Inserting a Resistor

Inserting a resistor in series with the current sense
information brings ramp compensation and stabilizes the Figure 43. A Brown−out Circuit Protects the
converter in CCM operation. Power Supply against Low Input Voltages

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 DAP018A/B/C/D/F

When the input voltage is low, below VBO(on), the BO an OVP for instance (or a latched OCP for this particular
comparator output is low and the current source is activated, version). When the BO comparator has given the
drawing 10 mA from the BO pin (pin 11) to ground. The authorization to work, the controller resets its hiccup mode
controller is silent, and no driving pulses are delivered to the on the VCC (if any) and waits for the next VCC(on) event to
power MOSFET. When the input is sufficiently high, the BO start pulsing again (via soft−start sequence). A 20 ms RC
comparator toggles high and shuts down the current source, time−constant has been added in series with the brown−out
providing the necessary hysteresis to the circuit. When comparator to further avoid false trigger of the controller.
toggling high, the BO signal also resets ALL the internal Figure 44 shows typical signals in presence of a
logic circuits including an eventual latch state triggered by brown−out suddenly occuring and coming back again:

Controller waits for

the next VCC(on) event
VCC
Double hiccup 1 restart
VCC(on)
VCC(min)

VCClatch
VCCreset
BO acknowledged
here: hiccup reset
Vbulk
VBO(on)

Mains
Interruption
VBO(off)

BO
signal
General
internal reset
(latch...)

Drv

Figure 44. A Brown−out Event Immediately Stops the Driving Pulses

When the bulk comes back to its normal level, the controller waits for the next VCC(on) event to re−start pulsing. If the
controller was in a double−hiccup mode, the logic circuit is reset to accelerate the restart to the next VCC(on) event.

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 DAP018A/B/C/D/F

Controller waits for the next VCC(on) event (fresh re−start)

VCC
restart
VCC(on)
VCC(min)

VCClatch
VCCreset

Vbulk
VBO(on)

VBO(off)
Mains interruption

BO
signal

The BO information is latched. The next re−start

occurs when VCC hits VCC(on) again

Drv

Figure 45. A Brown−out Event Immediately Stops the Driving Pulses

When the bulk comes back to its normal level, the Frequency Foldback and Skip Cycle
controller waits for the next VCC(on) event to re−start Unlike its predecessor, Speedking II implements a
pulsing. In this case, the BO re−appears while VCC was still frequency reduction in low power mode. Also called
ok but the controller waits for VCC to ramp down to VCClatch frequency foldback, this technique has proven to offer a
then performs a fresh re−start before pulsing again. good performance, especially in the middle of the power
The bridge resistors can be evaluated using the following range. On this controller, the foldback occurs when the peak
equations: current reaches a level set via the original skip pin (pin 5).
V BO,on * V BO,off Once the peak current reaches this value, via a decrease in
R upper + (eq. 1) the feedback voltage, the controller freezes it and the only
I BO
way to further reduce the output power is to fold the
V BOR upper frequency back. The frequency variation is ensured over a
R lower + (eq. 2) delta feedback voltage of around 500 mV. When the
V BO,off * V BO
frequency hits the frequency limit (Ftrans), the frequency
Where VBO = 1 V typical and IBO = 10 mA typical. reduction is stopped. At this point, if the load goes further
Suppose the adapter designer needs a turn−on voltage of down, the feedback voltage drops and when it reaches
100 Vdc and a turn−off voltage of 50 Vdc, then the upper 300 mV, the controller enters traditional skip−cycle (no
resistor would be 4.9 MW and the lower side resistor 100 kW. soft−burst).
The total dissipation for a 330 Vdc bulk rail would amount At full power, the peak current varies according to the
to 22 mW. power demand, the switching frequency being fixed to
* Please note that the current source arrangement brings 65 kHz. The feedback voltage is allowed to move between
un−precision to the turn−on voltage only, whereas the 300 mV and 3.4 V which is the upper feedback limit beyond
turn−off voltage is only dependent on the VBO reference which a fault is detected. When the load starts to decrease,
voltage. the feedback voltage goes down to impose lower peak

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 DAP018A/B/C/D/F

currents. When the feedback pin reaches the Vfold level, the (typical), naturally reducing the amount of transmitted
peak current is set to Vfold /4.2 and cannot decrease power. When the feedback touches a typical 300 mV limit,
anymore. The feedback voltage continues to go down but it skip−cycle takes place. The whole behavior is illustrated by
now changes the switching frequency down to 26 kHz Figure 46:

Figure 46. The Controller Changes its Operating Frequency in Light Load Conditions

Further details are given by Figure 47 which represents

both switching frequency and peak current setpoints in
relationship to the feedback voltage. Pin 5 provides a means
to alter the foldback limit. To fine tune the efficiency but also
to combine a low skip current level and a reduced acoustic
noise in standby, the designer must wire a resistor to ground
to set the foldback level (Figure 48). As we internally have
a 10 mA current source, the relationship is straightforward:
V fold
R fold + (eq. 3)
10 m
For instance, suppose we want to set the folback point to
1 V, then the resistor value should be 100 kW. We
recommend to put a 10 nF capacitor to ground on this pin.
Both the resistor and the capacitor must be placed very close
to the controller to avoid any noise pick−up.
Because the clock frequency must reach 26 kHz at a
feedback voltage of 300 mV, pin 5 level cannot be set too low
in order to provide enough dynamic range for the
Voltage−Controlled Oscillator (VCO). To obtain a good
linearity, we recommend a minimum voltage dynamics of
300 mV, which implies a level on pin 5 always above
600 mV. Also, setting the frequency foldback too low will
alter the performance in standby power.
The graphs in Figure 47 (65 kHz version) depict the
operation in light load conditions where the frequency is
decreased down to 26 kHz (typical)

Figure 47. Operation in Light Load Conditions

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 DAP018A/B/C/D/F

VDD

Ifold
10 m
Vfold

5 Foldback
Clock
Circuitry
C1 Rload
10 nF
/ 4.2
Skip Cycle
300 mV Comparator
+
-
6
Reset
/ 4.2

This point cannot

be lower than -
Vfold / 4.2 +
0.8 V
Current Sense
LEB Comparator

Figure 48. A Pulldown Resistor Adjusts the Foldback Level

Bias Reduction in Light Load

When the power supply enters deep standby mode relationship between the jitter ramp and the frequency
(skip−cycle is active), a comparator instructs the controller deviation.
that it entered in light load conditions. When this happens,
the circuit reduces various internal bias currents to further VDD
bring its consumption down and improve the consumption
in no−load conditions.
ICjit Frequency
Frequency Jittering Modulation To Clock
Frequency jittering is a method used to soften the EMI Circuit
Jitter
signature by spreading the energy in the vicinity of the main 4
+
switching component. Speedking II offers a ±5% deviation
-
of the nominal switching frequency. The sweep sawtooth is
internally generated and modulates the clock up and down Ctimer
with an adjustable period. Figure 49 displays the internal
2.iCjit
arrangement around pin 4. It is actually a I – 2I generator, +
producing a clean 50% duty−cycle sawtooth. If we take a
2 V swing on the jitter capacitor, then we calculate the VCjitP
needed value for a 4 ms period, or a 250 Hz modulation VCjitV
speed, again applying the V x C = I x t relationship. We need
2 ms to ramp−up and 2 ms to ramp down, therefore: C = 20 m Figure 49. An Internal Ramp is Used to Introduce
x 2 m / 2 = 20 nF. If we select a 22 nF, then our modulation Frequency Jittering on the Oscillator Sawtooth
frequency will be around 227 Hz... Figure 50 shows the

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 DAP018A/B/C/D/F

Jitter ramp
68.9kHz

65kHz

61.1kHz Internal
sawtooth
adjustable

Figure 50. Modulation Effects on the Clock Signal by the Jittering Sawtooth

Over Power Protection

There are several known ways to implement Over Power drawing, a voltage is derived from the auxiliary winding and
Protection (OPP), all suffering from particular problems. produces a negative level during the on−time of the main
These problems range from the added consumption burden power transistor. The negative voltage amplitude directly
on the converter or the skip−cycle disturbance brought by relates to the input level via the transformer turn ratio linking
the current−sense offset. A way to reduce the power the primary winding to the auxiliary winding. Figure 51
capability at high line is described by Figure 52. On this depicts the typical signal obtained on the auxiliary winding:

1 v(24)

40.0

off−time

20.0 N1(Vout + Vf)

1
v(24) in volts
Plot1

−20.0 −N2Vbulk

on−time
−40.0

464u 472u 480u 488u 496u

time in seconds
Figure 51. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time

During the off−time, the voltage plateaus to a positive voltage increases. The equations to design the network are
level depending on the turn ratio between the output winding fairly simple:
(Ns) and the power winding. This ratio is noted N1. During Suppose we need to reduce the peak current from 2.5 A at
the on−time, the transformer terminal swings to a negative low line, to 2 A at high line. This corresponds to 20%
voltage whose amplitude now depends on the turn ratio N2, reduction or a setpoint voltage of 640 mV. To reach this
equal to the primary (Np) to the auxiliary winding ratio level, then the negative voltage developed on the OPP pin
(Naux). If we place a resistive divider between the auxiliary must reach:
winding and the OPP pin, as suggested by Figure 52, we V OPP + 800 * 640 + −160 mV (eq. 4)
have a means to influence the internal setpoint as the bulk

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 DAP018A/B/C/D/F

RoppU
VCC aux
Swings to:
+
N1Vout during toff
−N2Vin during ton

This point will

be adjusted to from FB
VDD
reduce the ref
at hi line to the
Reset
desired level.
-
K1 SUM2
ref +
CS
OPP K2

Iopp 0.8 V ±5%

RoppL ref = 0.8 V + VOPP
(VOPP is negative)

Figure 52. The OPP Circuitry Affects the Maximum Peak Current Setpoint by
Summing a Negative Voltage to the Internal Voltage Reference

Let us assume that we have the following converter The OPP pin is made of zener diodes arranged to protect
characteristics: the pin against ESD pulses. These diodes accept some peak
Vout = 19 V current in the avalanche mode and are designed to sustain a
certain amount of energy. On the other side, negative
Vin = 85 to 265 Vrms
injection into these diodes (or forward bias) can cause
N1 = Np:Ns = 1:0.2 substrate injection wich can lead to an erratic circuit
N2 = Np:Naux = 1:0.16 behaviour. To avoid this problem, the pin is internall
Given the turn ratio between the primary and the auxiliary clamped slightly below –300 mV which means that if more
windings, the on−time voltage at high line (265 Vac) on the current is injected before reaching the ESR forward drop,
auxiliary winding swings down to: then the maximum peak reduction is kept to 40%. If the
V aux + −N 2V in,max + −0.16 375 + −60 V (eq. 5) voltage finally forward biases the internal zener diode, then
care must be taken to avoid injecting a current beyond
To obtain a level as imposed by Equation 3, we need to –2 mA. Given the value of ROPPU, there is no risk in the
install a divider featuring the following ratio: present example.
Div + 0.16 + 0.00266 (eq. 6) On Figure 53, we can see that the OPP starts to fold the
60 setpoint immediately from a low mains operation. This is no
If we arbitrarily fix the pulldown resistor ROPPL to 1 kW, different than a standard OPP circuitry built from a resistive
then the upper resistor can be obtained by: string placed between the bulk rail and the current sense pin.
R OPPU + 60 * 0.16 + 374 kW (eq. 7)
However, in some applications, it is good to remove the OPP
0.16ń1 k at low line and place a small threshold so that our OPP only
If we now plot the peak current setpoint obtained by changes the circuit power capability at high line only.
implementing the recommended resistor values, we obtain Figure 54 offers a possible solution built on a zener diode
the following curve: connection.

Peak currentsetpoint

100%

20%

Vbulk
375
Figure 53. The Peak Current Regularly Reduces
Down to 20% at 375 Vdc

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RoppU Dz
VCC aux
Rbias Swings to:
+
N1Vout during toff
−N2Vout during ton

This point will

be adjusted to from FB
VDD
reduce the ref
at hi line to the
Reset
desired level.
-
K1 SUM2
ref +
CS
OPP K2

Iopp 0.8 V ±5%

RoppL ref = 0.8 V + VOPP
(VOPP is negative)

Figure 54. The Zener Diode can Introduce a Threshold which

Disables OPP at Low Line for Maximum Power Capability

Suppose we need a threshold placed at 150 Vdc. In that Peak current

setpoint
case, give the turn ratio, we need to install a zener diode
featuring the following breakdown voltage: 100%
V z + 150 0.16 + 24 V (eq. 8)
20%
In high line conditions (Vbulk = 375 Vdc), the voltage on the
zener diode voltage will now swing to: Vbulk
150 375
(eq. 9)
V aux + −N 2V in,max ) 24 + −0.16 375 ) 24 + −36 V Figure 55. The Addition of the Zener Diode
Introduces a Threshold at 150 Vdc
Applying Equation 6 again, we have: The bias resistor Rbias, makes sure that enough current
circulates in the zener diode to make it work far enough from
R OPPU + 36 * 0.16 + 224 kW (eq. 10)
0.16ń1 k its knee. The tradeoff includes the power consumption
The new compensation now looks like what Figure 55 brought by the addition of this new component. Further
shows: reduction can be obtained by inserting a standard diode in
series with the zener to block the positive excursion.

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 DAP018A/B/C/D/F

PACKAGE DIMENSIONS

SOIC−14
D SUFFIX
CASE 751A−03 NOTES:
1. DIMENSIONING AND TOLERANCING PER
ISSUE H ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
−A− 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
−B− P 7 PL DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
0.25 (0.010) M B M DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1 7
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G R X 45 _ F A 8.55 8.75 0.337 0.344
C B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
−T− G 1.27 BSC 0.050 BSC
K M J
SEATING D 14 PL J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
0.25 (0.010) M T B S A S M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
SOLDERING FOOTPRINT
7X
7.04 14X
1.52
1
14X
0.58

1.27
PITCH

DIMENSIONS: MILLIMETERS

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