AN-1126 BGA (Ball Grid Array) : Application Report
AN-1126 BGA (Ball Grid Array) : Application Report
ABSTRACT
Leaders in the consumer electronics industry will be determined by their ability to deliver increasingly
miniaturized products at lower costs. The Ball Grid Array (BGA) package achieves these objectives by
providing increased functionality for the same package size while being compatible with existing Surface
Mount Technology (SMT) infrastructure.
Contents
1 Introduction .................................................................................................................. 3
2 Package Overview .......................................................................................................... 3
2.1 PBGA (PLASTIC BGA) CONSTRUCTION ..................................................................... 3
2.2 TE-PBGA (THERMALLY ENHANCED BGA) CONSTRUCTION ............................................ 4
2.3 EBGA (ENHANCED BGA) CONSTRUCTION ................................................................. 5
2.4 TSBGA (TAPE SUPER BGA) CONSTRUCTION .............................................................. 5
2.5 PACKAGE ELECTRICAL PERFORMANCE ................................................................... 7
3 Component Reliability ...................................................................................................... 7
4 Package Handling/Shipping Media ....................................................................................... 8
5 Design Recommendations ................................................................................................. 8
5.1 SOLDER PAD GEOMETRY ...................................................................................... 8
5.2 NSMD vs. SMD LAND PATTERN ............................................................................... 8
5.3 ESCAPE ROUTING GUIDELINES .............................................................................. 8
6 Assembly Recommendations ............................................................................................ 10
6.1 PROCESS FLOW & SET-UP RECOMMENDATION ........................................................ 10
6.2 PCB PLATING RECOMMENDATIONS ....................................................................... 11
6.3 SOLDER PASTE PRINTING .................................................................................... 11
6.4 PASTE RECOMMENDATIONS ................................................................................ 11
6.5 COMPONENT PLACEMENT ................................................................................... 11
6.6 REFLOW .......................................................................................................... 12
6.7 SOLDER JOINT INSPECTION ................................................................................. 13
6.8 REPLACEMENT AND REWORK .............................................................................. 14
6.9 SITE PREPARATION ............................................................................................ 14
6.10 COMPONENT PLACEMENT ................................................................................... 14
6.11 COMPONENT REFLOW ........................................................................................ 14
List of Figures
1 PBGA, TE-PBGA , EBGA and TSBGA .................................................................................. 3
2 Cross-Sectional View of 2 and 4 Layer PBGA .......................................................................... 4
3 Cross-Sectional View of 4 Layer TE-PBGA ............................................................................. 5
4 Cross-Sectional View of EBGA ........................................................................................... 5
5 Cross-Sectional View of TSBGA Packages ............................................................................. 6
6 Typical Process Flow ....................................................................................................... 7
7 NSMD and SMD Pad Definition ........................................................................................... 8
8 P = Pad Pitch D = Pad Diameter L = Line Width S = Line Space .................................................... 9
9 Routing for Four Rows of Solder Balls ................................................................................... 9
10 Routing for Five Rows of Solder Balls .................................................................................. 10
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List of Tables
1 Guidelines for PCB Pad Design........................................................................................... 8
2 Recommended Number of Routing Lines Between Adjacent PCB Solder Pads ................................... 9
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Copyright © 2004, Texas Instruments Incorporated
www.ti.com Introduction
1 Introduction
Leaders in the consumer electronics industry will be determined by their ability to deliver increasingly
miniaturized products at lower costs. The Ball Grid Array (BGA) package achieves these objectives by
providing increased functionality for the same package size while being compatible with existing Surface
Mount Technology (SMT) infrastructure.
Some of the other benefits of using BGA packages over similar lead count packages include:
1. Efficient use of board space.
2. Improved thermal and electrical performance. BGAs can offer power and ground planes for low
inductances and controlled impedance traces for signals.
3. Improved surface mount yields compared to similar fine pitch leaded packages.
4. Reduced package thickness.
5. Potentially lower cost of ownership compared to leaded packages by virtue of their reworkability.
This application note provides general information about Plastic Ball Grid Array (PBGA) packages, and it's
variants - the TE-PBGA (Thermally Enhanced BGA), EBGA (Enhanced BGA) and TSBGA (Tape Super
BGA). Information on FBGA (Fine Pitch BGA) and LBGA (Low Profile BGA) packages can be found in
National Semiconductor's Laminate CSP application note (AN 1125). Figure 1.
PBGA 35 mm TE-PBGA 40 mm
EBGA 35 mm TSBGA 40 mm
2 Package Overview
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Solder mask is applied on both sides over the copper pattern to ensure that all the substrate vias are
completely tented.
Four layer substrates are available for applications requiring power or ground planes (they also provide
additional routing flexibility). For thermal applications, the inner layers can be clad with thicker (2 oz)
copper (~ 70 μm).
The IC is attached on the top side of the substrate using die attach. The chip is then gold wire-bonded to
bondfingers on the substrate. Traces from the bondfingers transfer the signals to vias that then carry them
to the bottom of the substrate and finally to circular solder pads on the same side.
The bottom side solder pads are laid out in a square or rectangular grid format with a pitch recommended
by JEDEC registration standards (MO-151) for PBGAs.
The part is then over-molded to completely encapsulate the chip, wires and substrate bondfingers.
Figure 6 shows the typical process flow for cavity up and cavity down assembly.
2 Layer PBGA
4 Layer PBGA
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In the I-Metal-I-Plane structure, the ground solder ball pads are formed by punching out vias in the tape,
Figure 5. The heat spreader is exposed on the punched openings. The punched vias are filled with solder,
connecting the ground solder balls directly to the heat spreader. All ground bond pads on the die are
bonded to a ring on the heat spreader. This provides a low inductance ground plane and a good return
path for signal traces, with controlled impedances. Thus, the I-Metal-I-Plane package offers better
electrical performance than a I-Metal package. Assembly process steps are identical to the I-Metal
package, except for the two stage solder ball attach process.
For cavity down packages (TSBGA,EBGA) with ball pitch ≤ 1mm, the PCB warpage must be carefully
controlled and it is recommended that PCB warpage under the package is < 4 mils.
I-Metal TSBGA
I-Metal-I-Plane TSBGA
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www.ti.com Component Reliability
3 Component Reliability
All BGA packages are qualified to JEDEC MSL Level 3 at 220° C reflow conditions. All packaged devices
pass 1000 hrs, THBT (85°C / 85%RH / Biased Testing) , 1500 TMCL (−40 to 125° C), 96 hrs ACLV (121°
C / 100%RH), 1000 hrs HTSL (150° C) and 1000 hrs DOPL (125° C).
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5 Design Recommendations
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For NSMD pads, exposure of underlying copper traces is forbidden, so the diameter and tolerance of the
solder mask opening define D.
The number of routing lines as a function of pad pitch for various PCB line space/width geometries is
shown in Table 2. Routing assumes a four-layer board (2 signal and 2 ground) with NSMD pads on the
PCB.
Table 2. Recommended Number of Routing Lines Between Adjacent PCB Solder Pads
Ball pitch 1.27 mm Ball pitch 1.00 mm
L/S = 0.15 mm 1 N/A
L/S = 0.125 mm 1 1
L/S = 0.10 mm 2 1
Either a 1.0 or 1.27 mm pitch PBGA with four rows of solder balls can be routed to a four layer PCB
(Figure 9) using a 0.15 mm (6 mils) or 0.125 (5 mils) line/space respectively. The first two ball rows can be
routed to one signal layer while the third and fourth ball rows can be routed to a second signal layer.
Routing becomes more complicated for a four-layer board, if there are five rows of solder balls. For
example, for a 1.27 mm ball pitch PBGA, a 0.125 mm (5 mil) PCB line/space design will be necessary for
routing (Figure 10) with a 0.8:1 ratio of PCB pad to package pad. A 1.0 mm PBGA will require a 0.10 mm
(4 mil) line/space with a 0.8: 1 PCB pad to package pad ratio, to successfully route 5 rows of solder balls
to a four-layer PCB (Figure 11). For both packages, the first three ball rows are routed to one signal layer
while the fourth and fifth ball rows are routed to the second signal layer.
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6 Assembly Recommendations
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Standard pick and place equipment can place these components within the required degree of accuracy.
6.6 REFLOW
The BGA may be assembled using standard IR or IR convection SMT reflow processes. As with other
packages, the thermal profile for specific board locations must be determined. The BGA is qualified for up
to three reflow cycles at 225° C peak (J-STD-020). The actual temperature used in the reflow oven is a
function of:
• Board density
• Board geometries
• Component location on the board
• Size of surrounding components
• Component mass
• Furnace loading
• Board finish
• Solder paste types
It is recommended that the temperature profile be validated at the ball location of the BGA as well as
several other locations on the PCB surface.
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Convection / IR
Maximum 3 °C/sec
(1)
Ramp Up °C/sec Recommended 1 °C/sec (2)
(2)
Minimum
(2)
Maximum
Dwell Time 120° C to 160° C (1) Recommended 130 seconds
(2)
Minimum
(2)
Maximum
Dwell Time 160° C to 183° C (1) Recommended 35 seconds
(2)
Minimum
Maximum 85 seconds
Dwell Time ≥ 183° C (1) Recommended 50 seconds (2)
(2)
Minimum
(2)
Maximum 225° C
(1) (2)
Peak Temperature Recommended 220° C
Minimum
Maximum 10 seconds
Dwell Time Max. (within 5° C of peak
Recommended 5 seconds
temperature)
(2)
Minimum 1 second
Maximum 4 °C/sec
Ramp Down °C/sec(1) Recommended 2 °C/sec
(2)
Minimum
(1)
Will vary depending on board density, geometry, package types, PCB finish, and solder paste types.
(2)
All Temperatures are measured on the solder joint.
Figure 13. General Reflow Profile Guidelines for PBGA & EBGA
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