k-way b-bit Multiplexer
There should be log k selectors to a k-way multiplexer. We’re using a log k-to-k decoder to build
a single MUX. The following diagram represent the architecture of a k-way 1-bit MUX.
Data k
k
k
log k
log k-to-k Decoder
(Note- there is an independent AND gate for each k line)
To build a b-bit MUX, we should fix b number of 1-bit MUX together.
k
k-way 1-bit MUX
k
k-way 1-bit MUX
...
k
k-way 1-bit MUX
As for this processor, we’re required to design the following multiplexers.
1. 2-way 3-bit multiplexer
2. 2-way 4-bit multiplexer
3. 8-way 4-bit multiplexer
The above procedure is applicable for all three multiplexers. Only the numerical values differ.
Multiplexer Function
2-way 3-bit multiplexer Selects the address to be jumped or the next address. This address
will be later carried to the program counter.
2-way 4-bit multiplexer Selects the immediate value or output value of the adder. This
value will be later carried to the register bank.
8-way 4-bit multiplexer Selects the correct register and drive it to the adder.
Let us consider the schematics of the 2-way 3-bit MUX only. The latter have the same
schematics as below.