HIGH GAIN TRANSFORMER-LESS

BOOST CONVERTER FOR

SMALL POWER GENRATORS
Abstract— Renewable energy sources the solutions for overcoming this is the
including photovoltaic cells, fuel cells, and distributed generation system using renewable
wind turbines require converters with high energy sources like solar, wind or hydro,
voltage gain in order to interface with power having the advantage that the power is
transmission and distribution networks. produced in close proximity to where it is
These conversions are conventionally made consumed. Among renewable energy systems,
using bulky, complex, and costly photovoltaic systems are expected an important
transformers. Nowadays, converters with a role in future energy production, because it is a
high voltage gain which do not require a clean, emission-free, and renewable electrical
transformer, coupled inductors, or extreme generation source with high reliability.
[4]
duty cycle values are highly desirable given Renewable energy sources cannot directly
the quick penetration of low-voltage power support the ac or dc electrical appliances
generating sources. This paper proposes a because the voltage provided by renewable s is
boost dc-dc converter topology with the usually low in amplitude. Consequently, a step-
novel capability of cancelling the input up converter is required to provide high voltage
current ripple at an arbitrarily preselected gain. High gain DC/DC converters are the key
duty cycle with high voltage gain without part of renewable energy systems. Another
utilizing extreme values of duty cycle or important requirement for a converter in
boosting transformers. Simulations are used renewable energy applications is to drain a
to verify the modelling approach and predict continuous current with minimum ripple.
the performance at different power levels. Therefore converters combining these two
The converter was validated in the features are expected to find many applications
laboratory through the construction of within the renewable-energy contact.
hardware prototype. The recent emerging technology
Key Words-DC–DC converter, high-voltage requires dc-to-dc converters with a steep
gain, low-voltage power generating sources, voltage ratio ,basically there are two types of
input current ripple cancellation. topology dc-dc converter present, one is
transformer less topology and other one is with
transformer. According to the efficiency, the
I. INTRODUCTION transformer less topology is better than with
transformer topology. High voltage gain dc–dc
Global energy consumption tends to boost converters play more and more important
grow continuously. To satisfy the demand for role in many industry applications such as
electric power against a background of the uninterrupted power supplies, electric traction,
depletion of conventional, fossil resources the distributed photovoltaic (PV) generation
renewable energy sources are becoming more systems, fuel cell energy conversion systems,
popular. The rapid increase in the demand for automobile HID headlamps, and some medical
electricity and the recent change in the equipments. In these applications, a classical
environmental conditions such as global boost converter is normally used, but the
warming led to a need for a new source of voltage stress of the main switch is equal to the
energy that is cheaper and sustainable. One of high output voltage; hence, a high-voltage
rating switch with high on-resistance should be large current spikes. Here the converter does
used, generating high conduction losses. In not require transformers or coupled inductors
addition, an extremely high duty cycle will and is intended to be used along with fast-
results in large conduction losses on the power switching power semiconductors.
device and serious reverse recovery problems.
As a result, the conventional boost converter
would not be acceptable for realizing high step-
up voltage gain along with high efficiency.

The major challenge of designing a

boost converter for high power application is
how to handle the high current at the input and
high voltage at the output.. In boost converter
designs, the input current-ripple is required to
be a small percentage of the input dc current. It
is well known that the current ripple is smaller
as the input inductor becomes larger. Another Figure.1 Circuit Diagram of proposed topology
possibility to reduce the converter’s input
current ripple is given by the interleaving The proposed converter contains two
structures. The interleaving technique connects transistors (s1 and s2), three diodes (d1, d2, and
the converter in parallel to share the power d3), three capacitors (C1, C2, and C3), two
flow, to reduce the size, weight, and volume of inductors for energy storage (L1 and L2), and a
the inductors and capacitors. The interleaving small inductor (L3) for current limiting through
of SC circuits has also been proposed as a diode d3. In practical implementation, L3 is
solution for high voltage gain. The presented around 100 times smaller than L2 and 50 times
converter does not require transformers or smaller than L1. As a result of its reduced size,
coupled inductors and is intended to be used small-ripple approximations do not apply to L3,
along with fast-switching power and hence, the selection of its inductance is
semiconductors. Also, the topology presented based on the complete charge interchange
herein is able to cancel the input current ripple, between C2 and C3. A fast switching device,
and are highly desirable given the quick like a MOSFET, is used with reduced on
penetration of low voltage power generating resistance to minimize conduction loss, and
sources. also it provides fast dynamic control over
II. HIGH GAIN TRANSFORMER-LESS switch duty ratio to maintain the desired output
BOOST CONVERTER WITH INPUT voltage.
CURRENT RIPLLE CANCELLATION
The converter has two equivalent
Fig.1 shows a proposed topology for circuits resulting from the switch action. The
transformer-less boost converter with high- transistors switches are complementarily, i.e.,
voltage gain. Which combines two principles when S1is closed, S2is open and vice versa.
highly used in state of- the-art power Switching state 1 corresponds to the condition
converters: 1) At the converter’s input, two when S1is closed, S2is open and switching state
inductors are interleaved for cancelling the 2 corresponds to the condition when S2is
input current ripple, and 2) at the converter’s closed, S1is open. . When S1is on (and S2is off),
output, an SC voltage multiplier is utilized to the topology is represented by the equivalent
increase the voltage gain. The SC stage has circuit in Fig.2.
been improved by using a small resonant
inductor to limit the peak current resulting from
the switching process and hence preventing
Fig.2 Equivalent circuits when 𝑆1 is on
Fig.4 Waveforms of input current, Current
During this time, the diode d1 and d3 is through input inductors, and Switching
reversely biased, blocking the voltage across C1 sequence.
and C3. The current through L2forces the diode
d2to be closed since transistor S2is open. The The converter’s input current corresponds to
current through L1rises with a slope of Vin/L1, the sum of the currents through L1and L2. Since
and L2 discharges at a rate of (Vin–Vc2)/L2. L1and L2 charge/discharge in a complementary
While 𝑆2 is on (and 𝑆1 is off), the resulting manner, size of the two inductors is chosen
equivalent circuit is as shown in Fig.3. such that the input current is ripple free for a
selected value of the converter’s duty cycle.
The current waveforms shown in Fig.4
correspond to a converter that features a zero
input current ripple at a duty cycle of D= 75%.
This is possible if both inductors are charged
with the same voltage and L2=3L1 .
III.SYSTEM ANALYSIS AND SELECTION
OF COMPONENTS.

The proposed topology is an interleaving-

type converter and it features a small inductor
Fig.3 Equivalent circuits when 𝑆2 is on for peak current limiting which has no effect on
the basic operation of the converter for power
The capacitors 𝐶2 and 𝐶3 are connected transfer. In addition, the interleaving of two
in parallel, leading to SC-type behavior. As a inductors allows current ripple cancelation at
result of this, a small inductor (𝐿3) is needed in an arbitrary preselected duty cycle.
order to limit the peak current around this loop. Furthermore, the switch count is reduced to
During this time, the 𝐿1 discharges with a slope two, and as a result, the converter is controlled
that is equal to (𝑣𝑖𝑛−𝑣𝐶1) /𝐿1 , while 𝐿2 charges by a single duty cycle.
at a rate of 𝑣𝑖𝑛 /𝐿2 . When S2is conducting, the A. Voltage Gain Analysis.
capacitors C2and C3are connected in parallel,
The dynamics of L1, L2, and C1 may be
leading to an SC-type behavior. As a result of conveniently analyzed considering their
this, a small inductor (L3) is needed in order to
average behavior, On the other hand, C2, C3,
limit the peak current around this loop. A and L3form an SC circuit, and therefore, their
typical waveform for the current through L1and
dynamic behavior has to be formulated with
L2, the input current, and the switching additional considerations. However, a number
sequence for S1and S2 is as shown in Figure.4.
of the converter’s features can be explained
focusing on L1, L2, and C1, where dynamic In steady state, the average current through
averaging applies. Under this assumption, C1 must be equal to zero, which leads to the
switching functions may be readily replaced by following expressions for the current through
their corresponding duty cycles. For the L1,
analysis hereinafter, the converter’s duty ratio 1 Vc 1+ Vc 3
d(t) is defined as percentage of time over the IL1 = ¿ ¿
D R
switching period that the switch s2 is on, i.e. (9)
t +T s
1 As C2 and C3 form an SC circuit, average
d (t)= ∫ q2 (τ )d τ (1)
dynamic equations do not apply. However, the
Ts t
steady-state current through L2 can be
Where TS is the switching period and q2 is computed by input/output power balance
the switching function of s2 that is equal one considerations and it is given us,
while s2 is closed and zero otherwise. Under 1 Vc 1+ Vc 3
IL2 = ¿ ¿
this assumption and neglecting for now the 1−D R
inductors’ equivalent series resistance (ESR), (10)
the equations that represent the average From Fig. 1, the output voltage is
dynamics for inductors L1 and L2 are,
VO = Vc1+Vc3. (11)
Thus, combining (4),(5) and (9)–(11), the
di L 1
L1 =d ( v ∈−v c 1 ) + ( 1−d ) ¿ (2) converter gain becomes,
dt 1
Vo =
di L 2 ¿¿ (1−D) D
L2 =d ¿ (3) (12)
dt The plot of the above voltage gain as a
In steady state, the average voltage function of the duty cycle is shown in Fig.5.
across the inductors must be equal to zero, thus
the steady state voltage across C1 and C2 may
be expressed as,
1
V C 1= Vin
D
(4)
1
V C 2= Vin
1-D
(5)
The voltages across C1and C2are proportional to
one another, i.e.
1−D
V C 1= VC2 Fig.5 Voltage Gain vs. Duty Cycle
D
(6)
According to Fig.5 and expression
D
V C 2= V (12), the minimum voltage gain is 4 and it is
1−D C 1 obtained when the duty cycle is equal to 0.5. If
(7) the duty cycle is larger than 0.5 the gain
The average dynamic current equation for C1is increases again, but the operating point of the
given by, duty cycle is selected higher than 0.5.
dv c 1 v c 1+ v c 3 Capacitors C2 and C3 work in an SC
C1 = diL1 –
dt R way because C2 clamps the voltage across C3
(8) while the switch s2 is closed. In steady state, C2
and C3 feature the same average voltage. i.e.
VC2 = VC3 (13) The converter’s practical gain is obtained by
The gain expressed by (12) corresponds to an adding (18) and (21),
ideal case as the inductor’s ESR has been V0 1 1
neglected. In a practical implementation, the = +
V in R L1 R L2
leakage resistance in inductors greatly limits D+ ( 1−D ) +
this gain. So rewriting (9) and (10) using (6) D ( 1−D ) R D ( 1−D ) R
and (7) and (11). (22)
D 1 V c1 The proposed topology sizes the inductor’s to
IL1 = (1+ ) cancel the input current ripple at a given duty
1−D D R
ratio. For example, if L2=3L1, the input current
(14) is ripple free at D= 75%. As a first
1−D 1 V c2 approximation, it may be assumed that the
IL2 = (1+ ) inductor’s ESRs follow the same trend, i.e.,
D 1−D R
RL2= 3RL1. Fig.6. shows the converter’s voltage
(15)
gain under this assumption for different values
By including the ESR of L1, (2) becomes,
of the ratio between the load resistance Rand
diL1
L1 =d ( v in −R L1 iL1 −v C 1 ) + (1−d ) ( v in −R L1 iL1 ) RL2. The figure is readily obtained by plotting
dt equation (22). According to the Fig.6, the
(16) minimum voltage gain is four and occurs at D=
Where RL1 is the ESR resistance of L1. In 50%. If the duty cycle is smaller than 50%, the
steady state, (16) becomes, gain increases again, and therefore, the
0= D (Vin – RL1IL1 – VC1) + (1-D) (Vin – RL1IL1) minimum gain that the converter can operate is
around four. Here the operating range for the
= Vin – RL1IL1 – DVC1 (17)
proposed topology is selected to be at D > 50%,
By substituting (14) in (17), the ratio between
which ensures that L3will have enough time to
the voltage across C1 and the input voltage
discharge.
becomes ,
V C1 1
=
Vin R L1
D+
D ( 1−D ) R
(18)
Similarly, the inclusion of the ESR in L2 (RL2)
leads to rewriting (3) as,
diL 2
L2 =d ( v in−R L2 i L2 ) + (1−d ) ( v in −R L2 i L2 −v C 2 )
dt (
19)
This, in steady state, becomes
0= D(Vin − RL2IL2) + (1 − D)(Vin − RL2I= − VC2)
= Vin − RL2IL2 − (1 − D) VC2 (20) Fig.6 Voltage gain vs. Duty cycle considering the
inductor’s ESR
Moreover, substituting (15) in (20), the ratio
between the voltage across C2 and the input
The selection of the inductors has to be such
voltage becomes,
that L2 >L1, in order to achieve ripple
VC2 1 cancelation for the input current. Also, L2
=
V in R L2 >L1implies that RL2 >RL1, and thus, larger
( 1−D )+ voltage gains are obtained for D <10%, which
D ( 1−D ) R
can be observed in Fig. 6.2. The figure also
(21)
suggests that, as in most dc/dc converter’s
topologies, the inductor’s ESR limits the dependence of the input current ripple with
practical gain of the approach. Therefore, this respect to the value of the duty cycle is shown
topology is more suitable if a large switching in Fig.8
frequency is employed as, in that case, reactive
components and, hence, ESRs are very small.

B. Energy Storage Inductor Sizing

The current ripple on the inductor L1 and

L2is given by,
V in 1−D
Δi L1 =
L1 F S( )
(23)
V in D
Δi L2 = Fig.8
L2 F S
Input current ripples vs. Duty cycle
(24)
Where D is the duty cycle, Fs is the switching Here the current ripple is given in
frequency, FS=1/TS is the converter’s switching amperes (not in percentage).If the converter
frequency. The input current ripple, denoted by duty cycle is set to 0.6 (inductors are calculated
Δiin, corresponds to the difference between each for having a zero ripple at D=0.75) then the
inductor’s current ripples, i.e, current ripple would be 0.2 times Vin/(fSL2).
V in D ( 1−D )
Δ in=
(
F S L2
−
L1 ) C. Peak-current limiting inductor sizing
(25) During the switching state when S2ON,
As it is evident from (25), the input current the diode d3 connects the capacitors C2 and C3 in
ripple can be eliminated by zeroing out the left- parallel, and as a result, a peak-current-limiting
hand side of this equation. This leads to the inductor is needed. It is evident from Fig.1, tha
following relationship, the average current through the diode equals
D the load current. However, the shape of the
L2=L1
1−D (26) current through d3 may be undesirable and,
For example, if the expected input and output hence, it is needed to be controlled. Consider
voltages are such that the duty cycle is equal to the switching process at the time when S2 turns
75%, by sizing L1 = 3L2, the input current ripple off, at that instant, C2 and C3 feature exactly the
is eliminated. Once the values of L1 and L2 are same voltage because they were connected in
selected, (25) may be used to predict the input parallel. Taking this voltage as VC0. After s2
current ripple for the full operating range. Thus, opens, C2 and C3 are no longer connected.
if L1 = 3L2, (25) becomes, While s2 is off (during (1 − D) TS seconds), C3
discharges following the load current while C2
V in 4
Δ in=
F S L1 3(D−1 ) (27)
charges following the current through L2. Call
V C2:1 and V C3:1 the final voltages across
It is clear from (27) that there is a capacitors C2 and C3, respectively. They can be
linear dependence of the input current ripple expressed as,
with respect to the value of the duty cycle, and
the assumption of ripple-free input current
becomes weaker as the operating point departs
from the selected duty ratio. a linear
 I L2
V C 2. 1 =V C 0 +Δv C2 =V C 0 + ( 1−D ) T S
C2
(28)

I0
V C 3. 1 =V C 0− ΔvC 3 =V C 0 − ( 1−D ) T S
C3 (29)
The voltage difference between them is given
by,

I L2 I 0
V diff = Δv C 2 −ΔvC 3 =
( +
C2 C3 )
( 1−D ) T S
Fig.10 Waveforms for the reactive component
(30) selection
Therefore if there is no inductor in series with As shown in Figure 4.9, this current
d3, the peak current would be Vdiff over the rises rapidly and may destroy power
resistance in this loop, given by the ON-state semiconductors if the inductor L3 is not
resistance of S2and d3, and the ESR of C2and properly designed. From Figure 4.8, it is also
C3.The equivalent circuit schematic for the evident that Ceq is the series connection of C2
current loop is as shown in Fig.9.Waveforms and C3. Since L3 stores a small amount of
for the reactive component selection is shown energy, it charges and discharges completely in
in Fig.10. Here Reqstands for the lumped a switching cycle, smoothing out the current
resistance of the various elements around the among capacitors.
loop which can lead to a peak current that However, it also produces a resonant current
overpasses the peak current limit of the various peak at a frequency of,
devices in that loop. Ceqis the series connection w0 1
of C2 andC3. The inductor Ld3 is necessary if the f 0= =
current overpasses the peak current limit of the 2 π 2 π √ L3 C eq
(31)
devices. For the converter to operate at a duty cycle
larger than 50%, L3should be selected such that
f0 >FS. This ensures that the inductor will
complete the discharge process before the
beginning of the next switching stage for
all values of the duty cycle within the
operating range.At the beginning of the
charging period, the current starts rising at a
rate of Vdiff/L3 as shown in Fig.10. Therefore,
representing the current through the loop as
Fig.9 Equivalent Circuit Schematics iL3(t) = ˆιL3sin(ω0t), its derivative at t = 0 can be
computed and equated to Vdiff/L3. Hence
obtaining solution for ˆιL3as,

¿ V diff
iL 3 =
w 0 Ld 3 (32)

D. Capacitor Sizing
The procedure for the selection of the large step-up voltage conversion from low
capacitance for C1, C2, and C3 is same as to that voltage obtained from the panel low voltage to
used in the sizing of the inductors L1 and L2. the required voltage level for the application.
When S1is on, the current through C1follows Typically, several PV panels are
the load current and capacitor C2 charges connected in series to provide a high-voltage
following the current through L2.Hence voltage output. Individual maximum power point
across C1 and C2 is given by the expressions, tracking (MPPT) converters are attached to
I0 each PV panel for extracting its maximum
Δv C 1 = ( 1−D ) T S power. Such a PV module composed of a PV
C1 (33) panel with an individual dc–ac inverter is called
I a solar micro inverter. Fig.11. shows the
Δv C 2 = L 2 ( 1−D ) T S conventional two-stage solar micro inverter that
C2 consists of an isolated dc–dc converter and a
(34) grid-tied dc–ac inverter.
Finally, C3 may be selected recognizing that L3
carries the same average current as the load.
When the instantaneous value of current
through this inductor overpasses the output
current, the capacitor C3 begins charging,
which leads to a voltage increase ΔVC3 given by
Δq/C3. This is graphically shown in Fig.10,
where the shaded area represents the charge Δq.
After L3 has been selected, the time while C3 is
charging can be computed by finding the time
at which i0 < iL3(t).C3 discharges through the
remaining of the switching period, and hence
the time duration for which C3discharges can be Fig.11 Conventional two-stage isolated solar
computed as, micro inverter
Conventional solar micro inverter uses a Dc-
i
T dis =T S −
( 1 2
( ))
− arcsin 0
2 f 0 w0 iL 3
Dc converter with transformer. This will make
the switching frequency limitation in power
converters to become a transformer issue, since
(35)
transformers increase their losses when the
During this time, C3follows the load current,
frequency is too high. So the proposed
and thus the sizing of C3 is possible using the
transformer-less high gain boost converter can
relation
be utilised instead of conventional boost
I0 converter. Hence, using transformer-less high
Δv C 3 = T
C3 dis (36)
gain boost converter allows a solar micro
inverter circuit to be small, low cost, and high
efficient converter. A solar micro inverter with
IV. SOLAR MICRO INVERTER transformer-less high gain boost converter is
shown in Fig.12.
In case if the voltage derived from the
PV panel is lower, then it is difficult for the ac
module to reach the high efficiency. However
employing a high step-up DC-DC converter in
front of the inverter, which improves the power
conversion efficiency from one level to another
level and it also provides the stable DC link to
the inverter. The DC-DC converter requires a
Fig.12 Solar micro inverter with transformer- Fig.13 Simulation diagram
less high gain boost converter
A 15V DC input is supplied to the a
The pre stage dc–dc converter releases converter and it gives a boosted output
the maximum solar energy from a PV panel voltage(80V).
and provides a high voltage dc bus for the post
stage dc–ac inverter that converts the dc
voltage to a sinusoidal ac output voltage and
connects with the ac grid system.
V. SIMULATION RESULTS
A transformer-less high gain boost converter
is simulation is done using Mat lab and the
results are presented. Simulation of the
proposed topology was carried out according to Fig. 14 Input Voltage Waveform
the values of table.1
Table 1 Parameters for MATLAB simulation
Parameter Value
Input Voltage 15V
Duty Cycle 70%
Output Voltage 71V
L2 330µH
L2 140µH
C1,C2,C3 10µF
MOSFETS IRFP4668PBF
Diodes MBR40250G
FS 25khz
The simulation diagram of transformer-less
boost converter topology is shown in Fig. 13.
 Fig.18 capacitor voltages (Vc1, Vc2, and Vc3)
VI. EXPERIMENTAL RESULTS

The hardware prototype of

Transformer-less high gain boost converter has
been implemented in the laboratory in order to
Fig.15 Converter output current and voltage validate its principle of operation and certain
Fig.16 Current Waveforms Iin, IL1, IL2 measurements were made including, the input
and output voltages, the input current ripple
cancellation and the switch voltages.5V power
supply is given to the PIC microcontroller for
generating the gating signals to the MOSFET.
The gating signals are given to the MOSFET
through MOSFET driver. The converter is
supplied with 12V DC supply and got an output
of 84V DC

Fig.17. Inductor (L3) Current Waveform, IL3

Fig.19 Experimental Setup

 Fig.23 Input current ripple cancellation
Fig.20 Output signal of the PIC microcontroller

V.CONCLUSION
Renewable energy sources such as
photovoltaic cells, fuel cells, and wind turbines
show great promise in meeting worldwide
energy demand in the face of increasing
pressures on conventional fossil fuels. These
applications require large step-up ratios and
high efficiencies that are beyond the capability
of conventional converters. Converters with
large step-up ratios that eliminate transformers
enable reductions in cost, bulk, and complexity.
Fig.21 Output Signal of MOSFET Driver This research identified a need for efficient
high step-up converters with the novel
capability of cancelling the input current ripple
at an arbitrarily preselected duty cycle in small
power generating systems. This is
accomplished without increasing the count of
the number of components. Two interleaved
inductors at the input and SC voltage
multipliers at the output are integrated in the
proposed converter. In addition, the converter
features a high voltage gain without utilizing
extreme values of duty cycle or boosting
transformers. These features make the
converter ideal to process electric power
coming from low-voltage power-generating
sources, such as renewable. The converter was
validated in the laboratory through the
construction of a hardware prototype. The
Fig.22 Output Voltage Waveform experimental results show that high step-up
voltage gain is achieved. Simulation results are
consistent with the analytical predictions of the Power Electron., vol. 26, no. 4, pp. 1146–
various formulas developed through this paper, 1153, Apr. 2011
and hence, the approach may be considered [6] Y. P. Hsieh, J. F. Chen, T. J. Liang, and L.
definitely validated. S. Yang, “Novel high step-up DC–DC
converter with coupled-inductor and
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