EPM240-MINI:

VOTING SYSTEM

Prepared by,
Siti Nursyuhada binti Mahsahirun
ct_nursyuhada@ymail.com

Verified by,
Zulkifli Md. Yusof
Faculty of Manufacturing
Universiti Malaysia Pahang
zmdyusof@ump.edu.my
1. LEARNING OUTCOME
This tutorial is aimed to deliver a very basic digital system design experience on an actual PLD
(programmable logic device) for undergraduate mechatronics program in FKP.

At the end of this tutorial, student should be able to:

i. start a new project in QuartusII software
ii. perform design entry using schematic diagram
iii. perform functional verification and timing simulation using university program VWF
iv. perform hardware verification on EPM240 Mini CPLD development board

2. REQUIREMENT
i. Personal computer with QuartusII software
ii. EPM240 Mini CPLD board

3. INTRODUCTION
3.1. SOFTWARE

QuartusII is one of the software that can be used for a digital system design and development. It was introduced
by Altera and widely used to facilitate system on IC or embedded system development. The tasks are mainly
involving simulation and verification process. The designed model are simulated for functional and timing
verification on Quartus II before integrated with the actual ALTERA devices for hardware verification.

The free version of Quartus II can be downloaded from Intel FPGA website at the following URL:
https://www.altera.com/downloads/download-center.html

In this tutorial, Quartus II 13.0 Web Edition will be used. This software supports both 32-bits and 64-bits operating
system as well as the DE-0 Nano FPGA board. Users may also use other version that meet their system requirement
and the targeting ALTERA device.

3.2. HARDWARE

PLDs are devices that can be programmed to perform Boolean operation. In contrast with microcontroller and
microprocessor, PLDs are not programed with a list of instruction but internally configure by electronically

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connecting and disconnecting nodes in the circuit. This gives PLDs an advantage to perform much faster than most
commonly used microcontroller and microprocessor.

There are several types of PLDs, those can be classified under SPLD, CPLD and FPGA. The SPLD and CPLD is
often described in contrast by the key word ‘simple’ and ‘complex’. SPLD comprises array of AND, OR and NOT
logic gate while CPLD comprises the array of logic gate blocks.

CPLDs and FPGAs are almost the same in terms of general architecture and working mechanism. Despite the
similarity, both devices are usually different by the elements constructing the logic blocks and the number of logic
blocks. FPGA are mostly used in IC development that merely associated with VLSI and the above scale in research
and development field. On the other hand, CPLD is merely associated with VLSI and the below scale.

In this tutorial, we will use EPM240 Mini board for real hardware implementation. This development board
implement CPLD as the core processing unit.

The EM240 Mini is a minimum development board that utilized Altera MAXII EPM240T100C5N CPLD. It
requires JTAG, clocking and voltage regulator bootstrapping components to allow the CPLD to be programmable
through QuartusII. The schematics diagram of this board is available in open sources.

18 PINS
JTAC GPIO
CONNECTOR

5V POWER MAXII CPLD

PORT EPM240T100C5N

POWER 18 PINS
INDICATOR GPIO

FIGURE 1: Top view

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There are a hundred of general input/output pins that can be utilized for this tutorial. Those are accessible through
the two (2) units of 22  2 headers. As shown in FIGURE 1.

50MHz
AMS1117 OSCILLATOR

FIGURE 2: Bottom view

The board implement 50MHz oscillator and AMS1117 3.3V voltage regulator circuit to provide 3.3V Vcc

3.3. PROBLEM DESCRIPTION

Design a combinational logic circuit that shows the results for three people who votes. The three people who votes
are labeled as A, B, and C. If two out of the three people or all of them vote for a particular event, then the output
of the circuit becomes HIGH. Else if one or none of them votes. The output becomes LOW.

There are several possible Boolean equations that can be derived. The following shows one of possible equation
for the voting system. The truth table of the problem description are given in TABLE 1.

TABLE 1: Truth table for the voting problem

Input Output
A B C V
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

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 From the truth table,
SOP;
𝑉 = 𝐴̅𝐵𝐶 + 𝐴𝐵̅𝐶 + 𝐴𝐵𝐶̅ + 𝐴𝐵𝐶

Simplifying equation by factorizing all expressions with ABC,

𝑉 = 𝐴̅𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵̅𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶̅ + 𝐴𝐵𝐶
= 𝐵𝐶(𝐴̅ + 𝐴) + 𝐴𝐶(𝐵̅ + 𝐵) + 𝐴𝐵(𝐶̅ + 𝐶)
= 𝐵𝐶 + 𝐴𝐶 + 𝐴𝐵

Therefore,
𝑉 = 𝐵𝐶 + 𝐴𝐶 + 𝐴𝐵

4. INSTRUCTIONS
4.1. New Project

1. Execute Quartus II software

2. Click File > New Project Wizard. This will brings us to the introduction page as shown in FIGURE 3

FIGURE 3: New project wizard introduction

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3. Click Next. This will brings us to page 1. Enter the working directory, name and top-level entity for this
project as shown in FIGURE 4. We may also use other working directory at our convenience

What is the working directory for the project?

C:/altera/13.0/project/project2
What is the name of the project?
Voting
What is the top-level design entity for the project?
Voting

FIGURE 4: New project wizard page 1 of 5

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4. Click Next. Page 2 should appear as shown in FIGURE 5. This page is used if we want to add any prior
file, we will skip this part

FIGURE 5: New project wizard page 2 of 5

5. Click Next. We should see page 3 as shown in FIGURE 6. Here, select the device model corresponding
to DE0-Nano FPGA development board

Device family : MAX II

Device : EPM240T100C5N

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 FIGURE 6: New project wizard page 2 of 5

6. Click Next. We should come to page 4 as shown in FIGURE 7. Here, we will not using any third party
software. Therefore, select ‘None’ for all tasks

FIGURE 7: New project wizard page 4 of 5

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7. Click Next. We should come to Summary page. Make sure the details are similar to as shown in
FIGURE 8

FIGURE 8: Summary of the newly created Voting project

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 8. Click Next. We are done with creating new project. Notice the voting entity as shown in FIGURE 9

Project
navigator

Tasks

Workspace

Messages

FIGURE 9: Default layout of Quartus II

4.2. Schematic Entry

1. Go to File > New. A new dialog box pops up as shown in FIGURE 10

FIGURE 10: Adding New File dialog box

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2. Go to Design Files. Click Block Diagram/Schematic File, and click OK. The schematic entry
window will appear on the working space as shown in FIGURE 11

Symbol Tool Orthogonal Node Tool

FIGURE 11: Schematics editor

3. Click Symbol Tool. A pops up dialog box will appear as shown in FIGURE 12

FIGURE 12: Adding new symbol

4. Expand c:\altera\13.0\quartus\library\, expand primitive and then expand logic

5. Select and2 and then check Repeat-insert mode and then click OK
6. Place the three (3) and2 gates as shown in FIGURE 13 by clicking on the desired placing area and then
press the ESC keyboard key to returns back to the normal arrow cursor

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 FIGURE 13: Adding three unit of 2 input AND gate

7. Repeat Step 6 to 8 for or3 gate as shown in FIGURE 14

FIGURE 14: Adding 3 input OR gate

8. Another way to add symbol is by clicking anywhere on the schematic editor working space. A menu
box will appear. Go to Insert then click Symbol
9. Expand c:\altera\13.0\quartus\library\, expand primitive and then expand pin
10. Select input then click OK. By now we should have our design entry such shown in FIGURE 15

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 FIGURE 15: Adding input and output pins

11. Place the three (3) unit input pins on the workspace as describe in Step 6
12. Repeat step 8 to 11 for one output pin
13. Right-click on the top most input pin and click on Properties. We should see a pin properties pops up
dialog box
14. Rename the pin name as “A”. By default, the default value will set to VCC if not, select VCC as shown
in FIGURE 16. Click OK
15. Repeat the Step 13 for pin “B” and “C” and output pin “V”

FIGURE 16: Naming input pin

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16. Select Orthogonal Node Tools on the schematic toolbars such shown in FIGURE 11. Make the circuit
connection for the Boolean equation that priory obtained from Section 4.1.1. To this stage, we should
see the schematics similar to FIGURE 17

FIGURE 17: Rename all input/output pins and circuit

17. Go to File and click Save All

FIGURE 18: Saving the schematics entry

18. Go to Process > Start and click Analysis and Synthesis. We can also simply click on the button
on the menu bar. The compilation report and a pops up dialog box appear after Analysis & Synthesis

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 compilation such shown in FIGURE 19. As for this tutorial, we are not going to evaluate the report
and warnings. Click OK

FIGURE 19: Analysis & Synthesis Compilation results

4.3. University Program VWF

1. Click the icon on the menu bar. A pops up dialog box will appear such shown in FIGURE 21. This
is another way to add new file rather than through File menu as we did at Step 1 of Section 4.2.1

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 FIGURE 20: Adding vector waveform file for functional verification of the design

2. Select University Program VWF such shown in FIGURE 20 and click OK. Simulation waveform
editor window will appear such shown in FIGURE 21
3. Go to View > Fit in Window to get the Vector Waveform at the workspace as in FIGURE 21. We can
also adjust the view at our convenience through Zoom In and Zoom Out tool

Zoom tool

FIGURE 21: Simulation waveform editor window

4. Go to Edit > insert and click insert node or bus. A pops-up dialog box will appear as shown in
FIGURE 22

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 FIGURE 22: Insert node for simulation

5. Click Node Finder. A pops-up box will appear as shown in FIGURE 23

FIGURE 23: Adding input nodes

6. Follow these steps: (1) Set the Filter to Pins:all; (2) Click List; (3) Click the “ >> ” button; (4) Click OK
on the Node Finder windows

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 FIGURE 24: Adding multiple selected nodes

7. We will then be back at the Insert Node or Bus box as shown in FIGURE 24, click OK. By stage we will
see voting inputs “A”, “B” and “C” all goes LOW at time 0ns to 100ns while voting output “V” is the
output to be determined as shown in FIGURE 25

FIGURE 25: Vector waveform workspace after inserting the nodes

8. Highlight “A” from 500ns to 1000ns by moving the mouse cursor to 500ns on “A” row, and Click-Hold-

Drag-Release on 1000ns. Click icon on the toolbar to force the input to go HIGH

FIGURE 26: Selecting input “B”

9. Click input port symbol of input “B” to highlight the whole frame of input “B” as shown in

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 FIGURE 27: Setting period to 500.0ns

10. Next, click overwrite clock icon on the toolbar. Pops-up window will appear as shown in FIGURE
27 fill-up period 500.0ns then click OK

11. Click port symbol of input “C” to highlight the whole frame of the input “C” as shown in
FIGURE 28

FIGURE 28: Selecting input “C”

12. Next, click a pops-up box will appear as shown in FIGURE 29. Fill -up transition occurrence to count
every 215ns, click OK

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 FIGURE 29: Setting the transition occurrence to count every 125ns

13. Go to File click Save as. A pops-up box will appear as shown in FIGURE 30, click Save

FIGURE 30: Saving the waveform simulation

14. Click run functional simulation icon on the toolbar. If the simulation is successful, a new window
will appear showing the result of simulated waveforms.

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 FIGURE 31: Functional simulation waveforms result

15. With corresponding input “A”, “B” and “C”, notice that “V” is responding in accordance to our Boolean
equation. Therefore, out design is now functional verified

16. Next, click run timing simulation icon on the toolbar the result as indicated in FIGURE 32. For
this simple simulation, we will not consider timing requirement carefully. However, for more complicated
model one should consider all the timing requirements as it will determine the functionality of the design
in an actual devices

FIGURE 32: Timing simulation waveforms result

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4.4. Pin Assignments and Compilation

1. Go to Processing > Start and click Start Analysis& Elaboration. As the compilation is done, a message
window will appear, click OK

2. Go to Assignments at the menu bar, click Pin Planner. Alternatively, we can also click icon on
toolbar. A Pin Planner window will appear as shown in FIGURE 33

FIGURE 33: Pin Planner window

3. Double-click the location box for input “A”, “B”, “C” and “V”, and type “PIN_40”, “PIN_42”, “PIN_44”
and “PIN_100” respectively. The location of general input/output pins are similar to the pin number of the
CPLD. For this tutorial, we are targeting Pin 40, 42 and 44 as voting inputs and pin 100 for output.

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 TABLE 2: Pin Assignments for the targeted voting inputs and LED to indicate the voting output

Signal Name FPGA Pin No.

INPUT_A PIN_40
INPUT_B PIN_42
INPUT_C PIN_44
OUTPUT_V PIN_100

4. By now, we should have our Pin Planner window such shown in FIGURE 34. Close the Pin Planner
window. Return to Quartus II main window

FIGURE 34: Pin Planner window after location

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 5. Click to start compilation. When the compilation is complete, message window will appear as
shown in FIGURE 35, click OK. By now, as the full compilation successful, Quartus II will gives us 10
warnings. However for this tutorial, we will not go through all the warnings

FIGURE 35: Compilation pops-up message window

6. Quartus II will generate compilation report as shown in FIGURE 36

FIGURE 36: Compilation report

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4.5. Programing DE0-Nano FPGA Board

1. Make circuit connection of the input switches and LED such shown in FIGURE 37

Vcc
PIN_100

PIN_40

PIN_42

PIN_44

(a) Circuit diagram

(b) Actual circuit connection

Figure 37: Switches and LED connection

2. Connect the EPM240-Mini CPLD board.to the USB blaster cable and USB power port to the PC

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3. On the Quartus II, click programmer icon on the toolbar. Alternatively, we can also go to Tool on
the menu bar and click on programmer. A programmer window will appear as shown in FIGURE 38.

FIGURE 38: Programmer window

4. Click hardware setup. A pops-up window will appear as shown in FIGURE 39. On the Hardware Setup
window, select USB Blaster [USB-0] and then click Close

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 FIGURE 39: Hardware settings

5. If the file name in the programmer does not show Voting.pof, click Add File button on the left side of the
programmer window. Select Voting.pof file from the output folder of the working directory

6. Click START. The progress indicator on the top right of the programmer window shows the status process
of uploading the file to EPM240-Mini board. By now, the board are ready for our Voting project hardware
verification

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 4.6. Hardware Verification

1. Observe the LED as we supply input pins with Vcc or unconnected

2. Notice that LED will only ON if more than one switches are ON. Otherwise the LED will turn OFF

5. CONCLUTION

Through this tutorial, we have learned to create a simple project on EPM240-Mini CPLD board using Quartus II
software. We now know how to perform schematic entry, functional verification, timing simulation and hardware
verification on our designed project. With this knowledge we should are ready to proceed for more complicated
schematics based design.

REFERENCES:

Ab Al-Hadi Ab Rahman & Zulkifli Md Yusof, “Altera Quartus II Tutorial for Introductory Digital Electronics”,
UTM tutorial module for students taking SEE1223

Zulfakar Aspar, “IC Design Using Altera FPGAs” 2nd Edition, Universiti Teknologi Malaysia, 2011

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