A3V28S40JTP

128M Single Data Rate Synchronous DRAM

128Mb Synchronous DRAM Specification

A3V28S40JTP

Zentel Electronics Corp.

Revision 1.0 Oct., 2013

 A3V28S40JTP
128M Single Data Rate Synchronous DRAM

General Description
A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. A3V28S40JTP achieve very high speed data rates up to 166MHz, and are
suitable for main memories or graphic memories in computer systems.

Features
- Single 3.3V ±0.3V power supply
- Maximum clock frequency :
- 60:166MHz<3-3-3>/-70:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- LDQM and UDQM (A3V28S40JTP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Support concurrent auto-precharge
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Pb-free package is available

Ordering Information
54Pin TSOPII (400mil x 875mil)
Part No. Max. Frequency Supply Voltage
A3V28S40JTP-60 166MHz (CL=3) 3.3V
A3V28S40JTP-70 143MHz (CL=3) 3.3V
A3V28S40JTP-75 133MHz (CL=3) 3.3V

Zentel Electronics reserves the right to change products or specification without notice.

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PIN CONFIGURATION (TOP VIEW)

PIN CONFIGURATION
(TOP VIEW)
Vdd 1 54 Vss
DQ0 2 53 DQ15
VddQ 3 52 VssQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VssQ 6 49 VddQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VddQ 9 46 VssQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VssQ 12 43 VddQ
DQ7 13 42 DQ8
Vdd 14 41 Vss
LDQM 15 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10(AP) 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
Vdd 27 28 Vss

CLK : Master Clock U,L DQM : Output Disable / Write Mask

CKE : Clock Enable A0-11 : Address Input
/CS : Chip Select BA0,1 : Bank Address
/RAS : Row Address Strobe Vdd : Power Supply
/CAS : Column Address Strobe VddQ : Power Supply for Output
/WE : Write Enable Vss : Ground
DQ0-15 : Data I/O VssQ : Ground for Output

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128M Single Data Rate Synchronous DRAM

Block Diagram

DQ 0 - 15

I/O Buffer

Memory Memory Memory Memory

Array Array Array Array
Bank #0 Bank #1 Bank #2 Bank #3

Mode Register

Control Circuitry

Address Buffer Control Signal Buffer

Clock Buffer
A0-11 BA0,1 /CS /RAS /CAS /WE UDQM
CLK CKE LDQM

Type Designation Code

A 3 V 28 S 4 0J TP - 60
75: 133MHz@CL=3
70: 143MHz@CL=3
Speed
60: 166MHz@CL=3
Package Type TP: TSOP II

Die Version 0J: Version 0J

I/O
4: x16
Configuration
Classification S: SDR

Density 28:128Mb

Interface V: LVTTL

Product Line 3: DRAM

Zentel Memory

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128M Single Data Rate Synchronous DRAM

Pin Descriptions

SYMBOL TYPE DESCRIPTION

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
CLK Input edge of CLK. CLK also increments the internal burst counter and controls the output registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst /
CKE Input access in progress). CKE is synchronous except after the device enters self refresh mode, where
CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK,
are disabled during self refresh mode, providing low standby power. CKE may be tied HIGH.

Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
/CS Input bank selection on systems with multiple banks. /CS is considered part of the command code.

/CAS, Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
/RAS, Input
/WE
Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output disable signal for read accesses. Input data is masked during a WRITE cycle. The
LDQM, output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM
Input
UDQM, corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15.

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
BA0, BA1 Input PRECHARGE command is being applied.

A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is
specified by A0-11. The Column Address is specified by A0-8. A10 is also used to indicate
A0–A11 Input precharge option. When A10 is high at a read / write command, an auto precharge is performed.
When A10 is high at a precharge command, all banks are precharged.

Data Input / Output: Data bus.

DQ0–DQ15 I/O
Internally Not Connected: These could be left unconnected, but it is recommended they be
NC – connected or VSS.

Data Output Power: Provide isolated power to output buffers for improved noise immunity.
VddQ Supply
Data Output Ground: Provide isolated ground to output buffers for improved noise immunity.
VssQ Supply
Power for the input buffers and core logic.
Vdd Supply
Ground for the input buffers and core logic.
Vss Supply

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128M Single Data Rate Synchronous DRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN,VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to Vss Vdd, VddQ -1.0 ~ 4.6 V

Storage temperature TSTG -55 ~ +150 °C

Operating ambient temperature TA 0 ~ 70 °C

Power dissipation PD 1.0 W

Short circuit current IOS 50 mA

NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Vdd 3.0 3.3 3.6 V

Supply voltage
VddQ 3.0 3.3 3.6 V

Input logic high voltage VIH 2.0 Vdd Vdd + 0.3 V 1

Input logic low voltage VIL -0.3 0 0.8 V 2

Output logic high voltage VOH 2.4 - - V IOH = -2mA

Output logic low voltage VOL - - 0.4 V IOL = 2mA

Input leakage current IIL -10 - 10 uA 3

Output leakage current IOL -10 - 10 uA 3

Note:
1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V ≤ VOUT ≤ VDD.

CAPACITANCE ( Vdd = VddQ = 3.3V, TA = 25°C, f = 1MHz, pin under test biased at 1.4V.)

Parameter Symbol Min Max Unit Note

Clock Cclk 2.0 3.5 pF

/CAS,/RAS,/WE,/CS,CKE, U/LDQM Cin 2.0 3.5 pF

Address CADD 2.0 3.5 pF

DQ0~DQ15 COUT 3.5 5.5 pF

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DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted, TA = 0 to 70°C)
Version
Parameter Symbol Test Condition Unit Note
-60 -70 -75

Burst length = 2
Operating Current
ICC1 tRC = tRC(min) 80 75 70 mA 1
(One Bank Active)
IO = 0 mA

Precharge Standby ICC2P CKE = VIL(max), tCC = 10ns 10

Current in mA
power-down mode ICC2PS CKE & CLK = VIL(max), tCC = ∞ 5

CKE = VIH(min), CS = VIH(min),

tCC = 10ns
Precharge Standby ICC2N 30
Input signals are changed one
Current time during 20ns mA
non power-down
mode CKE = VIH(min), CLK = VIL(max),
ICC2NS tCC = ∞ 25
Input signals are stable
Active Standby ICC3P CKE = VIL(max), tCC = 10ns 30
Current mA
power-down mode
(One Bank Active) ICC3PS CKE & CLK = VIL(max), tCC = ∞ 25
CKE = VIH(min), CS = VIH(min),
tCC = 10ns
Active Standby ICC3N 45
Input signals are changed one
Current time during 20ns
non power-down mA
mode CKE = VIH(min), CLK = VIL(max),
35
(One Bank Active) ICC3NS tCC = ∞
Input signals are stable

IO = 0 mA
Operating Current Page burst
ICC4 100 90 85 mA 1
(Burst Mode) 4Banks Activated
tCCD = 2CLKs

Refresh Current ICC5 tARFC = tARFC(min) 115 100 95 mA 2

Self Refresh Current ICC6 CKE = 0.2V 5 5 5 mA

NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).

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AC OPERATING TEST CONDITIONS (VDD = VddQ = 3.3V ±0.3V, TA = 0 to 70°C)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4 / 0.4 V

Input timing measurement reference level 1.4 V

Input rise and fall time tr/tf = 1/1 Ns

Output timing measurement reference level 1.4 V

Output load condition See Figure 2

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OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)

Version Unit Note

Parameter Symbol
-60 -70 -75

Row active to row active delay tRRD(min) 12 14 15 ns 1

RAS to CAS delay tRCD(min) 18 20 20 ns 1

Row precharge time tRP(min) 18 20 20 ns 1

tRAS(min) 42 45 45 ns 1
Row active time
tRAS(max) 100 100 100 us

Row cycle time tRC(min) 60 63 65 ns 1

Last data in to row precharge tRDL(min) 2 2 2 CLK 2

Last data in to Active delay tDAL(min) 5 5 5 CLK-

Last data in to new col. address delay tCDL(min) 1 1 1 CLK 2

Last data in to burst stop tBDL(min) 1 1 1 CLK 2

Mode register set cycle time tMRD(min) 2 2 2 CLK

Refresh interval time tREF(max) 64 64 64 ms

Auto refresh cycle time tARFC(min) 60 70 75 ns

NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.

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128M Single Data Rate Synchronous DRAM

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

-60 -70 -75
Parameter Symbol Unit Note
Min Max Min Max Min Max

CAS latency=3 tCC (3) 6 7 7.5

CLK cycle time ns 1
CAS latency=2 tCC (2) 10 10 10

CAS latency=3 tSAC (3) 5.4 5.4 5.4

CLK to valid output delay ns 1,2
CAS latency=2 tSAC (2) 5.4 5.4 6

CAS latency=3 tOH (3) 2.5 2.5 2.5

Output data hold time ns 2
CAS latency=2 tOH (2) 2.5 2.5 2.5

CLK high pulse width tCH 2.5 2.5 2.5 ns 3

CLK low pulse width tCL 2.5 2.5 2.5 ns 3

Input setup time tSI 1.5 1.5 1.5 ns 3

Input hold time tHI 0.8 0.8 0.8 ns 3

Transition time of CLK tT 0.3 1.5 0.3 1.5 0.3 1.5 ns

CLK to output in Low-Z tSLZ 1 1 1

CAS latency=3 5.4 5.4 5.4

CLK to output in Hi-Z tSHZ ns
CAS latency=2 5.4 5.4 6

NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

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128M Single Data Rate Synchronous DRAM

TRUTH TABLE

Command Truth Table

A10/ A11,
COMMAND Symbol CKEn-1 CKEn /CS /RAS /CAS /WE BA1 BA0
AP A9 ~ A0
Device deselect DSL H X H X X X X X X X
No operation NOP H X L H H H X X X X
Burst stop BST H X L H H L X X X X
Read RD H X L H L H V V L V
Read with auto precharge RDA H X L H L H V V H V
Write WR H X L H L L V V L V
Write with auto precharge WRA H X L H L L V V H V
Bank activate ACT H X L L H H V V V V
Precharge select bank PRE H X L L H L V V L X
Precharge all banks PALL H X L L H L X X H X
Mode register set MRS H X L L L L L L L OP code
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

CKE Truth Table

Current state Function Symbol CKEn-1 CKEn /CS /RAS /CAS /WE /Address
Enter Clock suspend or H L L V V V V
Activating
Active power down H L H X X X X
Clock suspend or Maintain Clock suspend or
L L X X X X X
Active power down Active power down
Clock suspend or Exit Clock suspend or
L H X X X X X
Active power down Active power down
All banks idle Auto refresh command REF H H L L L H X
All banks idle Enter Self refresh SREF H L L L L H X
H L L H H H X
All banks idle Enter Precharge power down
H L H X X X X
L H L H H H X
Self refresh Exit Self refresh
L H H X X X X
Precharge power L H L H H H X
Exit Prechage power down
down L H H X X X X
Precharge power Maintain Precharge power
L L X X X X X
down down
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

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128M Single Data Rate Synchronous DRAM

Function Truth Table

Current state /CS /RAS /CAS /WE /Address Command Action Notes
Idle H X X X X DESL NOP
L H H H X NOP NOP
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA ILLEGAL 2
L H L L BA,CA,A10 WR/WRA ILLEGAL 2
L L H H BA,RA ACT Bank active
L L H L BA,A10 PRE/PALL NOP 4
L L L H X REF Auto refresh 5
L L L L OC MRS Mode register set 5
Row active H X X X X DESL NOP
L H H H X NOP NOP
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA Begin read, determine AP
L H L L BA,CA,A10 WR/WRA Begin write, determine AP
L L H H BA,RA ACT Bank active / ILLEGAL 2
L L H L BA,A10 PRE/PALL Precharge / Precharge all banks
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Read H X X X X DESL Continue burst to end
L H H H X NOP Continue burst to end
L H H L X BST Terminate burst
L H L H BA,CA,A10 RD/RDA Terminate burst, begin read, determine AP 3
L H L L BA,CA,A10 WR/WRA Terminate burst, begin write, determine AP 3
L L H H BA,RA ACT Bank active / ILLEGAL 2
L L H L BA,A10 PRE/PALL Terminate burst, precharge
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Write H X X X X DESL Continue burst to end
L H H H X NOP Continue burst to end
L H H L X BST Terminate burst
L H L H BA,CA,A10 RD/RDA Terminate burst, begin read, determine AP 3
L H L L BA,CA,A10 WR/WRA Terminate burst, begin write, determine AP 3
L L H H BA,RA ACT Bank active / ILLEGAL 2
L L H L BA,A10 PRE/PALL Terminate burst, precharge
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Read with auto H X X X X DESL Continue burst to end
precharge L H H H X NOP Continue burst to end
L H H L X BST ILLEGAL
L H L H BA,CA,A10 RD/RDA Support concurrent auto-precharge 2
L H L L BA,CA,A10 WR/WRA Support concurrent auto-precharge 2
L L H H BA,RA ACT Bank active / ILLEGAL 2
L L H L BA,A10 PRE/PALL ILLEGAL 2
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Write with auto H X X X X DESL Continue burst to end
precharge L H H H X NOP Continue burst to end
L H H L X BST ILLEGAL
L H L H BA,CA,A10 RD/RDA Support concurrent auto-precharge 2
L H L L BA,CA,A10 WR/WRA Support concurrent auto-precharge 2
L L H H BA,RA ACT Bank active / ILLEGAL 2
L L H L BA,A10 PRE/PALL ILLEGAL 2
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL

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128M Single Data Rate Synchronous DRAM

Current state /CS /RAS /CAS /WE /Address Command Action Notes
Precharging H X X X X DESL NOP, idle after tRP
L H H H X NOP NOP, idle after tRP
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA ILLEGAL 2
L H L L BA,CA,A10 WR/WRA ILLEGAL 2
L L H H BA,RA ACT Bank active / ILLEGAL 2
L L H L BA,A10 PRE/PALL Nop, idle after tRP 4
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Row activating H X X X X DESL NOP, row active after tRCD
L H H H X NOP NOP, row active after tRCD
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA ILLEGAL 2
L H L L BA,CA,A10 WR/WRA ILLEGAL 2
L L H H BA,RA ACT ILLEGAL 2
L L H L BA,A10 PRE/PALL ILLEGAL 2
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Write H X X X X DESL NOP
recovering L H H H X NOP NOP
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA Begin read, determine AP
L H L L BA,CA,A10 WR/WRA Begin write, determine AP
L L H H BA,RA ACT ILLEGAL 2
L L H L BA,A10 PRE/PALL ILLEGAL 2
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Refreshing H X X X X DESL NOP, idle after tARFC
L H H H X NOP NOP, idle after tARFC
L H H L X BST ILLEGAL
L H L H BA,CA,A10 RD/RDA ILLEGAL
L H L L BA,CA,A10 WR/WRA ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PALL ILLEGAL
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Mode register H X X X X DESL NOP, idle after tMRD
accessing L H H H X NOP NOP, idle after tMRD
L H H L X BST ILLEGAL
L H L H BA,CA,A10 RD/RDA ILLEGAL
L H L L BA,CA,A10 WR/WRA ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PALL ILLEGAL
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL

Notes: 1. All entries assumes that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to the bank in specified state; function may be legal in the bank indicated by BA, depending on the state
of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.

ILLEGAL : Device operation and/or data-integrity are not guaranteed.

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128M Single Data Rate Synchronous DRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with Normal MRS

Address BA0 BA1 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function 0 0 0 0 WB 0 0 CAS Latency BT Burst Length

MRS Mode
CAS Latency Burst Type Burst Length Write Burst Mode
A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 A9 Type
0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 Programmed Burst Length
0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 Single Location Access
0 1 0 2 0 1 0 4 4
0 1 1 3 0 1 1 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved 1 1 1 Full Page Reserved

BURST SEQUENCE
STARTING COLUMN ORDER OF ACCESSES WITHIN A BURST
BURST LENGTH
ADDRESS
TYPE=SEQUENTIAL TYPE=INTERLEAVED
A0
2 0 0-1 0-1
1 1-0 1-0
A1 A0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
N=A0 – A8 Cn, Cn+1, Cn+2, Cn+3,
Full Page (y) Not Supported
(location 0 – y) Cn+4..., …Cn-1, Cn…

NOTE:
1. For full-page accesses: y = 511.
2. For a burst length of two, A1–A8 select the block-of-two burst; A0 selects the starting column within the block.
3. For a burst length of four, A2–A8 select the block-of-four burst; A0–A1 select the starting column within the block.
4. For a burst length of eight, A3–A8 select the block-of-eight burst; A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7. For a burst length of one, A0–A8 select the unique column to be accessed, and mode register bit A3 is ignored.

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Power-up sequence
Power-up sequence
1. Apply VDD and VDDQ at the same time. Keep CKE low during power up.
2. Wait for stable power.
3. Start clock and drive CKE high.

Note : Voltage on any input pin must not exceed VDD+0.3V during power up.

Initialization sequence
4. After stable power and stable clock, wait 200us.
5. Issue precharge all command (PALL).
6. After tRP delay, set 2 or more auto refresh commands (REF).
7. Set the mode register set command (MRS) to initialize the mode register.

Note : We recommend that you keep DQM and CKE high during initialization sequence to prevent data contention on the DQ
bus.

CKE

tRP tARFC tARFC tMRD

Command PALL REF REF MRS CMD
CKE
Power stable Clock stable

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Operation of the SDRAM

Read/Write Operations

Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank
active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write
command input.

Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after
read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the
bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks
specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive
burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.

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Write operation

Burst write or single write mode is selected

1. Burst write: A burst write operation is enabled by setting OPCODE A9 to 0. A burst write starts in the same clock as a write
command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations.
The write start address is specified by the column address and the bank select address at the write command set cycle.
.

2. Single write: A single write operation is enabled by setting OPCODE A9 to 1. In a single write operation, data is only
written to the column address and the bank select address specified by the write command set cycle without regard to the
burst length setting. (The latency of data input is 0 clock).

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Auto Precharge

Read with auto-precharge

In this operation, since precharge is automatically performed after completing a read operation, a precharge command need
not be executed after each read operation. The command executed for the same bank after the execution of this command
must be the bank active (ACT) command.
The next ACT command can be issued at the later time of either tRP after internal precharge or tRC after the previous ACT.

Write with auto-precharge

In this operation, since precharge is automatically performed after completing a burst write or single write operation, a
precharge command need not be executed after each write operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command.
The next ACT command can be issued at the later time of either tDAL from the last input data cycle or tRC after the previous
ACT.

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Burst Stop Command

During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to
High-Z after the /CAS latency from the burst stop command.

During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to
High-Z at the same clock with the burst stop command.

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Command Intervals

Read command to Read command interval

1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank
as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock.
Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.

2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands
cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. Even when the first command is a burst read that is not yet finished,
the data read by the second command will be valid.

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Write command to Write command interval

1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank
as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of
burst writes, the second write command has priority.

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;
it is necessary to separate the two write commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.

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Read command to Write command interval

1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as
the preceding read command, the write command can be performed after an interval of no less than 1 clock. However,
UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input.

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;
it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle,
provided that the other bank is in the bank active state. However, UDQM and LDQM must be set High so that the output
buffer becomes High-Z before data input.

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Write command to Read command interval:

1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as
the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in
the case of a burst write, data will continue to be written until one clock before the read command is executed.

2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed;
it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be
written until one clock before the read command is executed (as in the case of the same bank and the same address).

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Read with auto precharge to Read command interval (concurrent auto-precharge)

1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even
when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is
valid. The internal auto-precharge of one bank starts at the clock of the second command.

2. Same bank: The consecutive read command (the same bank) is illegal.

Write with auto precharge to Write command interval (concurrent auto-precharge)

1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the
case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next
clock of the second command.

2. Same bank: The consecutive write command (the same bank) is illegal.

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Read with auto precharge to Write command interval (concurrent auto-precharge)

1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However,
UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input. The internal
auto-precharge of one bank starts at the clock of the second command.

2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to
separate the two commands with a bank active command.

Write with auto precharge to Read command interval (concurrent auto-precharge)

1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However,
in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal
auto-precharge of one bank starts at the next clock of the second command.

2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to
separate the two commands with a bank active command.

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Read command to Precharge command interval (same bank)

When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval
between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by
lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during
burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output
to precharge command execution.

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Write command to Precharge command interval (same bank)

When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval
between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by
means of UDQM and LDQM for assurance of the clock defined by tRDL.

tRDL

tRDL

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Bank active command interval

1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no less than
tRRD.

Mode register set to Bank active command interval

The interval between setting the mode register and executing a bank active command must be no less than tMRD.

tMRD
RDL

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DQM Control
The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and LDQM is
different during reading and writing.

Reading
When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low, the output
buffer becomes Low-Z, enabling data output. By setting UDQM and LDQM to High, the output buffer becomes High-Z, and
the corresponding data is not output. However, internal reading operations continue. The latency of UDQM and LDQM
during reading is 2 clocks.

Writing
Input data can be masked by UDQM and LDQM. By setting DQM to Low, data can be written. In addition, when UDQM and
LDQM are set to High, the corresponding data is not written, and the previous data is held. The latency of UDQM and LDQM
during writing is 0 clock.

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Refresh

Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the
internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external
address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.).
The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not required.

Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh
operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit
command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF(max.) period
on the condition 1 and 2 below.

1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh
addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below* after exiting from
self-refresh mode.

Note : tREF(max.) / refresh cycles.

Others

Power-down mode
The SDRAM enters power-down mode when CKE goes Low. For cases of all banks in the IDLE state, it is referred to as
precharge power-down mode. For cases of any bank in the ACTIVE state, it is referred to as active power-down mode. In
power down mode, power consumption is suppressed by deactivating the input buffers excluding CLK and CKE. Power
down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down
mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed.

Clock suspend mode

By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During clock
suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the
SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE
Truth Table".

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Timing Waveforms
Read Cycle

tCC

tSAC tSAC tSAC tSHZ

C C C ACC

tSAC
C

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Write Cycle

tCC

tRDL

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Mode Register Set Cycle

tRP tMRD tRCD

Read Cycle/Write Cycle

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Read/Single Write Cycle

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Read/Burst Write Cycle

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Auto Refresh Cycle

tARFC tARFC

Self Refresh Cycle

tARFC tARFC

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Active Power-Down Mode, Clock Suspend Mode

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Precharge Power-Down Mode

Initialization Sequence

tARFC tARFC tMRD

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Package Drawing

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Important Notice:
Zentel products are not intended for medical implementation, airplane and transportation
instrument, safety equipments, or any other applications for life support or where Zentel products
failure could result in life loss, personal injury, or environment damage. Zentel customers who
purchase Zentel products for use in such applications do so in their own risk and fully agree Zentel
accepts no liability for any damage from this improper use.

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