Prepared by:
Assist. Lect. Omar Haitham Alhabieb
Computer Architecture
Lesson 4 (Data Paths in the CPU)
Data Paths in the CPU
The CPU can be divided into a data section and a control section.
The data section, which is also called the data path, contains the
registers and the ALU. The data path is capable of performing certain
operations on data items.
The control section is basically the control unit, which issues control
signals to the data path.
Internal to the CPU, data move from one register to another and
between ALU and registers. Internal data movements are performed
via local buses, which may carry data, instructions, and addresses.
Externally, data move from registers to memory and I/O devices,
often by means of a system bus.
Types of Internal Data Movements
Internal data movement among registers and between the ALU and registers
may be carried out using different organizations including one-bus, two-bus,
or three-bus organizations:
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
A. One-Bus Organization
Using one bus, the CPU registers and the ALU use a single bus
to move outgoing and incoming data.
Since a bus can handle only a single data movement within one
clock cycle, two-operand operations will need two cycles to
fetch the operands for the ALU. Additional registers may also
be needed to buffer data for the ALU.
This bus organization is the simplest and least expensive, but it
limits the amount of data transfer that can be done in the same
clock cycle, which will slow down the overall performance.
Figure 1 shows a one-bus data path consisting of a set of
general-purpose registers, a memory address register (MAR), a
memory data register (MDR), an instruction register (IR), a
program counter (PC), and an ALU.
Figure 1. One-bus data path
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
B. Two-Bus Organization
Using two buses is a faster solution than the one-bus organization.
In this case, general-purpose registers are connected to both buses.
Data can be transferred from two different registers to the input point
of the ALU at the same time.
Therefore, a two operand operation can fetch both operands in the
same clock cycle. An additional buffer register may be needed to hold
the output of the ALU when the two buses are busy carrying the two
operands. Figure 2 shows a two-bus organization.
Figure 2. Two-bus data paths
In some cases, one of the buses may be dedicated for moving
data into registers (in-bus), while the other is dedicated for
transferring data out of the registers (out-bus).
In this case, the additional buffer register may be used, as one
of the ALU inputs, to hold one of the operands. The ALU
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
output can be connected directly to the in-bus, which will
transfer the result into one of the registers.
Figure 3 shows a two-bus organization with in-bus and out-bus.
Figure 3. Two-Bus data path with in-bus and out-bus
C. Three-Bus Organization
In a three-bus organization, two buses may be used as source buses
while the third is used as destination.
The source buses move data out of registers (out-bus), and the
destination bus may move data into a register (in-bus).
Each of the two out-buses is connected to an ALU input point. The
output of the ALU is connected directly to the in-bus.
As can be expected, the more buses we have, the more data we can
move within a single clock cycle. However, increasing the number of
buses will also increase the complexity of the hardware.
Figure 4 shows an example of a three-bus data path.
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
Figure 4. Three-bus data paths
CPU Instruction Cycle
The basic actions during fetching an instruction, executing an
instruction, or handling an interrupt are defined by a sequence of
micro-operations.
A group of control signals must be enabled in a prescribed sequence
to trigger the execution of a microoperation.
In this lesson, we will study the micro-operations that implement
instruction fetch, execution of simple arithmetic instructions, and
interrupt handling.
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
Fetch Instructions
The sequence of events in fetching an instruction can be summarized as
follows:
1. The contents of the PC are loaded into the MAR.
2. The value in the PC is incremented. (This operation can be done in
parallel with a memory access.)
3. As a result of a memory read operation, the instruction is loaded into the
MDR.
4. The contents of the MDR are loaded into the IR.
Let us consider the one-bus data path organization shown in Fig. 1. We will
see that the fetch operation can be accomplished in three steps as shown in
the table below. Note that multiple operations separated by “;” imply that
they are accomplished in parallel.
Using the three-bus data path shown in Figure 4, the following table shows
the steps needed.
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
Execute Simple Arithmetic Operation
Add R1, R2, R0
This instruction adds the contents of source registers R1 and R2, and stores
the results in destination register R0. This addition can be executed as
follows:
1. The registers R0, R1, R2, are extracted from the IR.
2. The contents of R1 and R2 are passed to the ALU for addition.
3. The output of the ALU is transferred to R0.
Using the one-bus data path shown in Figure 1, this addition will take three
steps as shown in the following table:
Using the two-bus data path shown in Figure 2, this addition will take two
steps as shown in the following table:
Using the two-bus data path with in-bus and out-bus shown in Figure 3, this
addition will take two steps as shown below:
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
Using the three-bus data path shown in Figure 4, this addition will take only
one step as shown in the following table.
Add R0, X
This instruction adds the contents of memory location X to register R0 and
stores the result in R0. This addition can be executed as follows:
1. The memory location X is extracted from IR and loaded into MAR.
2. As a result of memory read operation, the contents of X are loaded into
MDR.
3. The contents of MDR are added to the contents of R0.
Using the one-bus data path shown in Figure 1, this addition will take five
steps as shown below:
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
Using the two-bus data path shown in Figure 2, this addition will take four
steps as shown below:
Using the two-bus data path with in-bus and out-bus shown in Figure 3, this
addition will take four steps as shown below:
Using the three-bus data path shown in Figure 4, this addition will take three
steps as shown below:
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Prepared by:
Assist. Lect. Omar Haitham Alhabieb
Interrupt Handling
After the execution of an instruction, a test is performed to check for
pending interrupts. If there is an interrupt request waiting, the following
steps take place:
1. The contents of PC are loaded into MDR (to be saved).
2. The MAR is loaded with the address at which the PC contents are to be
saved.
3. The PC is loaded with the address of the first instruction of the interrupt
handling routine.
The contents of MDR (old value of the PC) are stored in memory. The
following table shows the sequence of events:
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