Fabrication of pnp

transistor
By HEMANT CHOUDHARY(15EE35023)
PASULA SANDEEP(15EE35024)
PULAPA KIRAN(15EE35025)
Key steps involved
● Wafer production
● Epitaxial growth
● Etching
● Doping
● Metallization
● Assembly and packaging
Wafer Production
The first step is wafer production. The wafer is a round slice of semiconductor material such as silicon.
Silicon is preferred due to its characteristics. It is more suitable for manufacturing IC. It is the base or
substrate for entire chip. First purified polycrystalline silicon is created from the sand. Then it is heated to
produce molten liquid. A small piece of solid silicon is dipped on the molten liquid. Then the solid silicon
(seed) is slowly pulled from the melt. The liquid cools to form single crystal ingot. A thin round wafer of
silicon is cut using wafer slicer. Wafer slicer is a precise cutting machine and each slice having thickness
about .01 to .025 inches. When wafer is sliced, the surface will be damaged. It can be smoothening by
polishing. After polishing the wafer, it must thoroughly clean and dried. The wafers are cleaned using high
purity low particle chemicals .The silicon wafers are exposed to ultra pure oxygen.
Epitaxial growth
● It means the growing of single silicon crystal upon original silicon substrate. A uniform layer of
silicon dioxide is formed on the surface of wafer.
Masking
● To protect some area of wafer when working on another area, a process called photolithography is
used. The process of photolithography includes masking with a photographic mask and photo
etching. A photoresist film is applied on the wafer. The wafer is aligned to a mask using photo
aligner. Then it is exposed to ultraviolet light through mask. Before that the wafer must be aligned
with the mask. Generally, there are automatic tools for alignment purpose.
Etching
● It removes material selectively from the surface of wafer to create patterns. The pattern is defined
by etching mask. The parts of material are protected by this etching mask. Either wet (chemical) or
dry (physical) etching can be used to remove the unmasked material. To perform etching in all
directions at same time, isotropic etching will be used. Anisotropic etching is faster in one direction.
Wet etching is isotropic, but the etching time control is difficult. Wet etching uses liquid solvents for
removing materials. It is not suited to transfer pattern with submicron feature size. It does not
damage the material. Dry etching uses gases to remove materials. It is strongly anisotropic. But it
is less selective. It is suited to transfer pattern having small size. The remaining photoresist is finally
removed using additional chemicals or plasma. Then the wafer is inspected to make sure that the
image is transferred from mask to the top layer of wafer.
Doping
● To alter the electrical character of silicon, atom with one less electron than silicon such as boron
and atom with one electron greater then silicon such as phosphorous are introduced into the area.
The P-type (boron) and N-type (phosphorous) are created to reflect their conducting characteristics.
Diffusion is defined as the movement of impurity atoms in semiconductor material at high
temperature.
● There are two ways of doping:
○ Atomic diffusion
○ Ion implantation
Atomic diffusion

● In this method p and n regions are created by adding dopants into the wafer. The wafers are placed
in an oven which is made up of quartz and it is surrounded with heating elements. Then the wafers
are heated at a temperature of about 1500-2200°F. The inert gas carries the dopant chemical. The
dopant and gas is passed through the wafers and finally the dopant will get deposited on the wafer.
This method can only be used for large areas. For small areas it will be difficult and it may not be
accurate.
Ion implantation

● This is also a method used for adding dopants. In this method, dopant gas such as phosphine or
boron trichloride will be ionized first. Then it provides a beam of high energy dopant ions to the
specified regions of wafer. It will penetrate the wafer. The depth of the penetration depends on the
energy of the beam. By altering the beam energy, it is possible to control the depth of penetration of
dopants into the wafer. The beam current and time of exposure is used to control the amount of
dopant. This method is slower than atomic diffusion process. It does not require masking and this
process is very precise. First it points the wafer that where it is needed and shoot the dopants to the
place where it is required.
METALIZATION
● It is used to create contact with silicon and to make interconnections on chip. A thin layer of aluminum is deposited

over the whole wafer. Aluminium is selected because it is a good conductor, has good mechanical bond with silicon,

forms low resistance contact and it can be applied and patterned with single deposition and etching process.

● Making successive layers: - The process such as masking, etching, doping will be repeated for each successive

layers until all integrated chips are completed. Between the components, silicon dioxide is used as insulator. This

process is called chemical vapor deposition. To make contact pads, aluminum is deposited. The fabrication

includes more than three layers separated by dielectric layers. For electrical and physical isolation a layer of solid

dielectric is surrounded in each component which provides isolation. It is possible to fabricate PNP and NPN

transistor in the same silicon substrate. To avoid damage and contamination of circuit, final dielectric layer

(passivation) is deposited. After that, the individual IC will be tested for electrical function. Check the functionality of

each chip on wafer. Those chips are not passed in the test will be rejected.
Assembly and packaging
● Each of the wafers contains hundreds of chips. These chips are separated and packaged by a
method called scribing and cleaving. The wafer is similar to a piece of glass. A diamond saw cut the
wafer into single chips. The diamond tipped tool is used to cut the lines through the rectangular grid
which separates the individual chips. The chips that are failed in electrical test are discarded. Before
packaging, remaining chips are observed under microscope. The good chip is then mounted into a
package. Thin wire is connected using ultrasonic bonding. It is then encapsulated for protection.
Before delivered to customer, the chip is tested again. There are three configurations available for
packaging. They are metal can package, ceramic flat package and dual in line package. For military
applications, the chip is assembled in ceramic packages. The complete integrated circuits are
sealed in anti static plastic bags.
Pnp fabrication
Major Processing Steps for a Junction Isolated BJT
Technology

Start with a p substrate.

1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Emitter and collector p-type diffusion
5. n+ diffusion
6. p+ ohmic contact
7. Contact etching
8. Metal deposition and etching
9. Passivation and bond pad opening
Implantation of the Buried Layer (Mask Step 1 )
● Objective of the buried layer is to reduce the base resistance.
● P substrate is obtained by atomic diffusion of Si Wafer with
Boron,Aluminium,etc.
○ Atomic diffusion can be used due to large area of wafer.

● N+ buried layer is obtained by:

○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ Ion gun implants the n type doped ions into the P substrate.
○ Ion gun beam energy(1-200 keV)determines the depth of buried layer.
○ Remaining part like photoresist and oxide layer are etched off.
Epitaxial Layer (No Mask Required)
● The objective is to provide the proper n-type doping in which to build the
pnp BJT.
● The new Si layer is formed on the substrate using:
○ Molecular Beam Epitaxy
○ Chemical Vapour Deposition(CVD)

● Epitaxial layer is lightly doped with n type doping material

○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ Ion gun implants the n type doped ions into the Si layer
○ Exposure time determines the extent of doping.
○ Remaining part like photoresist and oxide layer are etched off.
p+ isolation diffusion (Mask Step 2)
● The objective of this step is to surround (isolate) the pnp BJT by a p+
diffusion. These regions also permit contact to the substrate from the
surface.
● Isolation Layer(P+ type) used to separate different IC.
○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ Ion gun implants the p type doped ions into the epitaxial layer
○ Exposure time determines the extent of doping.
○ Remaining part like photoresist and oxide layer are etched off.

● P+ : Highly Doped p type

● P : lightly doped p type
● N+ : Highly Doped n type
● N : lightly doped n type
Emitter and collector p-type diffusion (Mask Step 3)
● The step provides the p-type emitter and collector for the pnp BJT.
● Collector and Emitter(P type) of transistor are embedded in n type layer.
○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ Ion gun implants the p type doped ions into the epitaxial layer
○ Exposure time determines the extent of doping.
○ Ion gun beam energy(1-200 keV)determines the depth of buried layer.
○ Remaining part like photoresist and oxide layer are etched off.
n+ diffusion (Mask Step 4)
● This step implements the n+ doping of the pnp BJT and the ohmic contact to
the base.
● Base(n+ type) of transistor are embedded in n type layer.
○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ Ion gun implants the n type doped ions into the epitaxial layer
○ Exposure time determines the extent of doping.
○ Ion gun beam energy(1-200 keV)determines the depth of buried layer.
○ Remaining part like photoresist and oxide layer are etched off.
P+ ohmic contact(Mask step 5)
● This step permits ohmic contact to the emitter and collector regions if it
is not doped sufficiently high
● Collector and Emitter(n+ type) highly doped for metal contact
○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ Ion gun implants the n+ type doped ions into collector and emitter.
○ Exposure time determines the extent of doping.
○ Ion gun beam energy(1-200 keV)determines the depth of buried layer.
○ Remaining part like photoresist and oxide layer are etched off.
Contact etching (Mask Step 6)
● This step opens up the areas in the dielectric area which metal will
contact.
● Formation of Oxide layer(SiO2)for insulation and dielectric.
○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ The Desired part is left for metal contact
○ Remaining part photoresist is etched off.
Metal deposition and etching (Mask Step 7)
● In this step, the metal is deposited over the entire wafer and removed
where it is not wanted.
● Development of metal contact for electrical connection..
○ Creating a appropriate mask
○ Photolithography used to access the desired area
○ Aluminium layer is coated over it using sputtering.
○ Remaining part photoresist and unused Al layer are etched off.
References

● https://circuitglobe.com/fabrication-of-transistor.html
● http://inst.eecs.berkeley.edu/~ee40/su05/lectures/lecture
18.pdf
● https://www.youtube.com/watch?v=Q5paWn7bFg4&feature=youtu
.be
● https://www.youtube.com/watch?v=AMgQ1-HdElM&feature=youtu
.be
● https://www.youtube.com/watch?v=2fOtOp4KXbM