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Capyure 101

The document contains code for two VHDL entities: 1. A comparator entity "Comp" that compares two 4-bit inputs and outputs signals indicating whether the first is greater than, smaller than, or equal to the second. 2. A binary to gray code converter entity "BinaryToGray" that takes a 4-bit binary number as input and outputs the equivalent gray code number. It implements the gray code conversion by XORing adjacent bits.

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Gurdeep Singh
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46 views2 pages

Capyure 101

The document contains code for two VHDL entities: 1. A comparator entity "Comp" that compares two 4-bit inputs and outputs signals indicating whether the first is greater than, smaller than, or equal to the second. 2. A binary to gray code converter entity "BinaryToGray" that takes a 4-bit binary number as input and outputs the equivalent gray code number. It implements the gray code conversion by XORing adjacent bits.

Uploaded by

Gurdeep Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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comparator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Comp is
Port ( Input1, Input2 : in std_logic_vector(3 downto 0);
GR : out STD_LOGIC;
SR : out STD_LOGIC;
EQ : out STD_LOGIC);
end Comp;

architecture Behavioral of Comp is

begin
GR<='1' when( Input1>Input2)
else '0';
SR<='1' when( Input1<Input2)
else '0';
EQ<='1' when( Input1=Input2)
else '0';

end Behavioral;

binary to gray
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BinaryToGray is
Port ( Binary: in std_logic_vector(3 downto 0);
Gray: out std_logic_vector(3 downto 0) );
end BinaryToGray;

architecture Behavioral of BinaryToGray is

begin
Gray(3) <= Binary(3);
Gray(2) <= Binary(3) xor Binary(2);
Gray(1) <= Binary(2) xor Binary(1);
Gray(0) <= Binary(1) xor Binary(0);

end Behavioral;

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