AND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity and1 is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end and1;
architecture Behavioral of and1 is
begin
c <= a and b;
end Behavioral;
OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity or1 is
Port ( x : in std_logic;
y : in std_logic;
z : out std_logic);
end or1;
architecture Behavioral of or1 is
begin
z <= x or y;
end Behavioral;
NAND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nand2 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end nand2;
architecture Behavioral of nand2 is
begin
y<=not (a and b and c);
end Behavioral;
HALF ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ha is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
co : out std_logic);
end ha;
architecture Behavioral of ha is
begin
--s <= a xor b xor c;
--co <= (a and b)or(b and c)or (a and c);
s <= a xor b;
co <= a and b;
end Behavioral;
FULL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fa is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
co : out std_logic);
end fa;
architecture Behavioral of fa is
component ha
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
co : out std_logic);
end component;
component or1
port ( x: in std_logic;
y: in std_logic;
z: out std_logic);
end component;
signal t1,t2,t3 : std_logic;
begin
ha1:ha port map(a,b,t1,t2);
ha2 : ha port map (t1,c,s,t3);
or2:or1 port map(t2,t3,co);
end Behavioral;
PARALLEL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pa is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
co : out std_logic);
end pa;
architecture Behavioral of pa is
component ha
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
co : out std_logic);
end component;
component fa
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
co : out std_logic);
end component;
signal t:std_logic_vector(2 downto 0);
begin
ha1: ha port map (a(0),b(0),s(0),t(0));
fa1: fa port map (a(1),b(1),t(0),s(1),t(1));
fa2: fa port map (a(2),b(2),t(1),s(2),t(2));
fa3: fa port map (a(3),b(3),t(2),s(3),co);
end Behavioral;
D FLIP FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dff is
Port ( d : in std_logic;
clk : in std_logic;
q : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process(d,clk)
begin
if(clk='0'and clk'event) then
q<=d;
end if;
end process;
end Behavioral;
REGISTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg is
Port ( a : in std_logic;
clk : in std_logic;
b : out std_logic);
end reg;
architecture Behavioral of reg is
component dff
Port ( d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
signal t0,t1:std_logic;
begin
ff1:dff port map(a,clk,t0);
ff2:dff port map(t0,clk,t1);
ff3:dff port map(t1,clk,b);
end Behavioral;
