Place & Route

Cadence Innovus place & route

Verilog sim
CS/ECE 6710 Tool Suite
Behavioral
Synopsys
Verilog Design Compiler
Structural
Verilog
Cadence
Your
EDI
Library
Circuit Verilog sim
Layout
Cadence LVS Cadence
CCAR
Virtuoso Composer
AutoRouter Layout-XL
Layout Schematic

Ø 1
 In the CAD Book
w  Chapter 11 on SOC Encounter Place and Route
n  That’s an old name – In 2015 they changed it to
Cadence EDI (Encounter Design Implementation)
n  Now that’s an old name – it’s now called Cadence

Innovus…

n  Need additional information about your cells

w  Specifically, a .lef (physical place &route) file
l  This
basically describes the abstract views of your cells
in a way that place and route understands…

Encounter Innovus Place & Route

1.  Import Design g

l Verilo
2.  Floorplan ra
uctu psys)
s tr o
3.  Power plan o n vert m Syn layout
C (Fro al
p h ysic
4.  Place cells Into
5.  Synthesize clock tree?
6.  Route signal nets
7.  Verify results
8.  Write out results

Ø 2
 Innovus Usage
w  Need…
n  Structural Verilog <design>.v (from Synopsys)
n  Structural Verilog timing, <design>.sdc (from Synopsys)
n  Library timing information <library>.lib (from Liberate)
n  Library layout information <library>.lef (from Abstract)
n  6710.tcl file with Innovus variable settings (from /uusoc/facility/
cad_common/local/class/6710/F17/cadence/Innovus
n  mmmc.tcl file with timing information (multi-mode multi-corner
timing)
w  Make a new dir for Innovus... (I call mine INN)
w  Call with cad-inn

cad-innFlow
1.  Import Design
n  .v, .sdc, .lib, .lef, mmmc.tcl
2.  Source 6710.tcl file to get things set up
3.  Floorplan
n  Choose physical size, ratio, utilization percentage,
etc.
4.  Power plan
n  rings, stripes, row-routing (sroute)

Ø 3
 cad-edi Flow
5.  Placement
n  place cells in the rows
n  …with optimization step
6.  Synthesize clock tree?
n  use your buf and inv footprint cells
n  maybe not needed – Synopsys already did this…
7.  Global routing
n  NanoRoute
n  …with optimization step

cad-edi Flow
8.  Add filler cells
n  Fill in the spots in the row with no cells
n  Adds NWELL for continuity
9.  Write out results
n  <name>.def can be imported as layout
n  <name>_innovus.v is the placed and routed
Verilog dscription
n  Write out timing information if
desired. .spef, .sdc, _innovus.lib

Ø 4
 To start…

The set of files needed…

mmmc.tcl timing description

mmmc.tcl
# set the name of your .lib file (e.g. Lib6710_01.lib)
# You can create multiple library sets if you have multiple libraries
# such as fast, slow, and typ
# If you have multiple .lib files put them in a [list lib1 lib2] structure
create_library_set -name typical_lib \
-timing {!!your-lib-file!!.lib}
# Specify the .sdc timing constraint file to use
# This file comes from Synopsys synthesis. (e.g. design_struct.sdc)
create_constraint_mode -name typical_constraint \
-sdc_files {!!your-sdc-file!!.sdc}
…

Ø 5
 mmmc.tcl
#################################################################
# Below here you shouldn't have to change, unless you're doing
# something different than the basic EDI run...
#################################################################
# Create an RC_corner that has specific capacatance info.
create_rc_corner -name typical_rc\
…
# Define delay corners and analysis views.
create_delay_corner -name typical_corner \
-library_set {typical_lib} \
-rc_corner {typical_rc}
create_analysis_view -name typical_view \
-constraint_mode {typical_constraint} \
-delay_corner {typical_corner}
# Now define which analysis view to use for setup and for hold.
set_analysis_view -setup {typical_view} -hold {typical_view}

cad-inn gui

Ø 6
 Design
Import

Design Import

Ø 7
 Result of Successful Import

Type command to
Source 6710.tcl the Innovus command
line

Ø 8
Floorplan

Specify -> Floorplan

Floorplan

Specify -> Floorplan

Ø 9
 Floor
plan

Power Rings

Power -> Power Planning

Ø 10
 Power
Stripes

Power
Stripes

Annoying… This will

start the stripes from
0 offset…

Ø 11
Power
Stripes

Power
Rings
and
Stripes

Ø 12
 Power
Rings
and
Stripes

Select and remove

the leftmost
power stripe…

Route -> Sroute

Sroute to connect things up

Ø 13
 Route -> Sroute

Sroute to connect rows to power

Place -> Place Standard Cell...

Place cells

Ø 14
 Place cells

Make sure
to have your
I/O signals
placed!

Placed Cells…

Ø 15
 Clock Tree Synthesis…
w  Probably don’t have to do this explicitly
n  Synopsys has already generated a clock tree
during synthesis…
n  Innovus can make a new one for you, and might

have better information because of floorplan and

placement…
n  But, seems like it can’t be done at the GUI. Only

through scripts…

NanoRoute

Route -> NanoRoute -> Route

Ø 16
 Routed circuit

Routed circuit – another example..

Ø 17
Routed circuit – yet another example..
eration and could become a viable real-time alte
image-based texturing.

5. REFERENCES
[1] A. A. Apodoca and L. Gritz. Advanced Rend
Creating CGI for Motion Pictures. Morgan K
Publishers, 2000.
[2] R. Bridson, J. Hourihan, and M. Nordenstam
Curl-Noise for Procedural Fluid Flow. ACM
Transactions on Graphics (SIGGRAPH ’07)
2007.
[3] R. L. Cook and T. DeRose. Wavelet Noise. A
Transactions on Graphics (SIGGRAPH ’05)
24(3):803–811, 2005.
[4] T. Erber and G. M. Hockney. Equilibrium
Configurations of N Equal Charges On a Sp
Journal of Physics A: Mathematical and Gen
24(23):L1369–L1377, 1991.
[5] S. Gustavson. Simplex Noise Demystified. In
http://websta↵.itn.liu.se/⇠stegu/simplexnois
[6] A. Kensler, A. Knoll, and P. Shirley. Better
Noise. Technical Report UUSCI-2008-001, SC
Figure 6: Placed and routed circuit implementing our im- Institute, University of Utah, 2008.
proved noise function as a four-stage pipeline (105kµm2 ). [7] J. P. Lewis. Algorithms for Solid Noise Synth
This image is a screen capture from Cadence SOC Encounter ACM SIGGRAPH Computer Graphics, 23(3
and shows only metal routing layers. 1989.
Place -> Physical Cell -> Add [8] Filler
F. K. Musgrave. Fractal Solid Textures: Som
per second on a single core of 2.8GHz Core 2 Duo. Our final Examples. In Texturing and Modeling: A Pro
Approach, chapter 15, pages 447–487. Morga
Add Filler Cells
design uses three 256 entry hash tables where, to avoid ad-
ditional adders, each table entry encodes the hash value for Kaufmann Publishers, third edition, 2003.
the input, and for the input + 1 (see Figure 4). We also use [9] M. Olano. Modified Noise for Evaluation on
eight copies of a 64 entry gradient table, where each gradient Hardware. In Proceedings of Graphics Hardw
is a three element vector of fixed point values. pages 105–110, 2005.
As graphics pipelines demand more and more memory [10] D. Peachey. Building Procedural Textures. I
bandwidth we believe that providing a method for high qual- Texturing and Modeling: A Procedural Appro
ity textures through a hardware accelerated noise function chapter 2, pages 7–94. Morgan Kaufmann Pu
provides a good trade-o↵. Much of the bandwidth of high- third edition, 2003.
performance graphics chips is devoted to image-based (look- [11] K. Perlin. An Image Synthesizer. ACM SIGG
up) texturing. Procedural textures using noise o↵er an al- Computer Graphics, 19(3):287–296, 1985.
ternative that trades memory bandwidth for computation. [12] K. Perlin. In the beginning: The Pixel Strea
The scene in Figure 1 is an example that uses an average of In M. Olano, editor, Real-Time Shading SIG
552 calls to the noise function per shading sample. 37.2% of Course Notes, chapter 2. 2001.
the total execution time for rendering the image was spent in [13] K. Perlin. Noise Hardware. In M. Olano, edi
the evaluation of noise for various aspects of the image. The Real-Time Shading SIGGRAPH Course Note
textures on all of the surfaces and the smoke use noise to im- chapter 9. 2001.
prove visual quality. The use of image-based textures would [14] K. Perlin. Improving Noise. ACM Transactio
require far more memory bandwidth than our approach. Graphics (SIGGRAPH ’02), 21(3):681–682, 2
Admittedly, many applications would see more modest [15] K. Perlin. Implementing Improved Perlin No
improvements in performance than the specific scene used GPU Gems, chapter 5, pages 73–85. Addison
here which is designed to demonstrate heavy use of noise- 2004.
based textures. However, any time noise is used there would
[16] K. Perlin and E. Ho↵ert. Hypertexture. ACM
be a speedup using our hardware over a software implemen-
SIGGRAPH Computer Graphics, 23(3):253–
tation. At least one place where this could encourage vi-
sually complex images at a reduced memory bandwidth re- [17] P. Shirley and R. K. Morley. Realistic Ray T
quirement would be video games. Games typically use very K. Peters, Natick, MA, 2003.
large image textures to avoid the appearance of repetition. [18] J. Spjut, D. Kopta, S. Boulos, S. Kellis, and
While we do not have specific projections of memory band- E. Brunvand. TRaX: A Multi-Threaded Arch
width savings, it is well known that the large image tex- for Real-Time Ray Tracing. In 6th IEEE Sym
tures are a significant fraction of the memory bandwidth in on Application Specific Processors (SASP), 2
video games. Our design could increase the performance of [19] T. Whitted. An Improved Illumination Mode
applications that use noise by as much as 50% and would Shaded Display. Communications of the ACM
be a good step toward high quality procedural texture gen- 23(6):343–349, 1980. Ø 18

462
 Verify connectivity

Verify DRC (only wires!)

Ø 19
 Write Results...
Design -> Save -> Netlist
(structural Verilog)

Design -> Save -> DEF

(layout information)

Innovus Scripting
w  Usual warnings – know what’s going on!
w  Use top.tcl as a starting point
n  And the other .tcl files it calls...
w  Innovus has a floorplanning stage that you
may want to do by hand
n  write another script to read in the floorplan and
go from there...
w  Use innovus.cmd to see the text versions of
what you did in the GUI...

Ø 20
 Innovus Scritping Usage
w  Need structural Verilog, struct.sdc, library.lib, library.lef
w  Make a new dir for Innovus... (I call mine INN)
w  Make an mmmc.tcl file with timing/library info
w  <design>.globals has design-specific settings
n  use basename.globals as starting point.

w  Usual warnings about scripting…

n  top.tcl and other *.tcl are in the class directory as starting points
n  /uusoc/facility/cad_common/local/class/6710/F17/cadence/Innovus

w  Call with cad-inn, but this time source scripts

instead of using GUI

Innovus Scripting Starting Point

Note the same six files as before, but now adding <basename>.globals,
and all the other .tcl files from
/uusoc/facility/cad_common/local/class/6710/F17/cadence/Innovus

Ø 21
 <basename>.globals
#
# Set the name of your structural Verlog file
# This comes from Synopsys synthesis
set init_verilog {!!your-file-name.v!!}
# Set the name of your top module
set init_design {!!your-top-module-name!!}
# Set the name of your .lef file
# This comes from ELC
set init_lef_file {!!your-file-name.lef!!}
…

<basename>.globals

Ø 22
 <basename>.globals
##############################################################
# below here you probably don't have to change anything
##############################################################
# Set the name of your "muli-mode-multi-corner data file
# You don't need to change this unless you're using a
# different mmmc.tcl file.
set init_mmmc_file {mmmc.tcl}
# Some helpful input mode settings
set init_import_mode {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1 }
# Set the names of your gnd and power nets
set init_gnd_net {gnd!}
set init_pwr_net {vdd!}

top.tcl

Ø 23
 top.tcl

top.tcl
#############################################################
# You may not have to change things below this line - but check!
#
# You may want to do floorplanning by hand in which case you
# have some modification to do!
#############################################################

# Set some of the power and stripe parameters - you can change
# these if you like - in particular check the stripe space (sspace)
# and stripe offset (soffset)! These values should be divisible by 0.3
# so that they’ll fall on the lambda grid
set pwidth 9.9 ;# power rail width
set pspace 1.8 ;# power rail space
set swidth 4.8 ;# power stripe width
set sspace 210 ;# power stripe spacing
set soffset 207 ;# power stripe offset to first stripe

Ø 24
 top.tcl
#
# Set the flag for EDIto automatically figure out buf, inv, etc.
set dbgGPSAutoCellFunction 1

# Import design and floorplan

# If the config file is not named $basename.globals, edit this line.
source $BASENAME.globals
init_design

.globals file
w  Same .globals file that we saw before with
the walk-through
w  Start with basename.globals and mmmc.tcl
from the
/uusoc/facility/cad_common/local/class/
6710/F17/cadence/Innovus directory
w  This describes the .lib, .lef, etc. information

Ø 25
 top.tcl
# source the files that operate on the circuit
source fplan.tcl ;# create the floorplan (might be done by hand...)
source pplan.tcl ;# create the power rings and stripes
source place.tcl ;# Place the cells and optimize (pre-CTS)
source cts.tcl ;# Create the clock tree, and optimize (post-CTS)
source route.tcl ;# Route the design using nanoRoute
source verify.tcl ;# Verify the design and produce output files
exit

fplan.tcl
puts "-------------Floorplanning---------------"
#
# Make a floorplan - this works fine for projects that are all
# standard cells and include no blocks that need hand placement...
setDrawView fplan
setFPlanRowSpacingAndType $rowgap 2
floorPlan -site core -r $aspect $usepct \
$coregap $coregap $coregap $coregap
fit

#
# Save design so far
saveDesign ${BASENAME}_fplan.enc
saveFPlan ${BASENAME}.fp
puts "--------------Floorplanning done----------

Ø 26
 pplan.tcl
puts "-------------Power Planning----------------"
puts "-------Making power rings------------------"
#
# Make power and ground rings - $pwidth microns wide
# with $pspace spacing between them and centered in the channel
addRing -spacing_bottom $pspace \
-width_left $pwidth \
-width_bottom $pwidth \
-width_top $pwidth \
-spacing_top $pspace \
-layer_bottom metal1 \
-center 1 \
-stacked_via_top_layer metal3 \
...

pplan.tcl
puts "------making power stripes-----------------”
# Make Power Stripes. This step is optional. If you keep it
# in remember to check the stripe spacing
# (set-to-set-distance = $sspace) and stripe offset
# (xleft-offset = $soffset))
addStripe -block_ring_top_layer_limit metal3 \
-max_same_layer_jog_length 3.0 \
-snap_wire_center_to_grid Grid \
-padcore_ring_bottom_layer_limit metal1 \
…
# Use the special-router to route the vdd! and gnd! nets
sroute -allowJogging 1

# Save the design so far

saveDesign ${BASENAME}_pplan.enc
puts "-------------Power Planning done---------"

Ø 27
 top.tcl
Read the script...
place
pre-CTS optimization
clock tree synthesis
post-CTS optimization
routing
post-ROUTE optimization
add filler
write out results

Report Files
w  <topname>_Conn_regular.rpt
w  <topname>_Conn_special.rpt
w  <topname>_Geom.rpt

w  Want 0 violations in all

n  If you have 1 or 2 in the geometry you might be
able to fix them easily in Virtuoso...

Ø 28
 Read back to Virtuoso
w  Make a new library to hold the placed and
routed version
w  Commands to read Verilog and DEF are in
the CIW, not Library Manager…
n  Once you have both schematic and layout, you
can DRC-Extract-LVS to make sure it’s all OK!

Import Verilog
In CIW
File -> Import -> Verilog

Make SURE you import

The Verilog from Innovus!

Ø 29
Schematic view

Symbol view

Ø 30
 Read DEF

File -> Import -> DEF

Resulting layout view

Problem: all
cells are
abstract views!

Ø 31
Change abstract to layout cellviews
Edit -> Search

DRC, Extract

Change abstract to layout cellviews

Ø 32
 LVS Result

Yay!!!

Summary
w  Behavioral -> Structural -> Layout
w  Can be automated by scripting, but make
sure you know what you’re doing
n  Synopsys documentation for design_compiler
n  innovus.cmd (and documentation) for Innovus
w  End up with placed and routed core layout
n  or BLOCK for later use...

Ø 33