ST

Sitronix Dot Matrix LCD Controller/Driver

ST7066

Features

!" 5 x 8 and 5 x 11 dot matrix possible !" Programmable duty cycles

!" Low power operation support: -- 1/8 for one line of 5 x 8 dots with cursor
-- 2.7 to 5.5V -- 1/11 for one line of 5 x 11 dots & cursor
!" Wide range of LCD driver power -- 1/16 for two lines of 5 x 8 dots & cursor
-- 3.0 to 11V !" Wide range of instruction functions:
!" Correspond to high speed MPU bus interface Display clear, cursor home, display on/off,
-- 2 MHz (when VCC = 5V) cursor on/off, display character blink, cursor
!" 4-bit or 8-bit MPU interface enabled shift, display shift
!" 80 x 8-bit display RAM (80 characters max.) !" Pin function compatibility with HD44780,
!" 13,200-bit character generator ROM for a total KS0066 and SED1278
of 240 character fonts(5 x 8 dot or 5 x 11 dot) !" Automatic reset circuit that initializes the
!" 64 x 8-bit character generator RAM controller/driver after power on
-- 8 character fonts (5 x 8 dot) !" Internal oscillator with external resistors
-- 4 character fonts (5 x 11 dot) !" Low power consumption
!" 16-common x 40-segment liquid crystal display !" QFP80 and Bare Chip available
driver

Description
The ST7066 dot-matrix liquid crystal display 240 5x8(5x11) dot character fonts and 325 x 11 dot
controller and driver LSI displays alphanumeric, character fonts for a total of 240 different character
Japanese kana characters, and symbols. It can be fonts. The low power supply (2.7V to 5.5V) of the
configured to drive a dot-matrix liquid crystal display ST7066 is suitable for any portable battery-driven
under the control of a 4- or 8-bit microprocessor. product requiring low power dissipation.
Since all the functions such as display RAM,
character generator, and liquid crystal driver, required The ST7066 LCD driver consists of 16 common
for driving a dot-matrix liquid crystal display are signal drivers and 40 segment signal drivers which
internally provided on one chip, a minimal system can can extend display size by cascading segment driver
be interfaced with this controller/driver. ST7065 or ST7063. The maximum display size can
be either 80 characters in 1-line display or 40
The ST7066 has pin function compatibility with the characters in 2-line display. A single ST7066 can
HD44780, KS0066U and SED1278 that allows the display up to one 8-character line or two 8-character
user to easily replace it with an ST7066. The ST7066 lines.
character generator ROM is extended to generate

Product Name Support Character

ST7066-0A English / Japan
ST7066-0B English / European

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ST7066
Block Diagram

OSC1 OSC2 CL1

CL2
Reset M
Circuit
CPG Timing
Generator

Instruction
Register (IR) COM1 to
RS MPU Display 16-bit Common COM16
Interface data RAM shift Signal
RW (DDRAM) registe Driver
80x8 bits r
E Instruction
Decoder

SEG1 to
40-bit 40-bit Segment SEG40
shift latch Signal
Address registe circuit Driver
Counter r
DB4 to
DB7
Input/
Output
Data
DB0 to Buffer
Register LCD Drive
DB3 (DR) Voltage
Selector

Busy
Flag

Character Character
generator generator Cursor
RAM ROM and
(CGRAM) (CGROM) Blink
64 bits 9,920 bits controller

Parallel/Serial converter
GND and
Attribute Circuit

Vcc

V1 V2 V3 V4 V5

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ST7066

Pad Arrangement

1 80 64

ST7066

"ST7066" Marking : easy to find the PAD

(0,0)

Chip Size : 2300x3000µm

Coordinate : Pad Center
Origin : Chip Center
Min Pad Pitch:120µm
Pad Size : 96x96µm

24 41

Subtrate:VDD

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Pad Location Coordinates

Pad No. Function X Y Pad No. Function X Y

1 SEG22 -1040 1400 41 DB2 1040 -1400

2 SEG21 -1040 1270 42 DB3 1040 -1270
3 SEG20 -1040 1140 43 DB4 1040 -1140
4 SEG19 -1040 1020 44 DB5 1040 -1020
5 SEG18 -1040 900 45 DB6 1040 -900
6 SEG17 -1040 780 46 DB7 1040 -780
7 SEG16 -1040 660 47 COM1 1040 -660
8 SEG15 -1040 540 48 COM2 1040 -540
9 SEG14 -1040 420 49 COM3 1040 -420
10 SEG13 -1040 300 50 COM4 1040 -300
11 SEG12 -1040 180 51 COM5 1040 -180
12 SEG11 -1040 60 52 COM6 1040 -60
13 SEG10 -1040 -60 53 COM7 1040 60
14 SEG9 -1040 -180 54 COM8 1040 180
15 SEG8 -1040 -300 55 COM9 1040 300
16 SEG7 -1040 -420 56 COM10 1040 420
17 SEG6 -1040 -540 57 COM11 1040 540
18 SEG5 -1040 -660 58 COM12 1040 660
19 SEG4 -1040 -780 59 COM13 1040 780
20 SEG3 -1040 -900 60 COM14 1040 900
21 SEG2 -1040 -1020 61 COM15 1040 1020
22 SEG1 -1040 -1140 62 COM16 1040 1140
23 GND -1040 -1270 63 SEG40 1040 1270
24 OSC1 -1040 -1400 64 SEG39 1040 1400
25 OSC2 -910 -1400 65 SEG38 910 1400
26 V1 -780 -1400 66 SEG37 780 1400
27 V2 -660 -1400 67 SEG36 660 1400
28 V3 -540 -1400 68 SEG35 540 1400
29 V4 -420 -1400 69 SEG34 420 1400
30 V5 -300 -1400 70 SEG33 300 1400
31 CL1 -180 -1400 71 SEG32 180 1400
32 CL2 -60 -1400 72 SEG31 60 1400
33 Vcc 60 -1400 73 SEG30 -60 1400
34 M 180 -1400 74 SEG29 -180 1400
35 D 300 -1400 75 SEG28 -300 1400
36 RS 420 -1400 76 SEG27 -420 1400
37 RW 540 -1400 77 SEG26 -540 1400
38 E 660 -1400 78 SEG25 -660 1400
39 DB0 780 -1400 79 SEG24 -780 1400
40 DB1 910 -1400 80 SEG23 -910 1400

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ST7066
Pin Functions

NAME NUMBER I/O INTERFACED WITH FUNCTION

Select registers.
0: Instruction register (for write) Busy flag:
RS 1 I MPU address counter (for read)
1: Data register (for write and read)
Select read or write.
R/W 1 I MPU 0: Write
1: Read
E 1 I MPU Starts data read/write.
Four high order bi-directional tristate data bus
pins. Used for data transfer and receive
DB4 to DB7 4 I/O MPU between the MPU and the ST7066. DB7 can
be used as a busy flag.
Four low order bi-directional tristate data bus
pins. Used for data transfer and receive
DB0 to DB3 4 I/O MPU between the MPU and the ST7066.
These pins are not used during 4-bit operation.
Clock to latch serial data D sent to the
CL1 1 O Extension driver
extension driver
CL2 1 O Extension driver Clock to shift serial data D
Switch signal for converting the liquid crystal
M 1 O Extension driver
drive waveform to AC
Character pattern data corresponding to each
D 1 O Extension driver
segment signal
Common signals that are not used are changed
to non-selection waveform. COM9 to COM16
COM1 to COM16 16 O LCD are non-selection waveforms at 1/8 duty factor
and COM12 to COM16 are non-selection
waveforms at 1/11 duty factor.
SEG1 to SEG40 40 O LCD Segment signals
Power supply for LCD drive
V1 to V5 5 - Power supply
VCC - V5 = 11 V (Max)
VCC , GND 2 - Power supply VCC : 2.7V to 5.5V, GND: 0V
When crystal oscillation is performed, a resistor
Oscillation must be connected externally. When the pin
OSC1, OSC2 2
resistor clock input is an external clock, it must be input to OSC1.

Note:
1. Vcc>=V1>=V2>=V3>=V4>=V5 must be maintained
2. Two clock options:

R=91K
(Vcc=5V)

OSC1 OSC2 OSC1 OSC2

1 1 1 1
R Clock
input

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ST7066
FUNCTION DESCRIPTION

System Interface
This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by DL
bit in the instruction register.

During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).

The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM,
target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into
RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is
transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read
instruction data.

To select register, use RS input pin in 4-bit/8-bit bus mode.

Table 1. Various kinds of operations according to RS and R/W bits.

RS RW Operation
L L Instruction Write operation (MPU writes Instruction code
into IR)
L H Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
H L Data Write operation (MPU writes data into DR)
H H Data Read operation (MPU reads data from DR)

Busy Flag (BF)

When BF = "High”, it indicates that the internal operation is being processed. So during this time the next instruction
cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7
port. Before executing the next instruction, be sure that BF is not High.

Address Counter (AC)

Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.

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Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 x 8
bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general
data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display.

The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal.

!" 1-line display (N = 0) (Figure 2)

When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the ST7066, 8 characters are displayed. See Figure 3.
When the display shift operation is performed, the DDRAM address shifts. See Figure 3.

High Order Low Order

bits bits Example: DDRAM Address 4F

AC AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 1

Figure 1 DDRAM Address

Display
Position 1 2 3 4 5 6 78 79 80
(Digit) 00 01 02 03 04 05 ……………….. 4D 4E 4F
DDRAM Address

Figure 2 1-
1-Line Display

Display
Position 1 2 3 4 5 6 7 8
00 01 02 03 04 05 06 07
DDRAM
Address

For 01 02 03 04 05 06 07 08
Shift Left

For 4F 00 01 02 03 04 05 06
Shift Right

Figure 3 1-
1-Line by 8-
8-Character Display
Display Example

!" 2-line display (N = 1) (Figure 4)

Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed from the head. Note that
the first line end address and the second line start address are not consecutive. For example, when just the ST7066 is
used, 8 characters × 2 lines are displayed. See Figure 5.

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When display shift operation is performed, the DDRAM address shifts. See Figure 5.

Display 1 2 3 4 5 6
38 39 40
Position
00 01 02 03 04 05 ……………….. 25 26 27
DDRAM
Address 40 41 42 43 44 45 ……………….. 65 66 67
(hexadecimal)

Figure 4 2-
2-Line Display

Display
Position 1 2 3 4 5 6 7 8

DDRAM 00 01 02 03 04 05 06 07
Address
40 41 42 43 44 45 46 47

For 01 02 03 04 05 06 07 08
Shift Left
41 42 43 44 45 46 47 48

For
Shift Right 27 00 01 02 03 04 05 06

67 40 41 42 43 44 45 46

Figure 5 2-
2-Line by 8-
8-Character Display Example

Case 2: For a 16-character × 2-line display, the ST7066 can be extended using one 40-output
extension driver. See Figure 6.
When display shift operation is performed, the DDRAM address shifts. See Figure 6.

Display
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Position
DDRAM 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Address
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

For 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
Shift
Left 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50

For 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
Shift
Right 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E

Figure 6 2-
2-Line by 16-
16-Character Display Example

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Character Generator ROM (CGROM)
The character generator ROM generates 5 x 8 dot or 5 x 11 dot character patterns from 8-bit character codes. It can
generate 208 5 x 8 dot character patterns and 32 5 x 11 dot character patterns. User-defined character patterns are
also available by mask-programmed ROM.

Character Generator RAM (CGRAM)

In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character
patterns can be written, and for 5 x 11 dots, four character patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character
patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used
for display can be used as general data RAM.

Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.

LCD Driver Circuit

LCD Driver circuit has 16 common and 40 segment signals for LCD driving. Data from CGRAM/CGROM is
transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. When each common is selected
by 16 bit common register, segment data also output through segment driver from 40 bit segment latch. In case of
1-line display mode, COM1 ~ COM8 have 1/8 duty or COM1 ~ COM11 have 1/11duty , and in 2-line mode, COM1 ~
COM16 have 1/16 duty ratio.

Cursor/Blink Control Circuit

It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the
display data RAM address set in the address counter.

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Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: 0A)

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Table 4(Cont.) (ROM Code: 0B)

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Table 4(Cont.) (ROM Code: 0E)

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ST7066
Character Code CGRAM Character Patterns
(DDRAM Data) Address (CGRAM Data)
b7 b6 b5 b4 b3 b3 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 0 1 0 0 1 0 0
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 1 0 0 1 0 0
0 0 0 0 - 0 0 0 - - -
0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 1 0 0 1 0 0
0 0 0 1 1 0 0 0 1 0 0
0 0 0 1 1 1 0 0 0 0 0
0 0 1 0 0 0 1 1 1 1 0
0 0 1 0 0 1 1 0 0 0 1
0 0 1 0 1 0 1 0 0 0 1
0 0 1 0 1 1 1 1 1 1 0
0 0 0 0 - 0 0 0 - - -
0 0 1 1 0 0 1 0 1 0 0
0 0 1 1 0 1 1 0 0 1 0
0 0 1 1 1 0 1 0 0 0 1
0 0 1 1 1 1 0 0 0 0 0

Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data)
Notes:
1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding
to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line
regardless of the cursor presence.
3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are
all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either
character code 00H or 08H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
“-“: Indicates no effect.

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Instructions

There are four categories of instructions that:

!" Designate ST7066 functions, such as display format, data length, etc.
!" Set internal RAM addresses
!" Perform data transfer with internal RAM
!" Others
Instruction Table:
Instruction Code Description
Instruction DB DB DB DB DB DB DB DB Description Time
RS RW
7 6 5 4 3 2 1 0 (270KHZ)

Clear Write "20H" to DDRAM. and set

0 0 0 0 0 0 0 0 0 1 1.52 ms
Display DDRAM address to "00H" from AC
Set DDRAM address to "00H" from AC
Return and return cursor to its original position
0 0 0 0 0 0 0 0 1 x 1.52 ms
Home if shifted. The contents of DDRAM are
not changed.
Sets cursor move direction and
Entry Mode specifies display shift. These operations
0 0 0 0 0 0 0 1 I/D S 37 us
Set are performed during data write and
read.
D=1: entire display on
Display
0 0 0 0 0 0 1 D C B C=1: cursor on 37 us
ON/OFF
B=1: cursor position on
Cursor or Set cursor moving and display shift
Display 0 0 0 0 0 1 S/C R/L x x control bit, and the direction, without 37 us
Shift changing DDRAM data.
DL: interface data is 8/4 bits
Function
0 0 0 0 1 DL N F x x NL: number of line is 2/1 37 us
Set
F: font size is 5x11/5x8
Set Set CGRAM address in address counter
AC AC AC AC AC AC
CGRAM 0 0 0 1 37 us
5 4 3 2 1 0
address
Set DDRAM AC AC AC AC AC AC AC Set DDRAM address in address counter
0 0 1 37 us
address 6 5 4 3 2 1 0
Whether during internal operation or not
Read Busy
AC AC AC AC AC AC AC can be known by reading BF. The
flag and 0 1 BF 0 us
6 5 4 3 2 1 0 contents of address counter can also be
address
read.
Write data Write data into internal RAM
1 0 D7 D6 D5 D4 D3 D2 D1 D0 37 us
to RAM (DDRAM/CGRAM)
Read data Read data from internal RAM
1 1 D7 D6 D5 D4 D3 D2 D1 D0 37 us
from RAM (DDRAM/CGRAM)

Note:
Be sure the ST7066 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7066.
If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction
will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction
execution time.

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ST7066
INSTRUCTION DESCRIPTION
!" Clear Display

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 0 0 0 0 0 1

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"
into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first
line of the display. Make entry mode increment (I/D = "1").
!" Return Home

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 0 0 0 0 1 x

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return
cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
!" Entry Mode Set

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 0 0 0 1 I/D S

Set the moving direction of cursor and display.

I/D : Increment / decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
* CGRAM operates the same as DDRAM, when read from or write to CGRAM.
S: Shift of entire display
When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S =
"High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift
left, I/D = "0" : shift right).

S I/D DESCRIPTION
H H Shift the display to the left
H L Shift the display to the right

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!" Display ON/OFF

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 0 0 1 D C B

Control display/cursor/blink ON/OFF 1 bit register.

D : Display ON/OFF control bit

When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C : Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B : Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display character at
the cursor position.
When B = "Low", blink is off.
!" Cursor or Display Shift

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 0 1 S/C R/L x x

Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line.
Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each
line shifted individually. When display shift is performed, the contents of address counter are not changed.
S/C R/L Description AC Value
L L Shift cursor to the left AC=AC-1
L H Shift cursor to the right AC=AC+1
H L Shift display to the left. Cursor follows the display shift AC=AC
H H Shift display to the right. Cursor follows the display shift AC=AC

!" Function Set

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 1 DL N F x x

Control display/cursor/blink ON/OFF 1 bit register.

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ST7066

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select
8-bit or 4-bit bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N : Display line number control bit
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
F : Display font type control bit
When F = "Low", it means 5 x 8 dots format display mode
When F = "High", 5 x11 dots format display mode.
No. of Display
N F Character Font Duty Factor
Lines
L L 1 5x8 1/8
L H 1 5x11 1/11
H x 2 5x8 1/16

!" Set CGRAM Address

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

Code

Set CGRAM address to AC.

This instruction makes CGRAM data available from MPU.
!" Set DDRAM Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Code

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU.
When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".
In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and
DDRAM address in the 2nd line is from "40H" to "67H".

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!" Read Busy Flag and Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

Code

When BF = “High”, indicates that the internal operation is being processed.So during this time the next
instruction cannot be accepted.
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
!" Write Data to CGRAM or DDRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 1 0 D7 D6 D5 D4 D3 D2 D1 D0

Write binary 8-bit data to DDRAM/CGRAM.

The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC
direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to
the entry mode.
!" Read Data from CGRAM or DDRAM

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 1 1 D7 D6 D5 D4 D3 D2 D1 D0

Read binary 8-bit data from DDRAM/CGRAM.

The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not determined.
If you read RAM data several times without RAM address set instruction before read operation, you can get
correct RAM data from the second, but the first data would be incorrect, because there is no time margin to
transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address
set instruction : it also transfer RAM data to output data register. After read operation address counter is
automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift
may not be executed correctly.
* In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC
indicates the next address position, but you can read only the previous data by read instruction.

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ST7066

Reset Function

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes the ST7066 when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state
until the initialization ends (BF = 1). The busy state lasts for 40 ms after VCC rises to 4.5 V.
1. Display clear
2. Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
F = 0; 5x8 dot character font
3. Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4. Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
Note:
If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail
to initialize the ST7066. For such a case, initialization must be performed by the MPU as
explain by the following figure.

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ST7066
8-bit Interface (fosc=280KHz)

POWER ON

Wait time >40mS

After Vcc >4.5V

Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 1 N F X X

Wait time >37uS

Display ON/OFF control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 1 D C B

Wait time >37uS

Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 1

Wait time >1.53mS

Entry mode set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 1 I/D S

Initialization end

V1.5 20 2000/8/03
ST7066
4-bit Interface (fosc=280KHz)

POWER ON

Wait time >40mS

After Vcc >4.5V

Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 X X X X
0 0 0 0 1 0 X X X X
0 0 N F X X X X X X

Wait time >37uS

Display ON/OFF control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 1 D C B X X X X

Wait time >37uS

Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 0 0 0 1 X X X X

Wait time >1.53mS

Entry mode set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 0 1 I/D S X X X X

Initialization end

V1.5 21 2000/8/03
ST7066
Interfacing to the MPU

The ST7066 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or
8-bit MPU.
!" For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are
disabled. The data transfer between the ST7066 and the MPU is completed after the 4-bit data has been
transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are
transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one
instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag
and address counter data.
!" For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

Supply Voltage for LCD Drive

There are different voltages that supply to ST7066’s pin (V1 - V5) to obtain LCD drive waveform. The relations of the
bias, duty factor and supply voltages are shown as below:
Duty Factor
1/8, 1/11 1/16
Bias
Supply Voltage 1/4 1/5
V1 Vcc - 1/4VLCD Vcc - 1/5VLCD
V2 Vcc - 1/2VLCD Vcc - 2/5VLCD
V3 Vcc - 1/2VLCD Vcc - 3/5VLCD
V4 Vcc - 3/4VLCD Vcc - 4/5VLCD
V5 Vcc - VLCD Vcc- VLCD

1/4 bias 1/5 bias

(1/8, 1/11 duty (1/16 duty
cycle) cycle)

V5 V4 V3 V2 V1 Vcc Vcc V1 V2 V3 V4 V5

-5V VR R R R R +5V R R R R R VR -5V

VLCD VLCD

V1.5 22 2000/8/03
ST7066

Timing Characteristics

!" Writing data from MPU to ST7066

RS VIH1
VIL1

TAS TAH
R/W
TPW TAH

E
TR TDSW TH

DB0-DB7 Valid
data

TC

!" Reading data from ST7066 to MPU

RS VIH1
VIL1
TAS TAH

R/W
TR TPW TAH

E
TDDR TH

DB0-DB7 Valid
data

TC

V1.5 23 2000/8/03
ST7066

Absolute Maximum Ratings

Characteristics Symbol Value

Power Supply Voltage VCC -0.3V to +5.5V
LCD Driver Voltage VLCD -0.3V to +11.0V
Input Voltage VIN -0.3V to VCC+0.3V
o o
Operating Temperature TA -20 C to + 85 C
o o
Storage Temperature TSTO -55 C to + 125 C

o
DC Characteristics ( TA = 25 C , VCC = 2.7 V – 4.5 V )

Symbol Characteristics Test Condition Min. Typ. Max. Unit

VCC Operating Voltage - 2.7 - 4.5 V
VLCD LCD Voltage VCC-V5 3.0 - 11 V
ICC Power Supply Current fOSC = 280KHz, VCC=3.0V - 0.15 0.3 mA
Rf=90KΩ

VIH1 Input High Voltage - 2.2 - VCC V

(Except OSC1)
VIL1 Input Low Voltage - - 0.3 - 0.6 V
(Except OSC1)
VIH2 Input High Voltage - VCC – 1 - VCC V
(OSC1)
VIL2 Input Low Voltage - - - 1.0 V
(OSC1)
VOH1 Output High Voltage IOH = -0.1mA 2.5 - VCC V
(DB0 - DB7)
VOL1 Output Low Voltage IOL = 0.1mA - - 0.1 V
(DB0 - DB7)
VOH2 Output High Voltage IOH = -0.04mA 0.9VCC - VCC V
(Except DB0 - DB7)
VOL2 Output Low Voltage IOL = 0.04mA - - 0.1VCC V
(Except DB0 - DB7)
RCOM Common Resistance VLCD = 4V, Id = 0.05mA - 2 20 KΩ
RSEG Segment Resistance VLCD = 4V, Id = 0.05mA - 2 30 KΩ
ILEAK Input Leakage VIN = 0V to VCC -1 - 1 µA
Current
IPUP Pull Up MOS Current VCC = 3V 15 20 25 µA

V1.5 24 2000/8/03
ST7066

o
DC Characteristics ( TA = 25 C, VCC = 4.5 V - 5.5 V )

Symbol Characteristics Test Condition Min. Typ. Max. Unit

VCC Operating Voltage - 4.5 - 5.5 V
VLCD LCD Voltage VCC-V5 3.0 - 11 V
ICC Power Supply Current fOSC = 280KHz, VCC=5V - 0.3 0.6 mA
Rf=91KΩ
VIH1 Input High Voltage - 2.2 - VCC V
(Except OSC1)
VIL1 Input Low Voltage - -0.3 - 0.6 V
(Except OSC1)
VIH2 Input High Voltage - VCC-1 - VCC V
(OSC1)
VIL2 Input Low Voltage - - - 1.0 V
(OSC1)
VOH1 Output High Voltage IOH = -0.1mA 4.3 - VCC V
(DB0 - DB7)
VOL1 Output Low Voltage IOL = 0.1mA - - 0.4 V
(DB0 - DB7)
VOH2 Output High Voltage IOH = -0.04mA 0.9VCC - VCC V
(Except DB0 - DB7)
VOL2 Output Low Voltage IOL = 0.04mA - - 0.1VCC V
(Except DB0 - DB7)
RCOM Common Resistance VLCD = 4V, Id = 0.05mA - 2 20 KΩ
RSEG Segment Resistance VLCD = 4V, Id = 0.05mA - 2 30 KΩ
ILEAK Input Leakage VIN = 0V to VCC -1 - 1 µA
Current
IPUP Pull Up MOS Current VCC = 5V 57 62 67 µA

V1.5 25 2000/8/03
ST7066

o
AC Characteristics (TA = 25 C, VCC = 5V)

Symbol Characteristics Test Condition Min. Typ. Max. Unit

Internal Clock Operation
fOSC OSC Frequency R = 91KΩ 190 280 350 KHz
External Clock Operation
fEX External Frequency - 125 280 350 KHz
Duty Cycle - 45 50 55 %
TR,TF Rise/Fall Time - - - 0.2 µs
Write Mode (Writing data from MPU to ST7066)
TC Enable Cycle Time Pin E 1200 - - ns
TPW Enable Pulse Width Pin E 140 - - ns
TR,TF Enable Rise/Fall Time Pin E - - 25 ns
TAS Address Setup Time Pins: RS,RW,E 0 - - ns
TAH Address Hold Time Pins: RS,RW,E 10 - - ns
TDSW Data Setup Time Pins: DB0 - DB7 40 - - ns
TH Data Hold Time Pins: DB0 - DB7 10 - - ns
Read Mode (Reading Data from ST7066 to MPU)
TC Enable Cycle Time Pin E 1200 - - ns
TPW Enable Pulse Width Pin E 140 - - ns
TR,TF Enable Rise/Fall Time Pin E - - 25 ns
TAS Address Setup Time Pins: RS,RW,E 0 - - ns
TAH Address Hold Time Pins: RS,RW,E 10 - - ns
TDDR Data Setup Time Pins: DB0 - DB7 - - 100 ns
TH Data Hold Time Pins: DB0 - DB7 10 - - ns
Interface Mode with LCD Driver(ST7065)
TCWH Clock Pulse with High Pins: CL1, CL2 800 - - ns
TCWL Clock Pulse with Low Pins: CL1, CL2 800 - - ns
TCST Clock Setup Time Pins: CL1, CL2 500 - - ns
TSU Data Setup Time Pin: D 300 - - ns
TDH Data Hold Time Pin: D 300 - - ns
TDM M Delay Time Pin: M -1000 - 1000 ns

V1.5 26 2000/8/03
ST7066

AC Characteristics (TA = 25oC, VCC = 2.7V)

Symbol Characteristics Test Condition Min. Typ. Max. Unit

Internal Clock Operation
fOSC OSC Frequency R = 91KΩ 190 280 350 KHz
External Clock Operation
fEX External Frequency - 125 280 350 KHz
Duty Cycle - 45 50 55 %
TR,TF Rise/Fall Time - - - 0.2 µs
Write Mode (Writing data from MPU to ST7066)
TC Enable Cycle Time Pin E 1200 - - ns
TPW Enable Pulse Width Pin E 160 - - ns
TR,TF Enable Rise/Fall Time Pin E - - 25 ns
TAS Address Setup Time Pins: RS,RW,E 0 - - ns
TAH Address Hold Time Pins: RS,RW,E 10 - - ns
TDSW Data Setup Time Pins: DB0 - DB7 80 - - ns
TH Data Hold Time Pins: DB0 - DB7 10 - - ns
Read Mode (Reading Data from ST7066 to MPU)
TC Enable Cycle Time Pin E 1200 - - ns
TPW Enable Pulse Width Pin E 480 - - ns
TR,TF Enable Rise/Fall Time Pin E - - 25 ns
TAS Address Setup Time Pins: RS,RW,E 0 - - ns
TAH Address Hold Time Pins: RS,RW,E 10 - - ns
TDDR Data Setup Time Pins: DB0 - DB7 - - 320 ns
TH Data Hold Time Pins: DB0 - DB7 10 - - ns
Interface Mode with LCD Driver(ST7065)
TCWH Clock Pulse with High Pins: CL1, CL2 800 - - ns
TCWL Clock Pulse with Low Pins: CL1, CL2 800 - - ns
TCST Clock Setup Time Pins: CL1, CL2 500 - - ns
TSU Data Setup Time Pin: D 300 - - ns
TDH Data Hold Time Pin: D 300 - - ns
TDM M Delay Time Pin: M -1000 - 1000 ns

V1.5 27 2000/8/03
ST7066
The relations between Oscillation Frequency and LCD Frame Frequency
Assume the oscillation frequency is 280KHZ, 1 clock cycle time = 3.6us
1/16 duty; 1/5 bias,1 frame = 3.6us x 200 x 16 = 11520us=11.5ms
200 clocks
1 2 3 4 16 1 2 3 4 16 1 2 3 4 16

Vcc
V1
V2
COM1
V3
V4
V5

Vcc
V1
V2
COM2
V3
V4
V5

Vcc
V1
V2
COM16
V3
V4
V5

Vcc
V1
V2
SEGx off
V3
V4
V5

Vcc
V1
V2
SEGx on
V3
V4
V5
1 frame

V1.5 28 2000/8/03
ST7066
Assume the oscillation frequency is 280KHZ, 1 clock cycle time = 3.6us
1/11 duty; 1/4 bias,1 frame = 3.6us x 400 x 11 = 15840us=15.8ms
400 clocks
1 2 3 4 11 1 2 3 4 11 1 2 3 4 11

Vcc
V1
V2
COM1 V3
V4
V5

Vcc
V1
V2
COM2 V3
V4
V5

Vcc
V1
V2
COM11 V3
V4
V5

Vcc
V1
V2
SEGx off V3
V4
V5

Vcc
V1
V2
SEGx on V3
V4
V5
1 frame

V1.5 29 2000/8/03
ST7066
Assume the oscillation frequency is 280KHZ, 1 clock cycle time = 3.6us
1/8 duty; 1/4 bias,1 frame = 3.6us x 400 x 8 = 11520us=11.5ms
400 clocks
1 2 3 4 8 1 2 3 4 8 1 2 3 4 8

Vcc
V1
V2
COM1 V3
V4
V5

Vcc
V1
V2
COM2 V3
V4
V5

Vcc
V1
V2
COM8 V3
V4
V5

Vcc
V1
V2
SEGx off V3
V4
V5

Vcc
V1
V2
SEGx on V3
V4
V5
1 frame

V1.5 30 2000/8/03
ST7066

I/O PAD Configuration

Input PAD: E (No Pull-up) Input PAD: RS, RW(with Pull-up)

Output PAD: CL1, CL2, M, D

Enable

DATA

I/O PAD: DB0 – DB7

V1.5 31 2000/8/03
ST7066

LCD and ST7066 Connection

1. 5x8 dots, 8 characters x 1 line (1/4 bias, 1/8 duty)

COM1
.
.
.
.
.
COM8
ST7066

LCD Panel: 8 Characters

SEG1 x 1 line
.
.
.
SEG40

2. 5x11 dots, 8 characters x 1 line (1/4 bias, 1/11 duty)

COM1
.
.
.
.
.
.
.
ST7066

.
COM11

LCD Panel: 8 Characters

SEG1 x 1 line
.
.
.
.
.
.
.
SEG40

V1.5 32 2000/8/03
ST7066

3. 5x8 dots, 8 characters x 2 line (1/5 bias, 1/16 duty)

COM1
.
.
.
.
.
COM8
ST7066

COM9
.
.
.
.
.
COM16

SEG1 LCD Panel: 8 Characters

. x 2 line
.
.
.
.
.
.
SEG40

4. 5x8 dots, 16 characters x 1 line (1/5 bias, 1/16 duty)

COM1
.
.
.
.
.
COM8
ST7066

SEG1
.
.
.
.
SEG40
LCD Panel: 16
Characters x 1 line
COM9
.
.
.
.
.
COM16

V1.5 33 2000/8/03
 2000/8/03
Dot Matrix LCD Panel
COM1-16 SEG1-40 S1-S40 S1-S40
D DL1 DR2 DL1 DR2
VDD DL2 VDD DL2
FCS DR1 FCS DR1
SHL1 ST7065 CL1 SHL1 ST7065 CL1
SHL2 CL2 SHL2 CL2
GND M GND M
VEE VEE
ST7066

34
V1 V2 V3 V4 V5 V6 V1 V2 V3 V4 V5 V6
VCC

Note: R= 2.2K ~ 10K, VR= 10K~30K

GND
CL2
CL1
M
V1
V2
V3
ST7066 Application circuit

V4
V5
DB0-DB7
Reg. Reg. Reg. Reg. Reg. Reg.
To MPU Vcc(+5V) -V or GND
ST7066

V1.5
ST7066
PACKAGE DIMENSIONS

V1.5 35 2000/8/03