CURRICULUM VITAE
Pavan Krishna. M E-mail:
pavankrishna.m@gmail.com
Mobile: 09440478030.
Objective:
Aim to be associated with a progressive organization that
gives me scope to my knowledge and skills, as part of team that
dynamically works towards the growth of the Organization.
Strengths:
• Positive attitude in facing new challenges.
• Confident and efficient in undertaking assignments.
• Willing to do hard work and dedication towards given task.
Academic profile:
Year
Qualificati School/College of % Of
Board/University
on Passi Marks
ng
M.Tech SITAMS, Chittoor 67
J.N.T.U.Anantapur (2011)
(VLSISD)
B.Tech S.V.P.C. E.T , Puttur J.N.T. University,
2008 57
(E.C.E) Hyderabad
Intermediat Deepthi Junior
Board of Intermediate
e 2004 82
College, Proddatur Education, Hyderabad
(M.P.C)
Aditya high School, Board of Secondary
S.S.C 2002 83
Proddatur Education, Hyderabad
B.Tech Project profile:
TITLE : DENOISING OF AN SPEECH SIGNAL ON DSP PROCESSOR.
DESCRIPTION : A DSP PROCESSOR is used to remove noise in speech signal
by using wavelets.
COMPONENTS : TMS320C6713DSK Kit, MATLAB 7.2, CCS 3.1.
M.Tech Project profile:
TITLE : MULTIPULE COMMUNICATION DOMAIN DESIGN BY USING
FPGA SYSTEM ON CHIP.
DESCRIPTION : The integration of the NoC architecture with classical bus-
based systems.
LANGUAGE : VHDL
COMPONENTS : Xilinx ISE 9.2, Modelsim 6.2.
Software and Hardware Skills:
Design Skills: Digital design process including Design Architecture, RTL coding,
Synthesis, Simulation, Timing Analysis.
Simulators : Modelsim xe 11.
Synthesis : Xilinx ISE 10.i.
Schematic and Layout : Tanner Tools v12.5.
Languages:
Hardware Description Language : VHDL, Verilog.
Programming Languages : C.
Scripting languages : Perl (basics)
Operating Systems : Windows, MS DOS.
Seminar and Presentations:
Participated in A.P state level on “SPOT ART” contest conducted by friends
company Vijayawada in 1998 & 2000.
• Presented working model on “SPEED CONTROL OF DC MOTOR uses
MICRO CONTROLLER” in SRUJANA-2008.
Attended workshops:
• SOC AND IS Signal Integrity Issues.
• MENTOR GRAPHICS BASED VLSI DESIGN FLOW.
• “VLSI Design” sponsored by the Special Manpower development program
in the area of VLSI Design and related Software (SMDP-II) of Ministry of
Communication & Information Technology and Organized by the
department of E.C.E of NIT Calicut during 16th July -17th July, 2010.
Personal Details:
DOB : 15/Aug/1987.
Father’s Name : M.Subbaramaiah
Permanent Address : #5/109,
Vijayanagaram Street,
Proddatur – 516360,
Kadapa (Dist), A.P.
Gender : Male
Nationality : Indian
Languages Known : English & Telugu
In view of the above, I request you to be kind enough to give
opportunity to serve your esteemed organization in the capacity
mentioned above for which act of kindness, I shall be very thankful and
grateful to you.
Declaration:
I here by declare that above details furnished above are true to the
best of my knowledge and belief.
(M.PAVAN KRISHNA)
