SHILPHA.
G
Kambar Street, Alandur, Chennai - 600016 | Mobile no: +91 9944877292
Email Id: shilphaganesan@gmail.com
2 years and 6 months Experience as VLSI Project Engineer
OBJECTIVE
Seeking a position with an organization where I can contribute my skills as a Design Engineer in
VLSI for organization’s success and synchronize with new technology while being resourceful, innovative and
flexible.
SUMMARY
2+ years of experience in RTL design using Verilog HDL
Experience in writing Verilog and VHDL RTL coding
Experience in simulation and synthesis using Xilinx ISE Tool
Highly organized self-starter, with a sound professional attitude and strong work ethics.
Passionate electronics professional and good at out-of- the-box thinking.
Excellent interpersonal skills in communications and client relations.
ACADEMIC QUALIFICATIONS
RVS College of Engineering and Technology ( affiliated to Anna University, Chennai)
B.E., Electronics and Communication Engineering with CGPA: 7.2 (2015)
St.Mary’s Girl’s Higher Secondary School
Higher Secondary with 84% ( 2011)
Rajan Matriculation School
SSLC with 87 % (2009)
TECHNICAL SKILLS
Programming Languages Verilog HDL
VHDL
ModelSim
Xilinx ISE
Software Platforms Quartus II
Tanner EDA tool
Hardware Expertise FPGA Spartan 3
Spartan 3E
Altera DE2 Board
Communication Protocols UART
SPI
I2C
Area of Interest Digital Electronics
VLSI Design
PROFESSIONAL EXPERIENCE
VEE EEE Technology Solutions Pvt Ltd
Designation - VLSI Project Engineer
Duration - August 2015 to Till Date
PROJECTS
Project-1:
Product Title Dynamic Reconfigurable DA based FIR filter
Tool Modelsim, Xilinx ISE
Role RTL DESIGN using Verilog HDL
Hardware ALTERA FPGA
Finite Impulse Response (FIR) filter is one of the key functions of digital signal processing operations.
Multiplication and Accumulation (MAC) unit is the major factor in digital FIR filter. In addition to configuration
of coefficient values also give additional features in FIR filter. In this project we improve both kinds efficiently
with the help of Reconfigurable Distributed Arithmetic (Multiplier-less) architecture. Performances are
measured in terms of Hardware Slices, LUTs, Memory Utilization, Register Utilization, Combinational and
Sequential Delay consumption and Power consumption. Circuit has been implemented by using ALTERA FPGA.
Project-2:
Product Title Design and Implementation of UART using Verilog HDL
Tool Modelsim, Xilinx ISE
Role RTL DESIGN using Verilog HDL
Universal Asynchronous Receiver Transmitter (UART) is a serial communication interface. The UART design
has programmable features for Transmission, Reception and Baud Rate generation. The design is implemented
using Hardware Description Language Verilog. The design is simulated and verified on Xilinx ISE
Project-3:
Project Mixed Radix-2, Radix-4 & Radix-8 Single path Delay Commutator FFT for OFDM System
Tool Modelsim, Xilinx ISE
Role RTL DESIGN using Verilog HDL
Orthogonal Frequency Division Multiplexing (OFDM) architecture is modulation technique in which single
higher rate data streams is divided into many lower rate data streams. Fast Fourier Transformation (FFT) is the
best frequency transformation technique for converting timing sequence into frequency sequence. In this
project Mixed Radix and Novel architecture of “Single path Delay Commutator (SDC)” is used for designing
OFDM processor.
CO CURRICULAR ACTIVITIES
Participated in National level technical symposium in project presentation and won third prize at Sri
Ramakrishna Engineering College, Coimbatore.
Participated in PCB Design Workshop conducted by S FORGE LLP at RVS College of Engineering and
Technology.
Presented a paper on “Greenhouse effect monitoring” in THALES’14, a national level technical
symposium conducted by KalaignarKarunanidhi Institute of Technology.
Participated in the National Workshop on "Simulation on NS2" at RVS College of Engineering and
Technology.
Completed Value Added Course on "VLSI Architecture Design using Front End Tools".
EXTRA CURRICULAR ACTIVITIES
100% attendance record in the second year and third year at RVS College of Engineering and
Technology.
Acted as the class representative at RVS College of Engineering and Technology..
Has secured 2nd topper in 7th semester during UG course.
Secured 2nd rank in SSLC exam at school level.
Participated in group dance, group song and solo song in second state level inter collegiate student’s
meet”DREAMS’14”.
PUBLICATION
Published a paper in journal title as “LOW POWER 128 POINT SPLIT RADIX FFT FOR LTE
APPLICATION” during 2014 in IJMSR.
ACADEMIC PROJECT
1. UG Final Year Project
Project Incorporation of reduced full adder and half adder into carry select adder for digital FIR filter
Tool Modelsim,Xilinx ISE
Hardware Spartan 3 FPGA
Duration 6 months
Team Size 1
MAC unit of FIR filter has been designed using efficient Multiplier and adder circuits for optimized area,
power and delay. The design of direct form FIR filter with efficient MAC unit has been presented. Initially,
full adder and half adder structures are shrunk down by reducing number of gates. This compact Full adder
and half adder structures are incorporated into carry select adder. This Implementation was done by using
SPARTAN 3 FPGA kit and synthesized by using Xilinx ISE 10.1 design tool.
PERSONAL PROFILE
Father’s Name : Mr.K.Ganesan
Date of Birth : 24.01.1994
Gender : Female
Marital Status : Single
Nationality : Indian
Languages known : English, Tamil
Hobbies : Drawing , Singing
DECLARATION
I (Shilpha G) hereby declare that all the information furnished above is true to my knowledge.
Date : Signature
Place : Chennai G.Shilpha
