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Sakshi Nema is a Physical Design Engineer with a Master's degree in Microelectronics Engineering and 6 years of experience in microprocessor design, specializing in deep submicron technology. She has worked at Cadence Design Systems as a Technical Education Consultant and previously at Intel as a Graphics Hardware Design Engineer, contributing to projects like Skylake and KabyLake. Her expertise includes synthesis and APR flows, power optimization, reliability verification, and automation, along with strong interpersonal skills demonstrated through various leadership roles.

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23 views1 page

SakshiNema (6 0)

Sakshi Nema is a Physical Design Engineer with a Master's degree in Microelectronics Engineering and 6 years of experience in microprocessor design, specializing in deep submicron technology. She has worked at Cadence Design Systems as a Technical Education Consultant and previously at Intel as a Graphics Hardware Design Engineer, contributing to projects like Skylake and KabyLake. Her expertise includes synthesis and APR flows, power optimization, reliability verification, and automation, along with strong interpersonal skills demonstrated through various leadership roles.

Uploaded by

himani
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We take content rights seriously. If you suspect this is your content, claim it here.
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SAKSHI NEMA

Bangalore | +91 9739411677 | sguptanema@gmail.com | LinkedIn


____________________________________________________________________________________________________________________________________________________________________

PHYSICAL DESIGN ENGINEER


Master of Microelectronics Engineering graduate from BITS Pilani with 6 years of experience in Microprocessor design in
deep submicron technology. Involved with tool development and documentation in the digital signoff domain; solved critical
routing, timing challenges using optimized SD techniques; enabled flow automation through programming scripts;
converged strategic designs with efficient timing closure and optimized power consumption.
Areas of expertise:
 Synthesis & APR Flows – Block ownership with placement, routing and timing closures
 IR Drop Analysis – Power optimization and efficiency enhancement
 Reliability Verification – Design robustness and reliability metrics compliance
 Automation – Design convergence through automation scripts
 Customer Training & Course Development – Digital Design Signoff tools documentation, customer interactions
____________________________________________________________________________________________________________________________________________________________________
PROFESSIONAL EXPERIENCE

Cadence Design Systems, Bangalore


Technical Education Consultant July.16 – Present

Key Roles and Responsibilities


 Developing and delivering technical courses for Cadence Customers worldwide
 Conducting customer webinars on advanced technology and tool concepts
 Enhancing the customer experience with online video demonstrations
 Providing support to the customers for their tool related queries (i.e Voltus and Tempus)

Intel Technology Private Limited, Bangalore


Graphics Hardware Design Engineer Jan.12 – Jun.16
Project Description
Skylake, a high-speed Windows 10 compatible microarchitecture built at 14nm process with 2.5 times faster processing
speed caters to the ultra-low power devices (Tablets/ Ultrabooks), high performance mobiles as well as traditional desktop
CPUs. KabyLake, the 14 nm successor to the Skylake, features improved performance in 3D graphics & 4K video playback.
Key Achievements
 Successfully converged timing, routing and power of multiple blocks with ~1.5M gate-count in Skylake project
 Led design closure on RTL issues with early identification and resolution to achieve seamless synthesis execution
Key Roles and Responsibilities
 Collaborated with internal teams for enabling 4K improved performance in HD Graphics in Skylake
 Converged multi power design on Reliability Verification (EM, SH, IR drop)
 Executed ECO flows to minimize database perturbation in LV domain and achieved faster ECO to tape-in cycle

TECHNICAL SKILLSETS
 Tools – PT, ICC/DC, Innovus, Tempus, Voltus, RedHawk, Tavor, ModelSim, Silvaco
 Flow - APR (Automatic Place and Route), Timing Signoff, Power & Rail Analysis
 HDL/Scripting Languages – Verilog/Perl, TCL, SHELL
 Operating System - UNIX
__________________________________________________________________________________________________________________________________________ ________________________________________________________

INTERPERSONAL SKILLSETS
 Involved with co-curricular activities at Cadence Cultural Fest
 Led “Great Place to Work” program across multiple teams at Intel
 Led Student Council facilitating planning and discipline initiatives at SGSITS annual festivals
__________________________________________________________________________________________________________________________________________________________________________________________________

EDUCATION
Master of Microelectronics Engineering, BITS Pilani (Pilani Campus, Rajasthan) Jun.12
Bachelor of Electronics & Communication Engineering, SGSITS (Indore, Madhya Pradesh) Jun.10

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