SHIVANSHU GARG
Address: c\o Moh. Kayasthan Hasanpur, AMROHA,
UTTARPRADESH(244241)
Mobile number: (+91)9587400498
Email id: shivanshugarg17.sg@gmail.com
CAREER OBJECTIVE
An enthusiastic and self-motivated Physical design engineer looking for a challenging and
responsible position as Physical design Engineer to apply my knowledge and skill with my hard
work and patience and be world class in ASIC design.
CORE COMPETENCY
• Knowledge about LINUX (working with files and directories using various basic
commands like: cp, cat, more, less, head, tail, pwd, mkdir, mv, rm, ps, kill, jobs, find,
grep, awk ).
• Knowledge on PERL scripting & written scripts in Perl with the use of scalar, array ,
hashes, loops, & commands like: shift, unshift, push, pop, sed.
• Have a good knowledge in Verilog coding. Write various modules and test benches for
Half and Full adders and subtractors, MUX and De-MUXs, Encoders and Decoders, and
Flip Flops.
• Good knowledge about Static Timing Analysis and strongly acquainted with the terms
setup and hold times and violations, timing exceptions, cell delay, net delay, timing paths,
slack , skew , OCV, Signal Integrity, WC,BC, CRPR, etc.
• Well learned about the Physical Design and its flow from APR to TAPE OUT. Perceptive
knowledge on Inputs required for each step and process followed in each step. Well
known about floor plan, power plan, placement, CTS, routing, physical verification .
• Good Acquaintance with Cadence Tools: Simvision, Encounter, Innovus, Tempus. Fair
knowledge in usage of the tool in various steps.
• Familiar with other simulation tool: Questa Sim and Text Editors: VI , NANO .
PROFILE
• ASIC design engineer trainee at Incise Infotech. Private Limited.
TOOLS USED
S.NO TOOL WORK
1. Cadence (Simvision tool), Questa Sim RTL coding and test bench verification
2. Cadence (SOC Encounter version 11.13,14.28) RTL to GDSII
3. Cadence (SOC Innovus version 16.2) RTL to GDSII
4. Cadence(Tempus 16.2) STA(Static Time Analysis)
5. Cadence(Tempus 16.2) SI and Cross talk
PROJECTS
Projects 1:- Block level design of 4 bit counter and P&R implementation on 90nm
technology.
Objective:- Netlist to GDS implementation of 4 - bit counter.
Tool used :- Cadence (SOC Encounter, version 11.13 )
Responsibility:- Floor Planning , Power grid generation, Placement, CTS, Routing, timing
analysis and Physical verification.
Design description
Design mode: 90 nm.
No of standard cells: 13
Instances : 13
Analysis mode : non OCV
No. of Clocks: 1
Frequency: 166MHz
Temperature: 25 Deg. Celsius
Metal layers: 9
Problems faced:- Report analysis, floor Planning, methods to fix timing violations, fixing
geometry and metal density violations.
Project 2:- Block level design of USB and P&R implementation on 90nm technology.
Objective:- Netlist to GDS implementation of USB.
Tool used :- Cadence (SOC Encounter, version 11.13 )
Responsibility:- Floor Planning, Power Planning , Placement , CTS , Routing , Timing Check
and report analysis of design .
Design description
Design mode: 90 nm.
No of standard cells: 18508
Instances: 18508
Analysis mode : non OCV
No. of Clocks: 3
Frequency: 142.8 MHz
Temperature: 25 Deg. Celsius
Metal layers: 9
Problems faced: - Finding the width and spacing of stripes, Fixing timing violations ,Fixing
geometry and connectivity violations.
Project 3:-Block level design of Dual Tone Multi Frequency (DTMF) and P&R
implementation on 90nm technology.
Objective:- Netlist to GDS implementation of DTMF.
Tool used :- Cadence (Innovus, version 11.13 ) ,Tempus (STA) , Tempus (SI & Cross talk)
Responsibility:-Floor Planning, Power Planning, Placement, CTS, Routing, Timing checks, SI
and Cross talk.
Design description
Design mode: 90 nm.
No of standard cells: 3238
Macro: 5
Instances: 3243
Analysis mode : non OCV
No. of Clocks: 6
Temperature: 25 Deg. Celsius
Metal layers: 9
Problem faced:- Macro placement, Providing blockages, Finding the width and spacing of
stripes, Fixing timing violations, Fixing geometry and other violations, Fixing in Crosstalk
violation.
Projects 4:- Low Power Design using DMA
Objective: - Floor planning and Power planning of Low Power Design.
Tool used: - Cadence (Innovus, version 16.2).
Responsibility:- Reading CPF, creating power domains, creating minimum gaps around power
domains, creating power grid around each power domain and macros.
Design description
Design mode: 90nm.
No of standard cells: 24083
Macro: 7
Instances: 24090
Analysis mode : non OCV
No. of Clocks: 5
Temperature: 25 Deg. Celsius
Metal layers: 15
Problem faced: - Difficult to create via.
Project 5:- Block level design of Leon Processor and P&R implementation on
90nm technology.
Objective:- Netlist to GDS implementation of Leon Processor.
Tool used :- Cadence (Innovus, version 16.2)
Responsibility:- Floor Planning , Power grid generation, Placement, CTS, Routing, timing
analysis and Physical verification.
Design description
Design mode: 45 nm.
No of standard cells: 36384
Instances : 36388
No of blocks: 4
Analysis mode : non OCV
No. of Clocks: 6
Temperature: 25 Deg. Celsius
Metal layers: 9
Problems faced:- Report analysis, floor Planning, methods to fix timing violations, fixing
geometry and metal density violations.
Project 6:- Block level design of Asic-entity and P&R implementation on 90nm
technology.
Objective:- Netlist to GDS implementation of asic-entity.
Tool used :- Cadence (Innovus, version 16.2)
Responsibility:- Floor Planning , Power grid generation, Placement, CTS, Routing, timing
analysis and Physical verification.
Design description
Design mode: 90 nm.
No of standard cells: 17886
No of blocks: 29
No of instances: 18228
Analysis mode : non OCV
No. of Clocks: 8
Temperature: 25 Deg. Celsius
Metal layers: 9
Problems faced:- Report analysis, floor Planning, methods to fix timing violations, fixing
geometry and metal density violations.
STATIC TIMING ANALYSIS
STA (Analysing its basic topology related to its inputs ,output, ideal clock , generated clock ,
Duty cycle ,clock latency , clock uncertainty , Examples on Timing Analysis , setup & hold
calculation, WC,BC and CRPR.
RESPOSIBILITIES:
Understand the setup and hold time, Worst and Best cases, CRPR, calculation of arrival and
required times, slack , type of skews, timing exceptions .
CHALLENGES:
• Negative slack and methods to remove it.
• Analyzing the report of cell delay which depends on input transition &output capacitance.
EXPERIENCE
Incise Infotech Pvt ltd (Training)
o (March 2016 – June 2017)
Incise Infotech Pvt Ltd (Internship)
o (June 2017 – On Going)
o Completion date – 1st May 2018
EDUCATION
Degree Year Name of the Institute University/Board Result
B.Tech 2018 B K Birla Institute of Engineering RTU 74%
and Technology, Pilani
Intermediate 2013 Smt. Sukh Devi Inter College UP Board 76%
Matric 2011 Smt. Sukh Devi Inter College UP Board 70%
PERSONAL STRENGTHS
• Can easily adjust with the environment.
• Punctual and dedicated towards on my work.
• Love to learn new things related with new technologies.
PERSONAL PROFILE
Name : Shivanshu Garg
Date of Birth : 17th October 1995
Father Name : Mr. Pradeep Garg
Nationality : Indian
Sex : Male
Languages known : English & Hindi
Place : Hasanpur (Amroha)
