A.V.Lavanya Email-id:lavanya.arcot25@gmail.
com
Phone no: 9618979425
Summary:
About 3.4 years of working experience in VLSI physical design.
Worked as Physical Design Engineer in Wipro Technologies at Hyderabad from
September 2015 to April 2016.
Worked as Physical Design Engineer in Smartplay Technologies at Bangalore
from March 2015 to September 2015.
Worked as Physical design Engineer in First Pass semiconductors at Hyderabad
from January 2013 to Feb 2015.
Tools:
Experience in physical design of 90nm, 65nm, 40nm, 16nm and 14nm technologies using
Cadence and Synopsys tool.
Cadence SOC Encounter and IC complier – Floor Planning, Place & Route, and
clock tree synthesis
Encounter Timing System, Prime Time – Static Timing Analysis and Crosstalk
Analysis
STARRC -Extraction
IC Validator – Physical Verification (LVS and DRC)
MVRC – UPF check
RV- IR Drop Analysis
LEC, FASTRAIL
Academic Profile:
M.Tech in VLSI System Design (2010-2012) from JNTU University with 78.67 %.
B.Tech in Electronics and Communication Engineering (2005-2009) from JNTU
University, Hyderabad with 67.12 % aggregate.
Intermediate and SSC from A.P state board with 85.6% & 84.5% respectively.
1
VLSI & Software Exposure:
Operating Systems: Windows, Linux, UNIX.
HDL Languages: Verilog.
Scripting Languages: TCL.
Projects:
Project 1: Block P&R implementation
Team Size: 12
Role: Team member
Responsibility: Floorplan, power plan, placement, clock tree synthesis, routing, fixing
DRC & LVS, extraction and timing closure, MVRC, IR drop analysis.
Design Details:
Technology – TSMC 14nm, 10 Metal Layers
Tools: ICC, PTSI, StarRC,MVRC,RV
Block 1 Design Statistics: 22 macros, 5 primary clocks and 3 generated clocks, max
frequency of 450 MHz, 215k instances
Challenges:
The design has 2 power domains. Building clock tree for voltage crossing domains was
challenging.
Project 2: Block P&R implementation
Team Size: 12
Role: Team member
Responsibility: Floorplan, power plan, placement, clock tree synthesis, routing, fixing
DRC & LVS, extraction and timing closure.
Design Details:
Technology – TSMC 16nm, 12 Metal Layers
Tools: Innovus, ICC, PTSI, StarRC.
Block 1 Design Statistics: 74 macros, 15 primary clocks and 3 generated clocks, max
frequency of 800MHz, 760K instances
Block 2 Design Statistics: 52 macros, 13 primary clocks, 2 generated clocks, max
frequency of 800MHz, 460K instances.
Challenges:
The design was congested due to high macro count. Multiple floorplan iterations performed
to resolve congestion issues.
Project 3: Block P&R implementation
Team Size: 5
2
Role: Team member
Responsibility: Floor planning, placement, clock tree synthesis, routing, timing ECOs,
extraction and timing closure with ETS including crosstalk and OCV effects.
Design Details:
Technology –GF 40nm, 8 Metal Layers
Tools: SOC Encounter, QRC, ETS
Design Statistics: 12 macros, 4 primary clocks and 3 generated clocks, max frequency of
333MHz, 1.2 Million gate count.
Challenges:
The major challenge in this block is to create clock tree with less insertion delay and to
meet hold timing.
Project 4: Block P&R implementation
Team Size: 4
Role: Team member
Responsibility: Floor Planning, Placement, Building the clock tree, Routing, timing closure
with ETS including crosstalk and OCV effects.
Design Details:
Technology – TSMC 65nm, 8 Metal Layers
Tools: SOC Encounter, QRC, ETS
Design Statistics: 20 macros, 3 primary clocks, max frequency of 250MHz, 1.75 Million
gate count.
Challenges:
The major challenge in this block is to meet hold timing issues.
Project 5: Block P&R implementation
Team Size: 4
Role: Team member
Responsibility: Floor Planning, Placement, Building the clock tree, Routing, timing closure
with ETS including crosstalk and OCV effects.
Design Details:
Technology – CSM 90nm, 8 Metal Layers
Tools: SOC Encounter, ETS, QRC, ETS,Assura
Design Statistics: 4 macros, 3 primary clocks, max frequency of 200MHz, 1.12 Million
gate count.
Challenges:
The major challenge in this block is to meet timing including crosstalk and OCV. Most of
the nets are affected by crosstalk.
3
BTECH Project:
Project Name: Implementing process control & monitoring system using CAN protocol.
Details: The main aim of the project is to acquire data from temperature sensor and LDC using
CAN protocol which provides efficient data transmission with high data rates. It has advantage of
giving error free and loss less data to receiver when compared to other protocols. By taking
feedback we can control and monitor the system. It is highly applicable in vehicles, industries,
remote areas etc.
MTECH Project:
Project Name: Self-Sleep Buffer for Distributed MTCMOS Design.
Details: Self-sleep buffer for distributed MTCMOS design with gated clock is proposed. The
self-sleep buffer eliminates the need for a sleep distribution network. This work targets the
challenges and complexities related to sleep signal distribution in a distributed MTCMOS design.
Personal Profile:
Father’s Name : A.E.Varadaraj
Date of Birth : 25-01-1988
Gender : Female
Languages : English, Telugu
Nationality : Indian
I hereby declare that the information given above is true with proven records.
PLACE: HYDERABAD A.V.LAVANYA
