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Lab 4 Logica

This document contains code for two digital logic circuits (Circuit A and Circuit B) and their test benches written in VHDL. Circuit A and B both take a 4-bit input and output a single bit. The code defines the port connections, architecture, and stimulus processes to test the circuits by inputting different values and checking the output.

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Camila Camperos
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37 views16 pages

Lab 4 Logica

This document contains code for two digital logic circuits (Circuit A and Circuit B) and their test benches written in VHDL. Circuit A and B both take a 4-bit input and output a single bit. The code defines the port connections, architecture, and stimulus processes to test the circuits by inputting different values and checking the output.

Uploaded by

Camila Camperos
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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LÓGICA Y DISEÑO DIGITAL

INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS


CODIGO: 1091567

LABORATORIO N°4
EJEMPLO A:

-------------------------------------------------------
-- Company: --use UNISIM.VComponents.all;
-- Engineer:
-- entity CICUITO_A is
-- Create Date: 15:48:46 04/08/2020 Port ( A : in STD_LOGIC_VECTOR (3
-- Design Name: downto 0);
-- Module Name: CICUITO_A - Behavioral X : out STD_LOGIC);
-- Project Name: end CICUITO_A;
-- Target Devices:
-- Tool versions: architecture Behavioral of CICUITO_A is
-- Description:
-- begin
-- Dependencies:
-- X<= '0' WHEN A="0000" ELSE
-- Revision: '0' WHEN A="0001" ELSE
-- Revision 0.01 - File Created '1' WHEN A="0010" ELSE
-- Additional Comments: '1' WHEN A="0011" ELSE
-- '0' WHEN A="0100" ELSE
------------------------------------------------------- '0' WHEN A="0101" ELSE
library IEEE; '0' WHEN A="0110" ELSE
use IEEE.STD_LOGIC_1164.ALL; '0' WHEN A="0111" ELSE
'1' WHEN A="1000" ELSE
-- Uncomment the following library '1' WHEN A="1001" ELSE
declaration if using '1' WHEN A="1010" ELSE
-- arithmetic functions with Signed or '1' WHEN A="1011" ELSE
Unsigned values '0' WHEN A="1100" ELSE
--use IEEE.NUMERIC_STD.ALL; '0' WHEN A="1101" ELSE
'1' WHEN A="1110" ELSE
-- Uncomment the following library '0' WHEN A="1111" ;
declaration if instantiating
-- any Xilinx primitives in this code. end Behavioral;
--library UNISIM;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:58:16 04/08/2020
-- Design Name:
-- Module Name:
C:/Users/Yorgelis/Documents/ISE_DIGITALIZAR/LAB_4/LABORATORIO_4/CIRCUITO_A/SI
MULACION_CIRCUITO_A.vhd
-- Project Name: LABORATORIO_4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CICUITO_A
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY SIMULACION_CIRCUITO_A IS
END SIMULACION_CIRCUITO_A;
ARCHITECTURE behavior OF SIMULACION_CIRCUITO_A IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CICUITO_A
PORT(
A : IN std_logic_vector(3 downto 0);
X : OUT std_logic
);
END COMPONENT;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

-- constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CICUITO_A PORT MAP (
A => A,
X => X
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A<="0010";
wait for 50 ns;
A<="1010";
wait for 50 ns;
A<="1111";
wait for 50 ns;
A<="0000";
wait for 50 ns;
A<="0111";
wait for 50 ns;
A<="0101";
wait for 50 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;

END;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

EJERCICIO B:

------------------------------------------------------- --library UNISIM;


-- Company: --use UNISIM.VComponents.all;
-- Engineer:
-- entity CIRCUITO_B is
-- Create Date: 17:40:27 04/08/2020 Port ( A : in STD_LOGIC_VECTOR (3
-- Design Name: downto 0);
-- Module Name: CIRCUITO_B - X : out STD_LOGIC);
Behavioral end CIRCUITO_B;
-- Project Name:
-- Target Devices: architecture Behavioral of CIRCUITO_B is
-- Tool versions:
-- Description: begin
--
-- Dependencies: X<= '0' WHEN A="0000" ELSE
-- '0' WHEN A="0001" ELSE
-- Revision: '0' WHEN A="0010" ELSE
-- Revision 0.01 - File Created '0' WHEN A="0011" ELSE
-- Additional Comments: '0' WHEN A="0100" ELSE
-- '0' WHEN A="0101" ELSE
------------------------------------------------------- '0' WHEN A="0110" ELSE
library IEEE; '0' WHEN A="0111" ELSE
use IEEE.STD_LOGIC_1164.ALL; '1' WHEN A="1000" ELSE
'1' WHEN A="1001" ELSE
-- Uncomment the following library '1' WHEN A="1010" ELSE
declaration if using '1' WHEN A="1011" ELSE
-- arithmetic functions with Signed or '0' WHEN A="1100" ELSE
Unsigned values '0' WHEN A="1101" ELSE
--use IEEE.NUMERIC_STD.ALL; '1' WHEN A="1110" ELSE
'0' WHEN A="1111" ;
-- Uncomment the following library
declaration if instantiating end Behavioral;
-- any Xilinx primitives in this code.
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:50:52 04/08/2020
-- Design Name:
-- Module Name:
C:/Users/Yorgelis/Documents/ISE_DIGITALIZAR/LAB_4/LABORATORIO_4/CIRCUITO_B/SI
MULACION_CIRCUITO_B.vhd
-- Project Name: LABORATORIO_4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CIRCUITO_B
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY SIMULACION_CIRCUITO_B IS
END SIMULACION_CIRCUITO_B;
ARCHITECTURE behavior OF SIMULACION_CIRCUITO_B IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT CIRCUITO_B
PORT(
A : IN std_logic_vector(3 downto 0);
X : OUT std_logic
);
END COMPONENT;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

-- constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CIRCUITO_B PORT MAP (
A => A,
X => X
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A<="0010";
wait for 50 ns;
A<="1010";
wait for 50 ns;
A<="1111";
wait for 50 ns;
A<="0000";
wait for 50 ns;
A<="0111";
wait for 50 ns;
A<="0101";
wait for 50 ns;

-- wait for <clock>_period*10;


-- insert stimulus here
wait;
end process;

END;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

EJERCICIO C:

------------------------------------------------------- --library UNISIM;


-- Company: --use UNISIM.VComponents.all;
-- Engineer:
-- entity CIRCUITO_C is
-- Create Date: 17:58:34 04/08/2020 Port ( A : in STD_LOGIC_VECTOR (3
-- Design Name: downto 0);
-- Module Name: CIRCUITO_C - X : out STD_LOGIC);
Behavioral end CIRCUITO_C;
-- Project Name:
-- Target Devices: architecture Behavioral of CIRCUITO_C is
-- Tool versions:
-- Description: begin
--
-- Dependencies: X<= '0' WHEN A="0000" ELSE
-- '0' WHEN A="0001" ELSE
-- Revision: '1' WHEN A="0010" ELSE
-- Revision 0.01 - File Created '0' WHEN A="0011" ELSE
-- Additional Comments: '0' WHEN A="0100" ELSE
-- '0' WHEN A="0101" ELSE
------------------------------------------------------- '0' WHEN A="0110" ELSE
library IEEE; '0' WHEN A="0111" ELSE
use IEEE.STD_LOGIC_1164.ALL; '1' WHEN A="1000" ELSE
'1' WHEN A="1001" ELSE
-- Uncomment the following library '1' WHEN A="1010" ELSE
declaration if using '1' WHEN A="1011" ELSE
-- arithmetic functions with Signed or '0' WHEN A="1100" ELSE
Unsigned values '0' WHEN A="1101" ELSE
--use IEEE.NUMERIC_STD.ALL; '0' WHEN A="1110" ELSE
'0' WHEN A="1111" ;
-- Uncomment the following library
declaration if instantiating end Behavioral;
-- any Xilinx primitives in this code.
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:14:49 04/08/2020
-- Design Name:
-- Module Name:
C:/Users/Yorgelis/Documents/ISE_DIGITALIZAR/LAB_4/LABORATORIO_4/CIRCUITO_C/SI
MULACION_CIRCUITO_C.vhd
-- Project Name: LABORATORIO_4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CIRCUITO_C
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY SIMULACION_CIRCUITO_C IS
END SIMULACION_CIRCUITO_C;

ARCHITECTURE behavior OF SIMULACION_CIRCUITO_C IS

-- Component Declaration for the Unit Under Test (UUT)


COMPONENT CIRCUITO_C
PORT(
A : IN std_logic_vector(3 downto 0);
X : OUT std_logic
);
END COMPONENT;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

-- constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CIRCUITO_C PORT MAP (
A => A,
X => X
);

-- Clock process definitions


-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A<="0010";
wait for 50 ns;
A<="1010";
wait for 50 ns;
A<="1111";
wait for 50 ns;
A<="0000";
wait for 50 ns;
A<="1000";
wait for 50 ns;
A<="1011";
wait for 50 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;

END;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

EJERCICIO D:

------------------------------------------------------- Port ( A : in STD_LOGIC_VECTOR (3


-- Company: downto 0);
-- Engineer: X : out STD_LOGIC);
-- end CIRCUITO_D;
-- Create Date: 18:41:14 04/08/2020
-- Design Name: architecture Behavioral of CIRCUITO_D is
-- Module Name: CIRCUITO_D -
Behavioral begin
-- Project Name:
-- Target Devices: X<= '0' WHEN A="0000" ELSE
-- Tool versions: '0' WHEN A="0001" ELSE
-- Description: '0' WHEN A="0010" ELSE
-- '0' WHEN A="0011" ELSE
-- Dependencies: '0' WHEN A="0100" ELSE
-- '0' WHEN A="0101" ELSE
-- Revision: '0' WHEN A="0110" ELSE
-- Revision 0.01 - File Created '0' WHEN A="0111" ELSE
-- Additional Comments: '1' WHEN A="1000" ELSE
-- '1' WHEN A="1001" ELSE
------------------------------------------------------- '1' WHEN A="1010" ELSE
library IEEE; '1' WHEN A="1011" ELSE
use IEEE.STD_LOGIC_1164.ALL; '0' WHEN A="1100" ELSE
'0' WHEN A="1101" ELSE
-- Uncomment the following library '1' WHEN A="1110" ELSE
declaration if using '0' WHEN A="1111" ;
-- arithmetic functions with Signed or
Unsigned values end Behavioral;
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library


declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CIRCUITO_D is
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:45:45 04/08/2020
-- Design Name:
-- Module Name:
C:/Users/Yorgelis/Documents/ISE_DIGITALIZAR/LAB_4/LABORATORIO_4/CIRCUITO_D/SI
MULACION_CIRCUITO_D.vhd
-- Project Name: LABORATORIO_4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CIRCUITO_D
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY SIMULACION_CIRCUITO_D IS
END SIMULACION_CIRCUITO_D;
ARCHITECTURE behavior OF SIMULACION_CIRCUITO_D IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT CIRCUITO_D
PORT(
A : IN std_logic_vector(3 downto 0);
X : OUT std_logic
);
END COMPONENT;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

-- constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CIRCUITO_D PORT MAP (
A => A,
X => X
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A<="0010";
wait for 50 ns;
A<="1010";
wait for 50 ns;
A<="1111";
wait for 50 ns;
A<="0000";
wait for 50 ns;
A<="1000";
wait for 50 ns;
A<="1011";
wait for 50 ns;
-- wait for <clock>_period*10;

-- insert stimulus here

wait;
end process;
END;
LÓGICA Y DISEÑO DIGITAL
INTEGRANTE: TIANNY YORGELYS CARRASCAL BARRIENTOS
CODIGO: 1091567

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