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Countersprints

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yashashvinivaluva2511
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25 views25 pages

Countersprints

Uploaded by

yashashvinivaluva2511
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Code sync_up

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity sync_up is

Port ( i : in STD_LOGIC;

clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (3 downto 0);

qbar : out STD_LOGIC_VECTOR (3 downto 0));

end sync_up;

architecture Behavioral of sync_up is

signal count:STD_LOGIC_VECTOR (3 downto 0);


begin

process(i,clk,rst)

begin

if (rst='1') then q<="0000" ;qbar<= not q;

elsif (clk'event and clk='1') then

if (i='0') then count<= "0000" ;

else count<=count + 1;

q<=count;

qbar<=not q;

end if;

end if;

end process;

end Behavioral;

test bench code (synch up)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;
ENTITY sync_uptest IS

END sync_uptest;

ARCHITECTURE behavior OF sync_uptest IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT sync_up

PORT(

i : IN std_logic;

clk : IN std_logic;

rst : IN std_logic;

q : INOUT std_logic_vector(3 downto 0);

qbar : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal i : std_logic := '0';

signal clk : std_logic := '0';

signal rst : std_logic := '0';

--BiDirs

signal q : std_logic_vector(3 downto 0);


--Outputs

signal qbar : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: sync_up PORT MAP (

i => i,

clk => clk,

rst => rst,

q => q,

qbar => qbar

);

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;


end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

rst<='1';

wait for 100 ns;

rst<='0';i<='0';

wait for 100 ns;

i<='1';

wait for clk_period*10;

-- insert stimulus here

wait;

end process;

END;
----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity sync_down is

Port ( i : in STD_LOGIC;

clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (3 downto 0);

qbar : out STD_LOGIC_VECTOR (3 downto 0));

end sync_down;

architecture Behavioral of sync_down is

signal count:STD_LOGIC_VECTOR (3 downto 0);

begin

process(i,clk,rst)

begin

if (rst='1') then q<="1111" ;qbar<= not q;


elsif (clk'event and clk='1') then

if (i='0') then count<= "1111" ;

else count<=count - 1;

end if;

q<=count;

qbar<=not q;

end if;

end process;

end Behavioral;
--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY sync_downtest IS

END sync_downtest;

ARCHITECTURE behavior OF sync_downtest IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT sync_down

PORT(

i : IN std_logic;

clk : IN std_logic;

rst : IN std_logic;

q : INOUT std_logic_vector(3 downto 0);

qbar : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal i : std_logic := '0';


signal clk : std_logic := '0';

signal rst : std_logic := '0';

--BiDirs

signal q : std_logic_vector(3 downto 0);

--Outputs

signal qbar : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: sync_down PORT MAP (

i => i,

clk => clk,

rst => rst,

q => q,

qbar => qbar

);

-- Clock process definitions

clk_process :process
begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

rst<='1';

wait for 10 ns;

rst<='0';i<='0';

wait for 10 ns;

i<='1';

wait for clk_period*10;

-- insert stimulus here

wait;

end process;
END;

Test bench code(t flipflop)


LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY tfft IS

END tfft;

ARCHITECTURE behavior OF tfft IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT tff

PORT(

t : IN std_logic;

clk : IN std_logic;

en : IN std_logic;

q : INOUT std_logic;

qbar : INOUT std_logic


);

END COMPONENT;

--Inputs

signal t : std_logic := '0';

signal clk : std_logic := '0';

signal en : std_logic := '0';

--Outputs

signal q : std_logic;

signal qbar : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: tff PORT MAP (

t => t,

clk => clk,

en => en,

q => q,

qbar => qbar


);

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

en<='0';

wait for clk_period*10;

en<='1'; t<='0';

wait for clk_period*10;

t<='1';
-- insert stimulus here

wait;

end process;

END;

Code (t flipflop)
----------------------------------------------------------------------------------
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity tff is

Port ( t : in STD_LOGIC;

clk : in STD_LOGIC;
en : in STD_LOGIC;

q : inout STD_LOGIC;

qbar : inout STD_LOGIC);

end tff;

architecture Behavioral of tff is

begin

process(t,clk,en)

begin

if (en='0') then q<='0'; qbar<= not q;

elsif (clk'event and clk='1') then

if (t='0') then q<='0' ;qbar<= not q;

else q<= not q ;qbar <= not qbar;

end if;

end if;

end process;
Functional program
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity tff is

Port ( t : in STD_LOGIC;

rst : in STD_LOGIC;

clk : in STD_LOGIC;

q : inout STD_LOGIC;

qbar : inout STD_LOGIC);

end tff;

architecture Behavioral of tff is

begin

process(t,rst,clk)

begin

if (rst='1') then q<='0' ;qbar<= not q;

elsif (clk'event and clk='1') then

if (t='0') then q<='0' ;qbar<= not q;


else q<= not q ;qbar<= not qbar;

end if;

end if;

end process;

end Behavioral;

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity async_up is

Port ( i : in STD_LOGIC;

clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (3 downto 0);

qbar : out STD_LOGIC_VECTOR (3 downto 0));


end async_up;

architecture Behavioral of async_up is

component tff

Port ( t : in STD_LOGIC;

rst : in STD_LOGIC;

clk : in STD_LOGIC;

q : inout STD_LOGIC;

qbar : inout STD_LOGIC);

end component;

signal w1,w2,w3,w4: STD_LOGIC;

begin

U1: tff port map(i,rst,clk,q(0),w1);

U2: tff port map('1',rst,w1,q(1),w2);

U3: tff port map('1',rst,w2,q(2),w3);

U4: tff port map('1',rst,w3,q(3),w4);

end Behavioral;

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