EXP 1: (comment all clock line comment)
Half adder:
Synthesis:
begin
s<=a xor b;
c<=a and b;
Test Bench:
begin
a<='0';
b<='0';
-- hold reset state for 100 ns.
wait for 100 ns;
a<='0';
b<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
a<='1';
b<='0';
-- hold reset state for 100 ns.
wait for 100 ns;
a<='1';
b<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
Full Adder:
Synthesis:
begin
s<=(x xor y)xor z;
c<=((x xor y) and z) or (x and z);
Test Bench:
begin
x<='0';
y<='0';
z<='0';
-- hold reset state for 100 ns.
wait for 100 ns;
x<='0';
y<='1';
z<='0';
-- hold reset state for 100 ns.
wait for 100 ns;
x<='0';
y<='0';
z<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
x<='0';
y<='1';
z<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
x<='1';
y<='0';
z<='0';
-- hold reset state for 100 ns.
wait for 100 ns;
x<='1';
y<='0';
z<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
x<='1';
y<='1';
z<='0';
-- hold reset state for 100 ns.
wait for 100 ns;
x<='1';
y<='1';
z<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
EXP-02
(Check Libraries: use IEEE.STD_LOGIC_unsigned.ALL;) add this library
on top below .all library
(comment all clock line comment)
Synthesis:
begin
process(a,b,sel)
begin
case sel is
when"000"=>y<=a+b;
when"001"=>y<=a-b;
when"010"=>y<=a and b;
when"011"=>y<=a or b;
when"100"=>y<=a nand b;
when"101"=>y<=a nor b;
when"110"=>y<=not a;
when"111"=>y<=a;
when others=>null;
end case;
end process;
Test Bench
begin
a<="0101";
b<="0100";
sel<="000";
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0101";
b<="0100";
sel<="001";
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0101";
b<="0100";
sel<="010";
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0101";
b<="0100";
sel<="011";
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0101";
b<="0100";
sel<="100";
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0101";
b<="0100";
sel<="101";
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0101";
b<="0100";
sel<="110";
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0101";
b<="0100";
sel<="111";
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
EXP 3: (Here don’t comment clock line)
Synthesis:
signal temp:STD_LOGIC_VECTOR( 3 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
case sel is
when"00"=> temp<= si&temp(3 downto 1);
so <=temp(3);
when"01"=> temp<= si&temp(3 downto 1);
po<=temp;
when others=>null;
end case;
end if;
end process;
end Behavioral;
Test Bench:
-- Stimulus process
stim_proc: process
begin
sel<="00";
si<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
sel<="01";
si<='1';
wait for 100 ns;
sel<="10";
pin<="1100";
wait for 100 ns;
sel<="11";
pin<="1100";
--=wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
EXP 4(use libraries)&(Don’t comment clock lines)
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
Synthesis:(Add below architecture line)
signal count: std_logic_vector(2 downto 0);
begin
process(clk)
begin
if (clr='1') then count <= "000";
elsif (rising_edge (clk)) then
if (count="100")
then count <= "000";
else
count<=count+ 1;
end if;
end if;
end process;
q<=count;
end Behavioral;
Test Bench:
-- Stimulus process
stim_proc: process
begin
clr<='1';
-- hold reset state for 100 ns.
wait for 20 ns;
clr<='0';
-- hold reset state for 100 ns.
wait for 20 ns;
-- hold reset state for 100 ns.
-- wait for 100 ns;
-- wait for clk_period*10
-- insert stimulus here
wait;
end process;
Exp 5:fifo(here in last of testbench clock line is not
commented don’t change)
Libraries: (use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
Synthesis (Below architecture)
type memory_type is array (0 to 7) of std_logic_vector(3 downto 0);
signal memory: memory_type :=(others=>(others=> '0'));
signal readptr,writeptr: std_logic_vector(2 downto 0) :="000";
signal count : std_logic_vector(2 downto 0):="000";
signal newclk : std_logic;
signal count1 : std_logic_vector(25 downto 0);
begin
-----------------------------------------------------------------
clk_div1: process(clk,rst)
begin
if rst='1' then
count1<=(others =>'0');
elsif clk'event and clk='1' then
count1<=count1+'1';
end if;
end process;
-----------------------------------------------------------------
newclk<=count1(25);
clk_div<=count1(25);
-----------------------------------------------------------------
fifo_emty_full: process(readptr,writeptr,count)
begin
if(count="000") then
FF_empty<='1';
FF_full<='0';
elsif(count="111")then
FF_empty<='0';
FF_full<='1';
end if;
end process;
-----------------------------------------------------------------
count1_reptr_wdptr: process(newclk,rst,enr,enw,readptr,writeptr)
begin
if rst='1' then
count<="000";
readptr<=(others=>'0');
writeptr<=(others=>'0');
else if newclk'event and newclk='1' then
if enw='1' and enr='0' then
count<=count+'1';
if count="111" then
count<=count;
end if;
readptr<=readptr;
writeptr<=writeptr+1;
elsif enw='0' and enr='1' then
count<=count-'1';
if count="000" then
count<=count;
end if;
readptr<=readptr+1;
writeptr<=writeptr;
else
null;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------
mem_read_write:process(newclk,count,enw,enr)
begin
if(newclk'event and newclk='1') then
if enw='1' and enr='0' then
if count /="111" then
memory(conv_integer(writeptr))<=datain;
end if;
elsif enw='0' and enr='1' then
if count /="000" then
dataout<=memory(conv_integer(readptr));
end if;
end if;
end if;
end process;
end Behavioral;
Test Bench:
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst<='1';
enr<='0';
enw<='1';
dataout<="0110";
wait for 100 ns;
rst<='0';
enr<='0';
enw<='1';
dataout<="1100";
wait for 100 ns;
rst<='0';
enr<='1';
enw<='0';
dataout<="1100";
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
Exp 6:LCD
Synthesis: (ChatGPT Code)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity EXp006 is
Port ( rst, clk : in STD_LOGIC;
lcd_RS : out STD_LOGIC;
din : in STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0);
lcd_EN : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end EXp006;
architecture Behavioral of EXp006 is
signal div_count : std_logic_vector(20 downto 0);
signal clk_new : std_logic;
-- Define an enumerated type for state
type state is (reset, fuction, mode, cur, clear, d0, d1, d2, fuction1, mode1, cur1, clear1, d01, d11,
d21);
signal pss, nx : state;
begin
clk_DIV: process(clk, rst)
begin
if rst = '1' then
div_count <= (others => '0');
elsif rising_edge(clk) then
div_count <= div_count + '1';
end if;
end process;
clk_new <= div_count(20);
p_state_transition: process (clk_new, rst)
begin
if rst = '1' then
pss <= reset;
elsif rising_edge(clk_new) then
pss <= nx;
end if;
end process;
LCD_working: process (pss)
begin
case pss is
when reset =>
lcd_RS <= '0';
lcd_EN <= '1';
data_out <= "00111100"; --3Ch
nx <= fuction;
when fuction =>
lcd_RS <= '0';
lcd_EN <= '1';
data_out <= "00111100"; --3Ch
nx <= fuction1;
when fuction1 =>
lcd_RS <= '0';
lcd_EN <= '0';
data_out <= "00111100"; --3Ch
nx <= mode;
when mode =>
lcd_RS <= '0';
lcd_EN <= '1';
data_out <= "00000110"; --06h
nx <= mode1;
when mode1 =>
lcd_RS <= '0';
lcd_EN <= '0';
data_out <= "00000110"; --06h
nx <= cur;
-- Continue with other cases similarly
-- (omitting repetitive assignments for brevity)
when others =>
null;
end case;
end process;
end Behavioral;
TestBench (As it is from mam code)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY LCDTEST IS
END LCDTEST;
ARCHITECTURE behavior OF LCDTEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LCD_SIMPLE_Practice
PORT(
rst : IN std_logic;
clk : IN std_logic;
lcd_RS : OUT std_logic;
lcd_EN : OUT std_logic;
data_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal lcd_RS : std_logic;
signal lcd_EN : std_logic;
signal data_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LCD_SIMPLE_Practice PORT MAP (
rst => rst,
clk => clk,
lcd_RS => lcd_RS,
lcd_EN => lcd_EN,
data_out => data_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
rst<='0';
--din<="00101010";
wait for 100 ns;
rst<='1';
--din<="00101010";
-- hold reset state for 100 ns.
rst<='0';
--din<="00101010";
wait for 100 ns;
rst<='1';
--din<="00111111";
--hold reset state for 100 ns.
wait for 100 ns;
rst<='0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
