LAB02 report.

Name: Le Duc Vu Student’s ID: 18021443

Assignment: LAB02 Group 5

1. Flip-flops and latches

1.1.Different types of Flip-flops.

Figure 1: waveform of the ffs module.

Looking at the simulation result, it is immediately evident that all 3 1-bit flip-flops all share the
same clk, rst_n wires, therefore they are synchronous resettable flip-flops. The reason why the
sensitivity list only contains clk, and rst_n signals is that these signals are used for synchronize
and reset 3 1-bit flip-flops.

1.2. Modelling T flip-flops.

library ieee;
use ieee.std_logic_1164.all;
entity T_flip_flop is
port (clk,t,en,rst : in std_logic;
Q, Qnot: out std_logic;
);
 end T_flip_flop;
architecture TFF_arch of T_flip_flop is
signal op: std_logic;
begin
process(clk, rst) is
begin
if(en='0') then op<='Z';
elsif (en='1' and rst='1') then
op <= '0';
elsif (clk'event and clk='1'and en='1') then
if(t='1') then op <= not op;
else op <= op;
end if;
end if;
end process;
Q <= op;
Qnot <= not op;
end TFF_arch;
Table 1: T flip-flop.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity T_flip_flop_tb is
end;
architecture sim_T of T_flip_flop_tb is
component T_flip_flop
port (clk,t,en,rst: in STD_LOGIC;
Q, Qnot: out STD_LOGIC);
end component;

signal t, en, rst, Q, Qnot :STD_LOGIC;

signal clk : std_logic := '0';
constant clk_period : time := 10 ns;

begin
dut:T_flip_flop
port map(clk=> clk,
t=>t,
en=>en,rst=>rst,Q=>Q,Qnot=>Qnot);
clk_process :process
begin
clk <= '0'; wait for clk_period/2;
clk <= '1'; wait for clk_period/2;
end process;
--
simu:process
begin
 rst<='1'; en<='0'; wait for clk_period;
t<='1'; en<='0'; wait for clk_period;
en<='1';wait for clk_period;
t<='0';wait for clk_period;
t<='1';wait for clk_period;
end process;

end;
Table 2: Testbench of T flip flop.

Figure 2: Simulation result of D flip flop.

2. Binary Counter
2.1.Behavior description of a binary counter with asynchronous reset and synchronous set

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Binary_counter is
generic (DataWidth: integer :=8);
port(

clk: in std_logic;
rst_n: in std_logic;
enable: in std_logic;
set: in std_logic;
data_in: in std_logic_vector (DataWidth-1 downto 0);
counter_out: out std_logic_vector (DataWidth-1 downto 0));
end Binary_counter;

architecture beh of Binary_counter is

signal tmp: std_logic_vector (DataWidth-1 downto 0);
begin
BCounter: process (clk,rst_n,set,enable)
begin
if (rst_n = '0') then
tmp <= "00000000";
elsif (set = '1') then
 tmp <= data_in;
elsif rising_edge(clk) then
if (enable = '1') then
tmp <= (tmp + 1);
end if;
end if;
end process BCounter;
counter_out <= tmp;
end beh;

Table 3: Behavior description of the counting-up binary counter in VHDL:

Figure 3: simulation result of the binary counter.

3. Parallel to serial converter

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parallel_in_serial_out is
port(
clk : in std_logic;
rst_n : in std_logic;
load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic;
ready_out: out std_logic
)
end parallel_in_serial_out;

architecture behavior of parallel_in_serial_out is

begin

piso : process (clk,rst_n,load,data_in) is

variable temp : std_logic_vector (data_in'range);
begin
if (rst_n='0') then
 temp := (others=>'0');
elsif (load = '1') then
temp := data_in ;
ready_out <= '0';
elsif (rising_edge (clk)) then
data_out <= temp(15);
temp := temp(14 downto 0) & '0';
ready_out <= '1';
end if;
end process piso;

end behavior;
Table 4: Paralell to serial converter.

library ieee;
use ieee.std_logic_1164.all;

entity piso_tb is

end piso_tb;

architecture test_bench of piso_tb is

component parallel_in_serial_out
port(
clk : in std_logic;
rst_n : in std_logic;
load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic;
ready_out: out std_logic
);
end component parallel_in_serial_out;

signal rst_n_tb: std_logic;

signal load_tb: std_logic;
signal data_out_tb: std_logic;
signal ready_out_tb: std_logic;
signal data_in_tb: std_logic_vector(15 downto 0);

signal clk_tb: std_logic :='0';

begin
pisoTB: parallel_in_serial_out
port map ( clk => clk_tb,
rst_n => rst_n_tb,
 load => load_tb,
data_in => data_in_tb,
data_out => data_out_tb,
ready_out => ready_out_tb
);

clk_tb <= not clk_tb after 10 ns;

WAVEFORM: process
begin
rst_n_tb <= '0';
wait for 10 ns;
rst_n_tb <= '1';

data_in_tb <= "1011010010011100";

load_tb <= '1';
wait for 10 ns;
load_tb <= '0';

wait for 330 ns;

--wait until ready_out_tb = '0';

end process;
end test_bench;

CONFIGURATION test_bench_cfg OF piso_tb IS

FOR test_bench
END FOR;
END test_bench_cfg;
Table 5: testbench of the converter.

Figure 4: simulation result of the parallel to serial data converter.

 Parallel to serial converter

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parallel_in_serial_out is
GENERIC ( DATA_WIDTH : INTEGER := 16);
port(
 clk : in std_logic;
rst_n : in std_logic;
load : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : out std_logic;
ready_out: out std_logic
);
end parallel_in_serial_out;

architecture piso_structure of parallel_in_serial_out is

COMPONENT ff1
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
d : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END COMPONENT;

component mux

PORT (
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
c : IN STD_LOGIC;
f : OUT STD_LOGIC
);

END component;

signal t : std_logic_vector (DATA_WIDTH+2 downto 0);

begin

piso_gen0: for i in 0 to (DATA_WIDTH - 2)/2 generate

mux_map: mux port map (i0 => t(i+i+1), i1 => data_in(DATA_WIDTH - 2 - i), c => '1', f
=> t(i+i+2));
END GENERATE piso_gen0;

ff1_map0: ff1 port map (clk => clk, rst_n => rst_n, d => data_in(DATA_WIDTH - 1), q => t(1));

piso_gen1: for i in 0 to (DATA_WIDTH - 4)/2 generate

ff1_map1: ff1 port map (clk => clk, rst_n => rst_n, d => t(i+i+2), q => t(i+i+3));
END GENERATE piso_gen1;

ff1_map2: ff1 port map (clk => clk, rst_n => rst_n, d => t(DATA_WIDTH+2), q => data_out);
end piso_structure;
Figure 5: Parallel to Serial converter using D-flip-flop.