Department of Electrical Engineering

ELEC261 - Digital Systems Design

Sequential Circuit Design using VHDL

ELEC261
&
VHDL Testbench

Lecture 10 Prof. F Bensaali

 Sequential Circuit
Design using VHDL

2
Content:
• Sequential logic
• Synchronous/Asynchronous sequential logic
• D Flip-Flop
• Counter

3
 Sequential logic
Sequential logic

 Digital electronics is classified into:

o Combinatorial logic
o Sequential logic
 Combinatorial logic: output is a function of, and only of, the
present input
 Sequential logic : output depends not only on the present
input but also on the history of the input
o It has storage (memory)
outputs

Inputs
Combinatorial
logic Memory
element

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 Synchronous/Asynchronous Sequential
Synchronous/Asynchronous sequential logic
logic

 Two types of sequential circuits:

o Synchronous sequential circuits

o Asynchronous sequential circuits

 Synchronous: logic responds to changes of input signals

according to the state of a clock signal

 Asynchronous: logic responds to the external system almost

instantly

5
 D Flip-Flop
D Flip-Flop
Truth table
D Q CLK D Q (t+1)

0 - Q (t)
D Flip-Flop
1 0 0
CLK
1 1 1

Timing diagram
t0 t1 t2 t3

CLK

Q
Time

6
 D Flip-Flop
D Flip-Flop (Cont’d)
(Cont’d)

entity DFF is
port( D: in std_logic;
CLK: in std_logic;
Q: out std_logic );
D Q end DFF;
----------------------------------------------
D Flip-Flop architecture DFF_arch of DFF is
begin
CLK
process (CLK)
begin

-- clock rising edge

Detecting Rising Clock Edge: if (CLK='1' and CLK'event) then

Q <= D;
(CLK='1' and CLK'event) or end if;
rising_edge(CLK) end process;
end DFF_arch;
Detecting Falling Clock Edge?

7
 D Flip-Flop
D Flip-Flop with
with Asynchronous
Asynchronous RESET
RESET

D Q

D Flip-Flop

CLK

ARESET

Timing diagram t0 t1 t2 t3

CLK

ARESET

Q
Time

8
D Flip-Flop
D Flip-Flop with
with Asynchronous
Asynchronous RESET
RESET (Cont’d)
(Cont’d)

entity DFF is
port( D: in std_logic;
CLK: in std_logic;
ARESET in std_logic;
Q: out std_logic );
end DFF;
----------------------------------------------
architecture DFF_arch of DFF is
D Q begin

D Flip-Flop process (CLK, ARESET)

begin
CLK if (ARESET =’1’) then
Q <= '0';
ARESET elsif (CLK='1' and CLK'event) then
Q <= D;
end if;

end process;

end DFF_arch;

9
 D Flip-Flop
D Flip-Flop with
with Synchronous
Synchronous RESET
RESET

Exercise entity DFF is

port( D, CLK, SRESET: in std_logic;
Q: out std_logic );
D Q end DFF;

D Flip-Flop -----------------------------------------------------------------------------------
architecture DFF_arch of DFF is
CLK
?
SRESET
end DFF_arch;

Timing diagram
t0 t1 t2 t3

CLK

SRESET

Q
Time
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 D Flip-Flop
D Flip-Flop with
with Synchronous
Synchronous RESET
RESET (Cont’d)
(Cont’d)

Solution
entity DFF is
port( D: in std_logic;
CLK: in std_logic;
SRESET: in std_logic;
Q: out std_logic );
end DFF;
----------------------------------------------
D Q architecture DFF_arch of DFF is
begin
D Flip-Flop
process (CLK)
begin
CLK
if (CLK='1' and CLK'event) then
SRESET
if (SRESET =’1’) then
Q <= ’0’;
else
Q <= D;
end if;
end if;
end process;

end DFF_arch;

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 2-bit counter
2-bit counter with
with Asynchronous
Asynchronous RESET
RESET

Exercise
entity counter is
port( CLK, RESET: in std_logic;
RESET
O: out std_logic_vector (0 to 1) );
end counter;
O -----------------------------------------------------------------------------------
Counter
0 to 3 2 architecture counter_arch of counter is

?
CLK

end counter_arch;

Timing diagram
t0 t1 t2 t3 t4 t5 t6 t7 t8

CLK

RESET

OU 0 1 2 0 1 2 3 0 1 2 3

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2-bit counter
2-bit counter with
with Asynchronous
Asynchronous RESET
RESET (Cont’d)
(Cont’d)

Solution
entity counter is
port( CLK, RESET: in std_logic;
O: out std_logic_vector (0 to 1) );
end counter;
-----------------------------------------------------------------------------------
architecture counter_arch of counter is
signal O_sig: std_logic_vector(0 to 1);
RESET
begin
O
Counter
2 process(CLK, RESET)
0 to 3
begin
CLK if (RESET = '1') then
O_sig <= "00";
elsif (CLK = '1' and CLK'event) then
O_sig <= O_sig + 1;
end if;
end process;

-- concurrent assignment statement

O <= O_sig;
end counter_arch;
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VHDL Testbench

14
Content:
• WAIT statement
• ASSERTION statement
• Writing a VHDL testbench
o Testbench template
o Example

15
 WAIT statement
WAIT statement

 The wait statement explicitly specifies the conditions under

which a process may resume execution after being suspended

wait for time expression;

wait on signal;

wait until <condition>;

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 WAIT statement
WAIT statement (Cont’d)
(Cont’d)

1. Causes suspension of the process for a

1- wait for time expression;
period of time given by the evaluation of
time expression wait for 10 ns;

2. Causes a process to suspend execution 2- wait on signal;

until an events occurs on one or more wait on clk, reset;
signals in a group of signals
3- wait until <condition>;
3. The third form can specify a <condition>
wait until A>B;
that evaluates to a Boolean value, TRUE or
FALSE

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 WAIT statement
WAIT statement (Cont’d)
(Cont’d)

Example
A process that generates a clock with a
-- Clock generation process
10ns period
Clock_gen: process

begin
CLK <= '0';
wait for 5 ns;
CLK <= '1';
wait for 5 ns;
end process clock_gen;

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 Assertion statement
Assertion statement

 A statement that checks that a specified condition is true and

reports an error if it is not
Must evaluate to a Boolean value (true or false)
If false, it is said that an assertion violation occurred

assert condition A message to be reported when assertion

violation occurred
report string
Predefined severity names are:
severity severity_level; NOTE: used to pass information messages from
simulator
WARNING: used in unusual situation in which
the simulation can be continued
ERROR: used when assertion violation makes
continuation of the simulation not feasible
FAILURE: used when the assertion violation is
a fatal error and the simulation must be stopped

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 Assertion statement
Number (Cont’d)
systems

Example

assert (c = '0')
report "Case 1 returns an error"
severity error;

When the value of output c is NOT equal ’0’, the message is

displayed and the simulation is stopped because the severity
is set to error

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 VHDL testbench
VHDL testbench

 A testbench is a specification in VHDL that plays the role of a

complete simulation environment for the analysed Design

o Analysed design: Unit Under Test (UUT)

 A testbench contains:

o The UUT
o Stimuli for the simulation

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 VHDL testbench
VHDL testbench (Cont’d)
(Cont’d)

 The UUT is instantiated as a component of the testbensh

 The architecture of the testbench specifies stimuli for the UUT’s
ports
Top Level

no
I/O
component
no
no I/O
I/O

port
map

Unit Under Test

(UUT)

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 Testbench template
Testbench template

testbench
Unit Under
Test Tester
(UUT)

entity test_bench_name is --the entity interface is empty

entity model_name is end test_bench_name;
port (input_signals: in type;
output_signals: out type); architecture test_bench_arch of test_bench_name is
end model_name; -- Component declaration for the UUT
architecture model_arch of model_name is component model_name is
[Declarations] port (input_signals: in type;
output_signals: out type);
begin end component;
architecture body --Declare all signals used to connect tester and model
end model_arch; signal internal_signals : type := initialisation;
begin
-- Instantiate the UUT
uut: model_name port map ( port => signal1, … );
-- Place stimulus here
end test_bench_arch;

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 Testbench example
Testbench example

entity Testand_gate is
library ieee ; end Testand_gate;
use ieee.std_logic_1164.all; architecture stimulus of Testand_gate is
component and_gate is
entity AND_GATE is port (
port( A, B: in std_logic; A, B: in std_logic;
C: out std_logic C: out std_logic
); );
end AND_GATE; end component;
signal A, B, C: std_logic;
architecture AND_ARCH of AND_GATE is
begin
DUT:and_gate port map (A => A,B => B,C => C);
begin
STIMULUS0:process
begin
C <= A and B;
-- case 1
A <= '0'; B <= '0';
end AND_ARCH ; wait for 50ns;
assert (c='0') report "Case 1 returns an error" severity error;
-- case 2
A <= '0'; B <= '1';
AND gate VHDL code VHDL testbench wait for 50ns;
assert (c='0') report "Case 2 returns an error" severity error;
-- case 3
A <= '1'; B <= '0';
wait for 50ns;
assert (c='0') report "Case 3 returns an error" severity error;
-- case 4
A <= '1'; B <= '1';
wait for 50ns;
assert (c='1') report "Case 4 returns an error" severity error;
end process;

Simulation result end architecture;

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 Testbench template
Testbench example (Cont’d)
(Cont’d)

-- case 1
A <= '0'; B <= '0';
wait for 50ns;
assert (c='1') report "Case 1 returns an error" severity error;

FALSE

Error: Case 1 returns an error

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