An Effective Approach for Building Low-Power

General Activity-Driven Clock Trees

Chen-Hsien Lin†, Shih-Hsu Huang†, Wei-Kai Cheng‡
†
Department of Electronic Engineering, Chung Yuan Christian University, Taoyuan, Taiwan
‡
Department of Information & Computer Engineering, Chung Yuan Christian University, Taoyuan, Taiwan
g10576015@cycu.edu.tw, shhuang@cycu.edu.tw, wkcheng@cycu.edu.tw

Abstract—It is known that clock gating is a useful technique 1001, respectively. In other words, module M1 is idle at cycle
to reduce power consumption. Based on activity patterns of 1, active at cycle 2, active at cycle 3, and active at cycle 4;
modules, previous works utilized AND gates to construct activity- module M2 is idle at cycle 1, active at cycle 2, active at cycle
driven gated clock trees. Recently, it was pointed out OR gates 3, and idle at cycle 4; and so on.
can be used at the bottom level for further power saving. In this
paper, we present a general activity-driven clock tree structure in Fig. 1 gives the activity-driven clock tree built by the
which both AND gate and OR gate can be utilized at any node. previous work [3], which only use AND gates. As shown in
Based on this general structure, an effective synthesis algorithm Fig. 1, the total active cycles at level 1 (i.e., the bottom level),
is proposed. Benchmark data show that the proposed approach level 2, level 3, level 4, and level 5 are 32, 21, 13, 8, and 4,
can reduce 11.3% clock power consumption. respectively. The summation of active cycles of all the clock
gates is 78. Suppose that the power consumption of each clock
Keywords—Activity Patterns, Clock Gating, Clock Tree, Low gate at an active cycle is 10 μW. Then, clock power
Power, Design Methodology) consumption is 780 μW.

I. INTRODUCTION Clock 1 - Active

0 - Idle
It is recognized that clock gating [1,2] is one of the most
useful techniques to reduce clock power consumption. Based
on activity patterns of modules, activity-driven clock trees [3-
6] are used to represent gated clock trees. Several works [3-6]
have tried to construct low-power activity-driven clock trees by
using only AND gates to merge nodes with similar activity
patterns to disable the clock signal as possible. Different from
previous works [3-6] that only used AND gates, Lin et al. [7]
utilized OR gates at the bottom level for further power saving.
However, they [7] did not use OR gates at other levels of gated
clock tree. Furthermore, they [7] restrict that the gates at the
same level must use in the same logical type. In this paper, we M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15
present a general activity-driven clock tree structure in which Fig. 1. Clock tree obtained by previous work [3].
both AND gate and OR gate can be utilized at any node of
gated clock tree. Based on this general structure, we propose an Clock 1 - Active

effective synthesis algorithm for building a low-power activity- 0 - Idle

driven clock tree. Since the trade-off between AND gates and
OR gates are made during the stage of activity-driven clock
tree construction, clock power consumption can be greatly
minimized. Compared with previous work [7], benchmark data
show that our approach can reduce 11.3% clock power
consumption.

II. MOTIVATION
In this section, we use an example to demonstrate the
motivation of general activity-driven clock tree structure. This
circuit has fifteen modules M1 ~ M15. The activity patterns of M3 M1 M11 M7 M5 M6 M9 M2 M8 M10 M14 M15 M4 M13 M12
modules M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, Fig. 2. Clock tree obtained by our approach.
M12, M13, M14 and M15 are 0111, 0110, 0100, 1000, 1100,
1110, 1111, 1010, 0010, 1011, 0011, 0101, 1101, 0001 and Fig. 2 gives the activity-driven clock tree constructed by

978-1-5386-7960-9/18/$31.00 ©2018 IEEE 13 ISOCC 2018

our approach (i.e., both AND gates and OR gates can be In the experiments, we adopt seven circuits from ISCAS’89
considered to utilized at each node). As shown in Fig. 2, the benchmark suite to test the effectiveness of the proposed
total active cycles at level 1, level 2, level 3, level 4, and level 5 approach. These test circuits are targeted to TSMC 90nm
are 32, 12, 4, 4, and 4, respectively. The total active cycles of process technology. In each test circuit, we implement our
all the clock gates is 56. Then, clock power consumption approach, the previous work [3] (i.e., AND-gate-only clock
becomes only 560 μW. tree), the previous work [7] (i.e., OR gates at the bottom level)
for comparisons. For each activity-driven clock tree, we set 0.1
III. PROPOSED APPROACH ns as the clock skew constraint. Table I tabulates the
comparisons on their clock power consumptions. We find that,
In this section, we propose an approach to synthesize a low- in each test circuit, our approach has the smallest clock power
power general activity-driven clock tree (i.e., both AND gate consumption. Compared with previous work [3], in average,
and OR gate can be utilized at any node of gated clock tree). the proposed approach can reduce 29.2% clock power
Based on activity patterns of modules, the gated clock tree is consumption. Compared with previous work [7], in average,
constructed in the bottom-up manner. Here, due to page limit, the proposed approach can reduce 11.3% clock power
the detailed pseudo codes are omitted. In the following, we consumption.
highlight the basic ideas.
TABLE I. COMPARISONS ON CLOCK POWER CONSUMPTION.
For each level of gated clock tree, we try to apply two Power Consumption (nW) Reduction
strategies. In the first strategy, the activity patterns of parents Circuit
[3] [7] Ours Ours vs Ours vs
are directly propagated from their children. We select the [3] [7]
children whose total active cycles is 50% of the total cycles. s208.1 178.6 170.1 150.3 15.8% 11.6%
Take Fig. 3 as an example. In Fig. 3(a), children B3 and B4 are s349 387.0 278.9 252.7 34.7% 9.4%
selected since their total active cycles is 50% of the total cycle. s400 570.7 461.2 406.6 28.7% 11.8%
Then, the activity patterns of B9 and B10 are directly propagated s1269 893.2 653.5 584.0 34.6% 10.6%
s3271 2560.4 1992.9 1754.7 31.5% 12.0%
from B3 and B4, respectively. Moreover, we can use the AND- s6669 5319.4 4222.8 3721.6 3.00% 11.9%
ing of parent B9 to generate the activity pattern of child B2. s15850 12866.7 10398.8 9143.3 29.0% 12.1%
Average 29.2% 11.3%
If the first strategy is not applicable for some children, we
use the second strategy. In Fiug. 3, the activity patterns of B1,
B5, B6, B7 and B8 cannot be generated by only B3 and B4. In V. CONCLUSIONS
Fig. 3(b), we add parent B11 for generating activity patterns of In this paper, we present a novel approach to construct a
B1, B5, and B8. Similarly, in Fig. 3(c), we add B12 for general low-power activity-driven clock tree, in which both
generating activity patterns of B6 and B7. Note that the activity AND gate and OR gate can be utilized at any node of gated
patterns of B11 and B12 are determined by a greey (heuristic) clock tree. Compared with the conventional activity-driven
algorithm. clock tree, our approach can reduce 29.2% clock power
consumption. Compared with the activity-driven clock tree that
B9 B10 uses OR gates at the bottom level, our approach also can
reduce 11.3% clock power consumption.

B1 B2 B3 B4 B5 B6 B7 B8 ACKNOWLEDGMENT
(a) This work was supported in part by Ministry of Science and
Technology, Taiwan, under grant number 107-2218-E-033-
B9 B11 B10
007.

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