Scribd
Upload
57 views2 pages

Quiz 4 - Mock Test 2

This document contains 3 questions about digital logic circuits: 1) The first question asks to build a truth table and logic circuit for a function F using a 3:8 decoder and 74153 multiplexers. 2) The second question asks to build an adder circuit for 3-bit binary numbers using half adders. 3) The third question provides an incomplete truth table and timing diagram for a D flip-flop and asks to complete them.

Uploaded by

Adriana Mohd Samsul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
57 views2 pages

Quiz 4 - Mock Test 2

This document contains 3 questions about digital logic circuits: 1) The first question asks to build a truth table and logic circuit for a function F using a 3:8 decoder and 74153 multiplexers. 2) The second question asks to build an adder circuit for 3-bit binary numbers using half adders. 3) The third question provides an incomplete truth table and timing diagram for a D flip-flop and asks to complete them.

Uploaded by

Adriana Mohd Samsul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

QUIZ 4 – MOCK TEST 2

Q1) F(A,B,C,D) = B’D’ + AD’+B’C

i. Build the truth table for F output.


ii. Design the logic circuit for function F using 3:8 Decoder as shown in Figure Q1 (a)
iii. You are only provided with a few IC 74153 (Dual 4:1 Multiplexer) and its function table as
shown in the Figure Q1(b-c), perform output F using this Multiplexer.

(a)

Input
Data Inputs Enable Output
Selectors
SB SA nC0 nC1 nC2 nC3 nG nY
X X X X X X H L
L L L X X X L L
L L H X X X L H
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H
H H X X X L L L
H H X X X H L H
H: HIGH Level L : LOW Level X : Don’t Care
(b) (c)
Figure Q1

Q2) Using only half adders as shown in Figure Q2 and build the circuit to calculate addition of 3-bit
binary numbers A (A2A1A0) and B (B2B1B0) that yield C3S2S1S0

Figure Q2
QUIZ 4 – MOCK TEST 2

Q3) A D flip flop is connected as shown in Figure Q3(a), complete the function table (Table Q3) and
the timing diagram (Figure Q3(b)).

Figure Q3(a)

Table Q3

CLK PRE’ CLR’ A B Qnext FF State


↓ 0 1 X X 1 SET
↓ 1 0 X X 0 RESET
0,1 1 1 X X Q NC
↑ 0 1
↑ 1 0
↑ 1 1
↑ 1 1
↑ 1 1
↑ 1 1
1: HIGH State 0: LOW State NC: No Change

Figure Q3 (b)

You might also like