a.

‘timescale 1ns/1ps

The `timescale directive gives meaning to delays that may appear in a Verilog model. The
timescale is
placed above the module header and takes the form
`timescale time_unit / time_precision
 The `timescale directive can have a huge impact on the performance of most Verilog
simulators. It is a common new-user mistake to select a time_precision of 1ps (1 pico-second) in
order to account for every last pico-second in a design. adding a 1ps precision to a model that is
adequately modeled using either 1ns or 100ps time_precisions can increase simulation time by
more than 100% and simulation memory usage by more than 150%. I know of one very popular
and severely flawed synthesis book that shows Verilog coding samples using a `timescale of 1 ns
/ 1 fs[17] (measuring simulation performance on this type of design typically requires a calendar
watch!)
Globally changing the time_units of every `timescale in a design can adversely impact
the integrity of an entire design. Any design that includes #delays relies on the accuracy of the
specified time_units in the `timescale directive. Since the time_precision must always be equal to
or smaller than the time_unit in a `timescale directive, additional guidelines should probably be
followed if a global `timescale strategy is being employed:
Guideline: Make all time_units of user defined `timescales equal to 1ns or larger.
Reason: if a smaller time_unit is used in any model, globally changing all time_precisions to
1ns will break an existing design.
Note: If a vendor model is included in the simulation and if the vendor used a very small
time_precision in the their model, the entire simulation will slow down and very little will have
been accomplished by globally changing the time_precisions of the user models. To enhance
simulator performance, using a unit-delay simulation mode or using cycle based simulators are
better options than macro-generating all of the `timescales in a design.

EXAMPLES
`timescale 1ns/1ps
module alu_tb#(parameter n=4);
reg[n-1:0]a;
reg[n-1:0]b;
reg[2:0]sel;
wire[n-1:0]s;
wire c0;

alu a1(.a(a),.b(b),.sel(sel),.s(s),.c0(c0));
initial
begin
a=4'b0;b=4'b0;sel=4'b0;
$monitor($time,"a=%b,b=%b,sel=%b,s=%b,c0=%b",a,b,sel,s,c0); //$realtime:
same
#5 a=4'b0101;b=4'b1010;
#15 sel=3'b000;
#25 sel=3'b001;
#13 sel=3'b010;
#35 sel=3'b011;
#17 sel=3'b100;
#5 sel=3'b101;
#45 sel=3'b110;
#54 sel=3'b111;
#59 sel=3'b110;
a=4'b0111;
b=4'b1110;
end
endmodule

# 0a=0000,b=0000,sel=000,s=0000,c0=0
# 5a=0101,b=1010,sel=000,s=1111,c0=0
# 45a=0101,b=1010,sel=001,s=1011,c0=1
# 58a=0101,b=1010,sel=010,s=0110,c0=0
# 93a=0101,b=1010,sel=011,s=0100,c0=0
# 110a=0101,b=1010,sel=100,s=0000,c0=0
# 115a=0101,b=1010,sel=101,s=1111,c0=0
# 160a=0101,b=1010,sel=110,s=1111,c0=0
# 214a=0101,b=1010,sel=111,s=1010,c0=0
# 273a=0111,b=1110,sel=110,s=1001,c0=0
`timescale 1ns/1ps
module alu_tb#(parameter n=4);
reg[n-1:0]a;
reg[n-1:0]b;
reg[2:0]sel;
wire[n-1:0]s;
wire c0;

alu a1(.a(a),.b(b),.sel(sel),.s(s),.c0(c0));
initial
begin
a=4'b0;b=4'b0;sel=4'b0;
//$monitor($time,"a=%b,b=%b,sel=%b,s=%b,c0=%b",a,b,sel,s,c0);
$monitor($realtime,"a=%b,b=%b,sel=%b,s=%b,c0=%b",a,b,sel,s,c0);
#5.067 a=4'b0101;b=4'b1010;
#15.45 sel=3'b000;
#25.23 sel=3'b001;
#13.53 sel=3'b010;
#35.12 sel=3'b011;
#17.16 sel=3'b100;
#5.09 sel=3'b101;
#45.10 sel=3'b110;
#54.12 sel=3'b111;
#59.98 sel=3'b110;
a=4'b0111;
b=4'b1110;
end
endmodule

# 0a=0000,b=0000,sel=000,s=0000,c0=0
# 5a=0101,b=1010,sel=000,s=1111,c0=0
# 46a=0101,b=1010,sel=001,s=1011,c0=1
# 59a=0101,b=1010,sel=010,s=0110,c0=0
# 94a=0101,b=1010,sel=011,s=0100,c0=0
# 112a=0101,b=1010,sel=100,s=0000,c0=0
# 117a=0101,b=1010,sel=101,s=1111,c0=0
# 162a=0101,b=1010,sel=110,s=1111,c0=0
# 216a=0101,b=1010,sel=111,s=1010,c0=0
# 276a=0111,b=1110,sel=110,s=1001,c0=0

`timescale 1ns/1ps
module alu_tb#(parameter n=4);
reg[n-1:0]a;
reg[n-1:0]b;
reg[2:0]sel;
wire[n-1:0]s;
wire c0;
alu a1(.a(a),.b(b),.sel(sel),.s(s),.c0(c0));
initial
begin
a=4'b0;b=4'b0;sel=4'b0;
$monitor($realtime,"a=%b,b=%b,sel=%b,s=%b,c0=%b",a,b,sel,s,c0);
#5.34 a=4'b0101;b=4'b1010;
#15.76 sel=3'b000;
#25.45 sel=3'b001;
#13.123 sel=3'b010;
#35.876 sel=3'b011;
#17.85 sel=3'b100;
#5.64 sel=3'b101;
#45.156 sel=3'b110;
#54.756 sel=3'b111;
#59.5sel=3'b110;
a=4'b0111;
b=4'b1110;
end
endmodule
# 0a=0000,b=0000,sel=000,s=0000,c0=0
# 5.34a=0101,b=1010,sel=000,s=1111,c0=0
# 46.55a=0101,b=1010,sel=001,s=1011,c0=1
# 59.673a=0101,b=1010,sel=010,s=0110,c0=0
# 95.54900000000001a=0101,b=1010,sel=011,s=0100,c0=0
# 113.399a=0101,b=1010,sel=100,s=0000,c0=0
# 119.039a=0101,b=1010,sel=101,s=1111,c0=0
# 164.195a=0101,b=1010,sel=110,s=1111,c0=0
# 218.951a=0101,b=1010,sel=111,s=1010,c0=0
# 278.491a=0111,b=1110,sel=110,s=1001,c0=0
`timescale 100ns/1000ps // only 1,10 or 100 is valid in timeunit and also in precision
module alu_tb#(parameter n=4);
reg[n-1:0]a;
reg[n-1:0]b;
reg[2:0]sel;
wire[n-1:0]s;
wire c0;
alu a1(.a(a),.b(b),.sel(sel),.s(s),.c0(c0));
initial
begin
a=4'b0;b=4'b0;sel=4'b0;
$monitor($realtime,"a=%b,b=%b,sel=%b,s=%b,c0=%b",a,b,sel,s,c0);
#5.34 a=4'b0101;b=4'b1010;
#15.76 sel=3'b000;
#25.45 sel=3'b001;
#13.123 sel=3'b010;
#35.876 sel=3'b011;
#17.85 sel=3'b100;
#5.64 sel=3'b101;
#45.156 sel=3'b110;
#54.756 sel=3'b111;
#59.54 sel=3'b110;
a=4'b0111;
b=4'b1110;
end
endmodule

** Error in the specified time literal value of 1000. Expected value of 1, 10, or
100.