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Major 11111

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6 views2 pages

Major 11111

Uploaded by

jayesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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verilog

// File: d_flip_flop.v
// Simple D Flip-Flop for Vivado

`timescale 1ns / 1ps

module d_flip_flop (
input wire clk, // Clock input
input wire d, // Data input
output reg q // Output
);

always @(posedge clk) begin


q <= d; // Capture data on rising edge
end

endmodule
testbench
// File: d_flip_flop_tb.v
// Testbench for D Flip-Flop

`timescale 1ns / 1ps

module d_flip_flop_tb;

// Testbench signals
reg clk;
reg d;
wire q;

// Instantiate the D Flip-Flop


d_flip_flop uut (
.clk(clk),
.d(d),
.q(q)
);

// Generate clock: 10ns period


initial begin
clk = 0;
forever #5 clk = ~clk;
end

// Stimulus
initial begin
// Initialize inputs
d = 0;

// Apply some values


#10 d = 1;
#10 d = 0;
#10 d = 1;
#10 d = 1;
#10 d = 0;
#20 $finish;
end

endmodule

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