1.

Number System A = 1 B -0, C= 0 D-1

C=0 D=0
are the systems which
A -1 B - 1
Digital
systerns
A1 B= 0 C- 1 D= 1
eal with digital formation in the external
4 A 1 B-0 C= 0 D =0
(b) 2 and 3
world (a) 1 and4
(d) None of
these
analog signals (c) 1 only
(b) Use
c) Manipulate intormation
representation or
Q . T h e number of 1s in the binary
d Handle information
in digital form internally
(3 4096 15 256+5
16 3) are
are ditterent from diaital (b)9
Analog systems (a) 8
systems b e c a u s e (d) 12
(c) 10
use transistors
a) They sets of components is/areP
form Q.8 Which of the foliowing
b) They handle analog
intormation in
arbitrary boolean
sufficient to implement any
They handle intormation in digital form
slow function
d) They are
1. XOR gates NOT gates
digital circuits easier to design than 2 2 to 1 multiplexers
03 Why are

analog circuits? 3. AND gates XOR gates

4. Three-input gates that output
(4 B)Cfor
a) They do not control electricity precisely over
a wide range the inputs A B and C
b) They are made in the form of ICs. (a) 2 only (b) 1 and 3

of circuits are from the (c) 4 only (d) None of above

(c) All elements digital
same family. in
Q.9 Zero has two representation
d) They are smaller in size.
(a) Sign magnitude (b) 1scomplement
in (d) Both (a) (b)
gate can respond to an input signal
and
4 A digital (C) 2s complement
a) About a second Q.10 The 2s complement representation of (539)
(b) About a hundredth of a second hexadecimal is
C) A few billionth ofa second
(a) ABE (b) DBC
d) A few millisecond (a) 9E7
(c) DE5

Analog methods are not used for handling

Q.11 The decimal value 0 25
extremely precise information because to the binary value 0 1
(a) Is equIivalent
a) Precise information always involves
(b) Is equivalent to the binary value 0 01
numbers which are inherently digital
(C) Is equivalentto the binary value 0 O0111
limits to how closely an analog
(6) There are
(d) Cannot be represented precisely in binary
intormation
Signal can reproduce the
to be precise Q.12 Which ot the following computers is leastpowertul?
Analog information never need
(a) They are very expensive. (a) Minicomputer
the (b) Micro computer
What values of A, B C and D satisty
Simultaneous boolean ation?
(c) Main trame computer
following (d) Super computer
CD
AC. AB+ AC +CD =

A+AB =0, AB
218
Multiple Choice Questions:CS MADE ERSY
1 3 A device that works Q 24 (1101101 1011)
in conjunction witlacompulet
but not aspart ot it called (a) 109 687
is (b) 10
(a) Microprocessor b) Pepheral device (C)109 G88O (d) 119 08
(c) Hardware (d)Menory
Q 25 The decihal numther 122
IS expres
Q14 igital computers Used as
are more wiudely COmplement formas essed n
Commpared to anaiog computers because they aie
(a) 01111010 (b) 10KX)tO1
a) tasier to maintain
(c) 01001011 (d) 01110010
(b) Less expensiVe
(c)Always more accurate and taster Q.26 The 9's compliment of 33 is
(d Usetul over wider ranges of problem types (a) 33 (b) 44
(C) 39
Q.15 A haltbyte is known as
(d) 66
(a) Bug (b) Nibble Q.27 The 10's compiment of 15 is
(c) Data (d) Bit (a) 85 (b) 65
Q.16 The square of octal (c) 45 (d) 25
number 23 is
(a) 529 (b) 539 Q.28 The binary equivalent of (33),
(C) 551 (d) 650 (a) 100001 (b) 0010001
Q.17 Which of the following code is aweighted code (c) 100011 (d) None of these
(a) Gray
(b) Excess-3
(c) Shift counter Q.29 The equivalent binary code ot BCD
(d) 5111 number
Q.18 Which of the
10011000is
following 4 bit combination are invalid (a) 01001 100
(b) 10001001
in the BCD code?
(c) 0011101 (d) 1100010
(a) 0010 (b) 0101
(C) 110 Q.30 The Gray code of 10110
(d) 1100 is
equivalent to
(a) 01001 (b) 10111
Q.19 The code which uses 7
bits to represent a character (c) 11101 (d) 11011
S
(a) ASCII
(b) BCD Q.31 1101 0011 ?
(c) EBCDIC (a) 0110
(d) GRAY (b) 0101
Q.20 If (c) 1010
(123) (X3). then the
= (d) 0111
number of possible
values of x is Q.32 Match List-l with List-l| and select the
(a) 4
(b) 3 answer using the codes
correct
(c) 2 given below the ists
(d) 1 List-1 List-
Q.21 The binary A. 2421
equivalent of the decimal number 1. Sequential code
0 4375 is B. 8421
2. Retlective code
(a) 00111 C. XS3
(b) 0.1011 3. Non-reflecting code
(C) 01100
(d) 0 1010 Codes
Q.22 A B
Negative numbers can't be
Signed magnitude form represented in
(a) (a) 3
(b) 1's (b) 1 3
complement form (c) 1
(C) 2s 3
complement form (d) 3
(d) None of these 2

.23 Q.33 The result of the

(10110011100011110000),
(a) 22 14 7 16
in base 32 is
addition of the binary numbers
101.111and 1100.010 is
(b) 1192331
(C) 1197 16 (a) 11011.111
(d) 1114 23 16 (b) 11010111
(c) 11010.001
(d) 11011.010
 2. oolean Algebra and Logic Digital Logic Basic Lev
ithe f gic Gates
Gates
0.34
Which of
following boolean
the

reDresent distributive law? algebra

.42
Logic 1 in + ve
219

statements logic
system
(a) (A+ B)+ C (a) Zero level is
represented dy
A+(B
()A (B+C) =(A B)+ + C) (b) Lower
voltage level
(A
(c) A (B C)= (A B) C) (c) Higher
voltage level
C (d) Negative voltage
d) None of these
Q.43 An AND
of the following Circuit
3 5

boole algebra (a) ls a

memory CKT
represent commutative law? staterments (b) Gives an
output when all input signals
(a)(A B)+ C= A(B+ C) present simultaneously
are

() A(B+ C) (A: B) = (c) Is a ve OR

+(4 C gate
c)A+ B = B+ A (d) ls a linear CKT
(d) A A = A Q.44 The
following symbol represents a
36 Which of the follo llowing logic expression is
(a) 1 0 = 1 incorrect?
) 11 0 = 1
c) 1 1 1 1 (a) Inverter
(c) 1 1 =0 (b) Buffer
(c) Schmitt trigger
37 Let Xand Y be the input
and 2be the (d) Flip-flop
AND gate. The output of
a value of 2 is
given by Q.45 Match List-I with List-ll and select the correct
a)X+ Y (b)X
answer using the codes
given below the lists
c)XY (a)x List-1 List-ll
A. A B 0 1. A B
38 What logic gate is represented by the circuit
B. A+B =0 2. A B
shown below
C. A B 0 3 A1 and B = 1

D. A B =0 4. A 1 and B = 0

Codes:
Bulb A B C D
(a) 1 4

(b) 2
(c) 1
a) NAND (b)NOR
(a) EQUIVALENCE 2
c)AND
Q 46 The minmum Boolean expression for the following
39 The bool expression A BCequals
Circuit is
(b)(4 B)(4 C)
a)(A-)(A+C)
(d)None otthesSe
(4-BA C) A

positive AND gate ()NOR

OR gate
aal
is alsO a
negative
Oy
a NAND gate
( ) OR gate
AND gate
be ow
to get a high
must
ate in which al nputs (a) AR AC+ BC (b) A+ BC
UtDutis called a an (c) 4 B3 (d) A+B +C
NR gate
ainverter gate
 220 Multiple Choice Questions:CS DE ERSy
Q.47 The (C) One should cover all the Os
complement of the Boolean expressi preseny
AB BC + AC) Is complerment the resuiting exprese. and
(d) One should cover all the 1's Dre
SIOn
(a) (A
B)(BC A+ C) complement the resulting expressid set and
(b) (A
B)+(BC+ AC) SSIOn
(C)(A B) (B. C) (AC Q53 The boolean expression AB+ AB, A
Is independent of the boolean variable
C AC
(d)(A B) (B O(A+ C)
(a) A (b) B
Q48 Consider
tollowing gate network (c) C (d) None of these
Q.54 The XOR operator B is

D (a) Commutative
(b) Associative

Which one of the

Dfollowing gates is redundant?
(c) Distributive over AND operator
(d) Both (a) and (b)

(a) Gate No 1 Q.55 The number of possible boolean functions

(b) Gate No 2 that
can be defined for n boolean variables
(C) Gate No 3 (d) Gate No 4 ver
n-valued boolean algebra is
Q.49 The minimum number of NAND
gates required
to implement A+ (a) 2 (b) 2
AB+ ABC is equalto
(a) Zero (b) 1 (c) (d)
(C) 4 (d) 7

Q.56 The karnaugh map tor the boolean function Fot 4

Q.50 What is the boolean variables isgiven below where A, B

equivalent boolean expression in C

are don't care conditions. What values of 4 B

product-of-sums form for the Karnaugh map given
in the figure below? C. will result in the minimal expression?

AB
CD 00 01 11 10
00

01
1 B
11

10
(a) A B =C =1
(a) BD BD (b) B = C = 1; A = 0
(c) A = C = 1: B = 0
(b) (B+C+D) (B+ C+ D)
(d) A = B = 1: C = 0
(c) (B+ D) (B+ D)
Q.57 If one of the input to gate is inverted
(d) (B D) (B+ D) then it becomes an INHIBITOR
(a) AND (b) NANDD
Q.51 VWhich of the following expresSIons is not equivalent
to ?
(c) NOR (d) XOR

(a) NAND (b) NOR Q58 Find odd one out

(c)NAND 1 (d) NOR 1 1. AA A
Q.52 To get boolean expression in the product ot sum 2. 1+ A = 1+ A
3. A+ BC = (A + B) (A + C)
form, from a given Karnaugh map
(a) Dont care conditions should not be taken 4. A+ AC =A+C
(b) Don t care conditions, if present. should be (a) 2 and 4 (b) 2. 3 and 4
taken as zeroeS (C) 1 and 4 (d 4 only
 Which of the tollowin
5 9W h i c h

Digit Logic
Dut not assOCiative? operation is co Basic Level
(a) AND
(b) OR commutative Q67 The 221
c)NAND
(d) xOR NAND
(a) Bubbledgate
AND equIvalent
is
to
the talse
Choose
statemen b)Bubbled XOR
The leftmos
(a) column is
(c) Bubbled OR
rightmost column adjacent to the
(d) None of these
Maxterm groups may be b8 he
connection of cells formed by expressIon Y
Minterm group diagonai (a) A 8
AB AB Is
represented by
may be (b) A B
or horizontal connection oftormed
celIs
by vertical (c) A B
(d) AB
(a) G inings may occur in the Q69 For
1, 2. size of 2 the givern
r
3, n where K-map POS forn equation is
AB
The number of NOR gates
261
required to implement CD 00 01
NAND gate is 00
11 10
3 (b) 4 01 0
(c) 5
(d) 2 11 0
10 1 0 o1
62 Minimize expression of the expression
(a) tM(1. 3, 4 6.9 11. 12 14)
y= A(A+B)+B(A + B) is
(b) zM (0. 2.5. 7.8. 10. 10 11 15)
a) A+ AB (c) mM(1,3.
(b)A B (d)
4,7.8. 10. 11, 15)
(c) A+ B tM(O 2. 4, 7.9. 11, 12. 14)
(d) AB+ AB
Q70 Simplity the Boolean
63 The function function
represented by the Karnaugh map f= ABCD+
given below is: ACD AD
Which one of the
BC following is true?
(a) AD (b) BC
A 00 01 11 1 0
(C) ADC (d) None of these
0 1 0 1 0
Q.71 Which one of the
11 01 0 folliowing sets of gates are bess
suited for parity checking and parity generation?
a) AB (b) AB+ BC+ CA (a) AND. OR NOT gates
(b) XOR. XNOR gates
() Bec (d) ABC
(C) NOR gates
*
Ihe (d) NAND gates
don't care condition in K-map represented
byX, the value of Xis Q.72 Karmaugh map is used to
a) 0 (b) 0or 1 (a) Minimize the number of tlip-fiops in a digital
c) 1 (d) 0 and 1 Circuit
(b) Minimze the number ot gates only in digital
Which is odd one in K-map Circuit
a) Pairs (b) Triples (c) Minimize the number of gates and fan in of a
c) Quads (d) Octets digital circuit

precedence
(d) Design gates
When solving Boolean
h
expression, the is not tunctionally complete
descending order is Q73 Which of the toliowing
a) OR, AND, NOT, Parenthesis set?

(a) AND, OR (b)NOR

6) Parenthesi NOT,AND. OR (d) AND OR, NOT
(c) NAND
) arenthesis, OR, AND NOT
rarenthesis, AND, NOT OR
 M u l t i p l e C h o l c eQ u e s t i o n s : C S ADE ERSy
222 (a) Is slower

(b) Is faster
3. Combinational Circult
Operates at the sarne speed
as

Boolean algeDia
(c) rallel agde
pDara

conplicate
74 1he term Product of sum m
(d) Is more
adders are needed
many full
to.

a ANL'lunction of several
ANID lunctions
OR uncTOs
Q81 How
m-bit parallel
adder Coistruct
()OR unctonof several
an

(b) m
()ORfunctnonof several OR functions
(a) m / 2

several AND Tunctions (C) m-1 (d) m+ 1

() AND function of

the following Q82 ldentity the logic tunction performed by the

Q75 Which expr ession is computed by
CIrCut
NAND gate crcut diagiam shown in the given figure

NAND NAND NAND

NAND
fx.y
NAND

(a) Exclusive OR (b) Exclusive NOR

(a) + (b) (+y)
(c)'y (a) +VZ
(c) NANDD (d) NOR

a.76 What is the Boolean expression for the following Q.83 The logic expression for the output of the circuit
Circuit shown in the figure below is:

OR
Gate B
AND

B Gate
OR
GATE

D
C
D
(a) F(A B) = (A + B) (B+ 4)
(b) F(A B) =1 (Tautology) (a) AC+BC+CD (b) A+ B +CD
(c) FA B) = A B
(d) F(A B) =A (c) ABC+ CD (d) AB+ BC+ O
B(4A exclusive OR ed with B)
Q.77 A multiplexer is also Q.84 Which of the
known as following is termed as minimum error
(a) Coder (b) Decoder code?
(c) Data selector (d) Multivibrator (a) Binary code (b) Gray code
Q.78 The quantity 837 in (c) Excess 3 code (d) Octal code
excess-3 BCD code would
be represented as Q.85 The SOP form of given
(a) 1001 0011 0111 function
(b) 1000 0001 1001 y =
(A+ B+C+ D) (A+ B) is
(c) 1011 0110 1010
d) 1000 0011 0111
(a) y =ABCD+ AB (b) y =ABCD+ AB

Q.79 Half-adder is also known as

(c) y =ABCD + AB (d) y =
ABCD+ AB
a) AND gate
(b) NAND gate Q86 Full adder
(c) NOR gate
(d) EX-OR gate
forms
(a) The sum of two bits and a
Q.80 A (b) The sum of two
previous carry
comparison between serial and binary values of 4-bit
reveals that serial parallel adder (c) The sum of two decimal
order values
(d) The sum of two
octal values with cary
 Digital Logic
QOE E R S 5

Basic Level 223

/7 e lerONTET WhICh is tnue?
(b Codes
A B

a 0 - / hne deCOVEr. the mand nrepresented

as number ot

a) nput ines and output lines respectively

) utput ihnes and input ines respectivelN

Number of galeS dd Outut lines respectivey 4. Sequential Circuits

N o n e of these
9 4 h e tme required tor a pulse to change trom T0

The reverse operation of decoder is fo 90percent of its max1imum value is defined as

a Demuitiplexer (b) Encoder (a) Rise time (b) De ay tne

(cConverter (d None ot these (C) Propagation time (d) Operating speed

a0Which statement is true tor multiplexer? Q95 The clock signals are used in sequential log
of input Crcuits to
a)Number lines equals to number oft
outputs ines (a) Tell the time of the day
Tell how much time has elapsed since the
n Number ot input ines
less than number ot
(b
system was turned on
Output lines

Number ot input lines greater than the number (OCarry serial data signals
(d) Snchronize events in vanous parts of systerm
of output ines
)Any number ot input and output ines 96 An n s t a g e n p p l e c o u n t e r c a n c o u n t u p to

01 inmuitipiexer, the number of input ines depend

(a) 2 (b) 2-1
(c) (d) 2
a) The number of output lines a97 A 2 MHz signal is applied to the input ot a J-k
fip-fiop which is operating in the toggle mode
(b The number of selector lines The trequency of the signal at the output will be
c) The number of gates
(a) 1 MH (b) 2 MHz
a) None of these
(c) 4 MHz (dS MH2
Q92 The output tor the iogic circut shown in the
Q98 Register isa
igure is
a) Set of capacitor used to regster input
instructions in a digital computer

D D (b) Set to paper tapes and cards put in a fie

(c) Temporary storage unit within the CPU having
dedicated or genera purpose use
() Part ot the auxiliary memory

D D Q 99 Which of the tollowing circuitis called latch

(a) AND circuit (b) NAND circuit
a) AB (b) 4 B (c)Fip-filog ()ROM circuit
c AB (d) A-B
Q 100 T fip-fiop is commoniy used as
(a) A digtal counter only
93 Match List- with List-Il and select the correct
(b) A deiay switch
the lists
Swer using the codes given below (c) A digital counter and trequency divider
List- List-
1. Combinational circut
(d) None ot these
A. Multipiexer
B. ALU Sequential circut
Q101 When a J-k thp-flop IS Constructed trom an SR
2
C. Register flip-fiop
 224
Multiple Choice Questions :CS
(a) S-JA) R- A (a)10
mADE EnSY
S R (C)0 0
(b)1 1
(C (d) 0, 1
stR QA S(R)
(d) S-
O 108 The number of
R A columns is a
state
sequential circuit witth m attatile fora
Q102 I1 in a
shift resistor QIs ted back to nput the S tip flops and
nd inpDut
resulting counter is (a)m+n
(a) wisted ring with N 1 scale (b) m +
2n
(c) 2m +n
(b) Ring counter with N 1 scale (d) 2m +2n
(c) Twisted ring with 2 N 1 scale Q.109 In a
positive edge trIggered JK
(d) Ring counter with 2 N 1 scale and low K
a flip flo alalow
produces
Q 103 The dynamic hazard (a) High state
problem occurs in
(b) Toggle state (b Low state
(a) Combinational circuit alone
(d) Nochange
(b) Sequential circuit
only Q.110 Flip-Flop is
(c) Both (a) and (b) used to store bit intormatior
(d) None of these (a)C
(b)
(C) Either 0 or 1
Q 104 A switch-tail ring counter is (d) None of
made by Q.111 Preset and clear these
Single D FF The resulting circuit using a
are
(a) SR flip-flop
is
flop because present in
clocked RS flip
(b) JK fip-flop
(c) D-flip-flop (a) When
(d)T-fip-flop power is switched off.
flop is retained the state of
Q105 A
puise train can be
flip-
delayed by a finite number
periods using of clock
(b) When power is switched on, the state
(a) A flop is uncertain. of flip-
serial in- serial- out
(b) A serial in- shift register (c) It provides initial
(C)
-

parallel out shift register (d) Both (b) and condition to set
flip-flop
A parallel -

in serial (c)
(d) A
out shift register
serial -

in
parallel Q.112 The
Q.106 For
-

out shift
register sequential circuit
contains
the initial state of 000, (a) Combinational
the function circuit and
by the
arrangement of the J-K flip-flop inperformed (b) Only memory elements
figure is the
combinational
(c) Gates and circuit with clock
given clock pulse
(d) Any of
these
Q.113 The
flip-flop can be
constructed using only
KAO (a) AND gates
Clock K A (b) OR gates
(a) Shift Register (c) Not gates
(C) Mod6 Counter (b) Mod-3 Counter
d) Mod2 Counter (d) Universal gates
Q.107 The Q.114
tollowing arrangement In
clocked RS
flops has the
initial state of
ot
master slave
tlip
flip-flop. the output
previous output until is reman as
(respectively) After three clock P. Q as 0. 1 (a) R=
0, S =1
state P Q cycles the output (b) CP = 0
(respectively) (c) R 1. S 0
= (d) R 1, S 1
P Q.115 The JK
=

(a)
fiip-flop is obtained by
2 AND gate to the adding
(b) 2 AND gate input of RS flip-flop
to the
input of
feedback of outputsclocked
D
flop with SR
1p
(c) of RS flip-flop.
Clock Applying only feedback to the
flip-flops inputs of RS
(d) Not possible
 n A D E E R S Y

W c h ofthe bilowing problem of RS

Digital Logic Basic Level
Q116 eliminated by JK fip flop?
flip flop is
( a )S 1 5. Logic
(b) CP= ()
(C) R
1, CP = 1
(d) R 0 Q 126 Whichh
CP =0 of the

Q117
A register is
famitly?
(a) Individual mernory unt (a) RTL
(b) Storage device (C) TTL
(c) CompoSed of fip fiop
Q127 The main a
(d) Used to store 1 bit value
TL are
Q 118 Theedata entered in serial form is called (a) Lower
(a) Serial data
(b) Sequential data margins
(c) Spatial code (b) Lower
(d) Temporal code
(C) Higher
The data entered in
0119 parallel forn Consur
called to registers
(d) Higher
(a) Spatial code (b) Tempporal code
(c) Parallel code Q 128 Standard T
(d) None of
these and a
a 120 Which one is not a type of shift a) Toterm
(a) Bidirectional register? (C) Bipolar
(b) Unidirectional
(c) Left shift
(d) Right shift Q129 Non-volat
a.121 Thenumberoof states in state (a CCDs
(a) Number of inputs diagram determines PRO
(b) Number of flip-flops Q.130 Whch of t
(c) Number of output as man n
(d) Number of combinations of
inputs a Magne
Q122 Atoggle operation cannot
be
single performed using a
Aag
(a) NOR gate
(b) AND gate Botn
(c) NAND gate Q131 EE
(d) XOR gate
Q.123 In aripple counter a
using edge-triggered bEasil
flops, the pulse input is JK fip

a) Clock input of all applied to the C) Non-E

(b) Clock input fip-flops (d) Eftec
(c) Jand K
of
oneflip-flops Q132 EPROM
(d) JandK
input of one
flip-flop
input of all fip-tlops (a) Bipol
Q.124 Statettransition (c) UJTs
table and
state transition diagram
form part of the Q.133 Which of
(a) Combinationaldesign steps in
circuits access t
(b) Amplifier circuits (a) Cach
(c) Delay circuits (b) Mag
(d) Sequential circuits (c) Magr
(d) RAM
.125 The time required for
its require
state is
a gate or invertertochange Q.134 In magne
(a) Rise timmedefined as in a con

c) Propagation time (b) Decay time

(dl Charaina time
(a) Sect-
 (a
(1)

40. (b)
32 ( ) 33 )34 (b)35 () 36 38 (C) 39 (b)
(tb) 37 (
42 () 43 44 ) 45 (a) 49. (a) 50. (c)
(b) 46 (a) 47 (a) 48
(
() 53 ()54 (d) 55 (d) 56 (d) 57 (a) 58 (d) 59. (C) 60 (b)
(0
52

6 2( ) b 3 ()64 70 (a)
(b) 655 (b) 66 68 (a) 69 (a)
(b) 67 (C)
72 73 (a) 74 (a) 78 () 79. (d) 80 (a)
75. (a) 76 () 77 (C)
b82.(b) 83 ()84 (b) 85. (d) 86 (a) 87 (c) 89 (b) 90 (C)
88 (b)

(b) 93 (b) 94. (a) 99 (b) 100. (C)

(b) 92 95. (d) 96 (b) 97 (a) 98 (C)

103. (C) 104.(c) 105. (a) 106. (C) 107.(a) 108. (C) 109. (d) 110 (b)
101
(d) 102.(c)
112. (b) 113. (d) 114. (b) 115. (b) 116. (a) 117.(C) 118. (d) 119. (a) 120 (b)
11 (b)

122. (b) 123. (b) 124. (d) 125. (c) 126. (a) 127. (a) 128. (a) 129. (C) 130 (d)
21 (b)

131 (a)
132. (b) 133. (a) 134. (b) 135. (c) 136. (a) 137. (C) 138. (d) 139. (D) 140 (d)

Explanation Digital Logic

1
4096 2' have one
1

(0) A+AB= 0 256 =

2 have one
16 = 24 have one1
(0) AB = AC
temains as same
in
numbDer
Hence, they only
(in) AB+AC+CD = CD
1s and when any other number is multiplied b
From () we have d

themselves, the number of 1s s only the count

A+ AB (A+ B) = 0
the number of 1's in other muitiplicant
e A must be 1 and Bmust be 0
3 011
From (11) we have
15 1111
AB ACB 10 1s
5 0101
C
3 011
e Cis also 0
Putting the values of A, B and Cin () Correct option is (c)

1.0+1.0+ 0.D = 0D 8 (a)

0+1+0 =1
1 1
For, the above equation to be true Dis indeperndent.

2 to 1 multiplexer is a universal cirCuit.

34096+15 256+5'16+3
As we can see that
228
Multiple Choice Questions:CS
10. t 24 (a)
(539) 1B)
(10 0XX)1 01) 109

scomplimment 1101 11 10
(01 )(12 )(12
0101
050 1250062, 6

Hence (c)Is corect 25. to)

option
11. (b) 122
0
61 1
(0.25)10 025 05 30
2
0 50 1.0 1111010

(025)0 (001),
Hence (b) is correct option
Number Is
positive, so no need
Complement take 2
13. (b)
he devIce that 26
works in
computer but not as part of it is conjunction
with a
9'scomplement of
called peripheral 33 is
(93) (9
device eg printer A 3) =
66
printer is not part of computer,
It only do
the as jobs
27. a
per instructed by the
Computer 10's complement of
Hence (b) is the correct 15
option 9s complement of 15 +1
20. t (9-1)(9 5)+1
84 +1 85
(123)= X3),
AS we can 28 a)
observe that
5x
12x5 3 x5 =Yx X+ 3XY
25+10+3 YX+ 3 2 33
2
35 YX
16 0
8
(35) 0
100001

Putting 5
We have = 7
Putting y 7
Hence (c) We haver =5 29.
IS Correct option d)
21 a) 1001 1000
(0 4375)o (98)0
Now convert
(98), into binary
()04375 () 08750
2 () 0 75
x2 (iv) 0.50
0 8750 98
2
7500 150 49
10
0 2 24

(0 4375) (00111 2 12 100010

Hence (a) is correct option

1
 229
a D E E R S 5

Digital Logic Basic Level

Circuit 1S
S0, the expressIon for the givern C
AB+ (A+ B)
qurvalent Gray code C) +
Y = A(B+ BC
AC+ AB AC +
Y = AB+
AC+ BC
Y = AB+
47. (a)

AB(BC+ AC) = Y
1101 Compliment of Y

AB (BC+ AC)
0011
Y =

1010 AC
=
(A+B)+ BC.
= (A+ B)+ (B+ C)-(A+ C)
(c
33. number is Hence. (a) is correct optiobn.
Addition ot
1 101 111

+1 100 010 49 (a)

A
= A1+B+ AC
=

1 101 0 001 A+ AB+ ABC

Hence. (a) is corect option.

The e x p r e s s i o n 50. (c)

10 1.0+ 1.0 In product of sum form

= 1.1 0 . 0
F BD+BD
(B+D)(B+ D)
1 10 = 11 [190 =
1
1.11.1 AB AB AB AB AB
CD
O1
CD
Hence, (b) is the correct option. 1
CD 1
CD 1
39 b)
law which CD
the distributive
A+ BC represents
as
can be expanded Hence (c) is the correct option.
A+ BC= (A+ B) (A + C)
51. (d)
5. (b) Let.
when A = B
AB = O Then O NOR 1 0
1 1 0
00 0 x = 1
e. Let.
when A = B= 1
A+B 0 Then 1 NOR 1 =O

1+1 = 1 = 0 Hence, (d) is the required option

e
A = 1, B = O0
when
A B 0
53. (b)
1 0 O0 AB+ AC + AC
AB
A B =0 when AB +C
0. B= 1 AB + B)+CA'+ A) =A
or A
=0
=

A 1, B is independent of
B
e =

Hence, boolean expression

option.
Hence (b) is the correct

58. (d)
a ed. 1 + A = 1 and 1+ A= 1
series they are And 2nd is alsotrue because
a r e in
en the switches
ed
are OR
in parallel
they
en
they a r e
 230
Multiple Choice Questions CS
DE ERS
s9. 76. c)
Both universal gates NAND and NOR don t follow
asso iative law
OR (A+B)
61.

B
OR
A B) ANDABAB = As B

c)
78. (c)
The quantity 837 1s first
A A B)+ B(A+ B con verted to
representation then it is
incremented by
BCL
(A4 AB)+ (AB+ BB bit 3 bit by
A+ AB+ AB+ B 837 1000 0011 0111
A+B(A+ A+ 1) A B Excess-3 1011
0110 1010
63. c 81. (b)
Bu We can
A 00
construct a m-bit parallel adder
01 () by.
11 10 m-full adders ODR
o10 () (m- 1) full adders
and one half
(ii) (2m adder OR
1) full adders and (n
-1) OR GATES
BC BC 82 (b)
B C BC

64 (b)
+
Don't care
condition can be either 0 or 1 as

D
the per
requirement If needed don't care
else not included is included
fY
67. (c) y + +y) =

y+ y = iy
Therefore the above circuit
B
AB AB NOR gate performed exclusive
A+B
70. la) 83. (c)
f =

ABCD+ACD
=AD BC+ C+ 1)+
AD

75. (a)
f = AD A1 11 DC
A B)C= (A B) C

NAND X

NAND
D D
D CD-C D
(A B -

NAND F
NAND 2,
(A B C)C-D
NAND ABC CD
f=y+z = C[D A4B1
 231
A D E E R S Y

Digital Logic Basic Level

Next state

d Present state
y = (A+ B+C+ D) (A+ B)

=(A+B C+ D)-(A B
(ABC D) +(A B)
ABCD+ AB
o

. (c 6 different states
In d e c o d e r there are'n input lines and 2" output

ines
at most
110. (b) store one bit
intormation
but

used to
(b) Flip-tlop Is O or 1
either
92. intormation can
be
that
Y (A+ A) AB+AB
(AA AB) + A+B
114. (b)
Truth table of
clocked RS tlip-flopis
=0+A+ B A+B
CP S

96. (b) counter c a n count up

to the
An n stage ripple Q
by the n-bits.
value represented 1
binary
= 2n 1 0 Q
Reset (i e 0)
1
Set (1.3 1)
0
98. (c of flip flop,
with
of group invalid
Register is
consists

of
i n f o r m a t i o n . Register 1
each flip-flop
having 1 bit general
Used for
storage.
temporary
acts as a
115. (b
purpose.
D R D

106
maximum

counter,
so
Johnson

figure is a where n is the CP

GIven
will be 2n,
possible
states

number of flip-flops
in output

D
Q
Q K
K
K

Clock

state = 000
initial
 CHAPTER
Digital Logic
12 7 A I t e r ieh l i i t maitiaaa a
1. Number Systemn
Q1 (22), (101), (0)-( ) we a will
The value of N ()eatilt it eiOverflow e t r o r
(a)t (b) 4 )Retit lt aOverflowerro
()1 ()8

Q2 (8), base umber system is e Jual to (3/)

m base y number system the poNitble values
Q8 Onl ie folowing loaling Oint torhat
ofandy are 2 bits
(a) 53 ()8
(c)3 4 AM
(d) 13
Q3 Suppose the largest bit S Sin Dil
binary number reqines
digits in decimal representatio WIuhof the E pOnent
following relation between and N M Mlisna
approximately cottect Ihe vale ol loaling pont number in thiS tsystem
(a) d2 (b) 2
()dn log (d) d n log hen wlhal is the comesponding decimal value it
Q 4 he lloaling ponl stored is 3F 800000
Let A- 1111
1010 and O000 1010Do
lwo (a) 0
8 bit2's Complernent numbers hen product (b)
in (C)
's complement i (d)2
(a) 11000100 (b) 1001 1100 Q9 Asingle preCision floating point number contains
(C) 10100101 (d) 11o10101
heseguence ol Dits 100011111 O0000000001
Q5 Which of the O00O00OOOO00, Intormation stored
following 4 bit numberS equals ils
is in the
1sComplement? lollowing left to right order, sign bit,
(a) 1010
exponent
(bias 127) and mantussa
(b) 1000 Which of the following
(c) No such number exists
representation in decinal
ISequivalent?
(d) None of these
(a) 2 (12 )
(b)1)2(12 ")
Q6 If the
decimal umber (c)1)2 (1 2 0) (d) (1)2 * (12)
1s 3248 10' then its
32 bit
equivalent tloatng number Q.10 Sign extension is a
IS step n
(a)
0 100X01 101
(a) Floating point multiplication
11111011100000000XOOO00 (b) Signed 16 bit integer addition
(b)1 10001101 (C) Arithmetic left shift
111110111OOO 000 (d) Converting a signed integer from one SIZe t
(c)o11010101 11111011100XXXO0000000 another

(d) 1 11010101 11 1 1011

Q.11 The decimal number 0
1000000000000000 hexadeciHmal representatiorn
239x ?'has the followin
(without normalizatio
and rounding off
E ERSY

Digital Logik 233

a 0 0 2 4
( 4 Advance Level
4 D0 0 (d) 4 3 1 8 Let fA B) - A 6 then smpitied from of the

aes ofr
and y i
(67 (2yx5), 71yx) function f ' t y Z) w)is
(a fry 2) w (b) y 2 tw
c) tr yz) w (d) None of these
(33
(d) 4 5 O 19 der the irCut shown below Each of the

C through C must be tied to a

al number
Adecimal nur has 25 O r O puts
digits The rurmber of Constant either 0 or 1
S
needed for sequvalert binary rerpresentatio
aoproximately
(b) 60 D
(d) &

The greatest negative number which car be

D D
stored in computer that has 8 bit work
and uses 2s compleme arithmetic is iength D
a-256

- 128
(b) 255
(d-127
D OR

What are the values of C through C, that would

in the given network of AND cause F to be the exclusive OR of A and B?
(a)(1.0.0 1) (b) (0 1 1. 1)

DDD,.D (c) (0 1 1 0) (d) (1 1 1. 1)

Q.20 Write the minimized expression of the function

F wil be written as of three variables that is 1 if the third variable is
eaual to the OR of the first two variable. 0

otherwise

C)+X (a) (r y) 2 (b) Iy+ (x+y)z

(C)ry) z (d) (ry) 2
Q.21 Which of the following functions implements the

2. Boolean Algebra and Logic Gates Karnaugh map shown belowN?

CD
00 01 11 10
a16 Thefunction AB
1
00 0 0
f= (ABC+ABC ABC ABC)e A
01x
can be written as: 11 0
a) BeC (b)A B A 10 0 1 1 0

)A (d) None of these

(a) AB+ CD
17 The Karnaugh map for the Boolean function F ot (b) D(C+ A)
4BOolean variables is given below where A.B. (c) AD+ AB
of A
Care don't care conditions What values (d) (C+DNC+ DXA+ B)
,will result in the minimal expression?
Q.22 The Boolean expression for the shaded area ir
CD
AB 00 01 11 10 the given Venn diagram is
A 0
00 0 0

01 0 1 0
B
11 1 BC0
10 0 0 1 0
0 C
a) A B= C= 1 (b) B =C 1. A =
=

0
A = C= 1: B =0 (d) A B 1 C=
=
 characteriistic
char
tabi
M u l t i p l e C h o i c e Questiois
whose

tip-flop, is
a28
Arn *Y
below
is to
b e impiemented
sing a JK
given
This
can
be done making
234 fup-flop

n1
() (4 A)

(c4 AE

" 1
ROt
is a
si
e x p r e s s o n

he
Boolean (b) J= X, K = Y
version of expresson

4B+BCOE +
ABLE J= X,
K =Y
(a) (d) J= Y, K = X
BCOE,
A
Y

the
following
choce
is Corfec
(c) J= Y, K =X
whHhof

en
exist
conditons don t tne output is complemer
care gate,
t what logic
0.29 For
exist
don T
cornditions
2Don
t care 29) is the set
ol
the input?
18 20 23, 27, (b) AND
D16, (a) NOT
care conditons
don t
care (d) XORR
the set of
22 27. 29) Is (c) OR
D 1 6 20
conditions functio as a NOT gate if
NAND can
3 only
(b) 2 and Q.30 The together
(a) 1 only connected
(d) Data insufficient are
(a) Inputs
(c) 2 and 4 only are left open
shown above Is (b) Inputs
for K-Map is set to 0
he logical expression
Q24
(c) One input
is set to 1
CD (d) One input
following sequence of instructions
Q.31 Consider the
a =a b
b = aeb

(b) (A+CWB D) a = be a
(a) (4 CN6. D)
This sequence
(c)(4 CKB D) (d) (A+C\B D)
(a) Retains the values of a and b
in
.25 The Boolean expression for the shaded area (b) Swap a and b
the Venn diagram iS the values of and b
c) Complements a

(d) Negatees values of a and b and then swaps

them

a.32 Consider a function that is defined by the following

(a)i+y+(x+y+Z) (b) (x+ yXXy2) truth table:
(C) T++ (1+ y+ Z) (d) None of these
B f(A, B, C)
Q.26 Consider four variable Boolean function, which
a
0 1
contains half the number of
mninterms with odd 1
number of 1's Then the Boolean can
be realized
with variables 4 B C
Das 0
(a) ABeCeD 1
(b) ABC
(c) BC
(d) (A®B)+ (Co D) 1
1
Q.27 Consider
1
Y= Ae Ae A9 AeAe A® Ae 1
the Yis AeA 1
(a) 1 OR
equivalent to
E
Which of the
(c) 1 NORB
(b) A EXOR O following statements about tie

minimal
(d) A AND A
of-sums
sum-of-products and minimal produ
implementations is correct
MADE E R S Y
Digital Logic Advance Level 235
Note That represents dont care term
(a) They are logicaly equivalent because the (a) S1 (h $1
don't cares are used in the same (d) S1S2
way
(D)They are logicaily not equivalent because the 37 he Venn dagram representng the Hew ilee a
don t cares are used difterent ways
in
oressn1 A(A ) 1s
(c) They are logically not equvalent by detiniton
(d) They are logically equivalent by defintion (a) () A
33 The output of a 3 input logic circut f Is 1
t a byC2< (d)
dand 0 otherwise (a. h c d
are constant) For what values of a. b c, ddoes
Q 38 The booleanexpiesson
this represent an implementation of the AND
gate
ABEBCDE BCDTARTYE BD
can simplified to BEBE the don't care
(a) a = b = c= 1
conditions are
(a) ABCDE AB CDE
(b) a = b = C= - 1 d= (b) ABCD ABCDE ABCD'E
(c) AB CDEABCDE ABCD'E
(c) a-brc=1d- (d) None of these
(d) a = b = C= - 1. d= Q 39 1he boolean expression
(4 C)(AB AC)(A C +B')can bes1mpitied
to
Q.34 For the switch circuit taking opern as 0 and
closed
as the expression tor the circuit (a) AB (b) AB A'C
is (c) A'B+ BC (d) AB BC
Q.40 Which term is redundant in the expression
AB+ AC+ BC
(a) AB (b) AC
YIS given by
(c) BC (d) None of these
(a) A (B C)D (b) A+ BC+ D
(C) A(BC D) (d) None of these Q.41 Find the number of minterms the
in
canonica
Sum of product form of A BC
35 The minimum number of 2-input NAND gates (a) 3 (b)5
reguired to implement the function F =(v+y) (c)7 (d) 8
(Z w) is
a))3 (b) 4 Q.42 BBAB®B n=? Where
(c)5 nis odd number
(d) (a) 0 (b)1
.36 A two-way switch has three terminals a, b and c (c) B (d) B
In ON position
(logic value 1), ais connected to
b and in OFF position, a is connected to c
Iwo Q.43 A A A A n-Where n Is even number
of these
two-way switches S1 and S2 are (a) 0 (b) 1
Connected to a bulb as shown below (c) A (d) A
C
O a 3. Combinational Circuit
Q.44 The tollowirng cncuit
Switch S 1 Switch S2
D D
Which of the foilowing expressions, if true, will D
always result in the lighting of the bulb?
 Multipte Choice
Questions : cS maO
236 (a) 1 y (t) rdy
h er e p r e s e n t e d a s
(c)2ty (d) 1arned omty
2 5 0 The i u t Eeiryu tepreserts furctirr A
)a
(iere 1 XF)
beow corverts
Q 45 he Carcut sthow
D
D-6 MUX
DD
(a Binary to gray (b Binary to Excess 3
AB
Excess 3 to gray (d Gray to binary
c (a) 2 (3 89 10)
Q 46 The output of the circuit shown following
in figure (D) Z (3 8 10 14)
s equa to
(c) I (0 1 2 4 5 67 11 12 13 15
(d) II (0
1
2 45 67 10 12 13 15)
D DD D Q.51 If haif adders and full adders are impie
using gates. then for the addition of two 17 t
nented
nurmbers (using minirnurn gates) the nurmber
D haif adders and tull adders required will be
(a (b) 1
(a) 0 17 (b) 16. 1
(c) AB- AB (d) 4B- AB (c) 1 16 (d) 8 8
Q 47 The crout grvenn igure s to be used to mplement O.52 To realize folowing function f
A
hetuncton Z= fiA B -
B What s the values
should De selected for / and J
D
4:1
MUX 4o
D D D
3
D
a D)= 1J=B ABCD
( ) I = B J=0 How many minimum number of 2 input NAN
C =B
gates are required
4 8 Mirmum numoer of NAN gates reaured to (a) 3 (D) 6
moiemert sum n nat-adder circuit s (c) 4 (d) 10
a (3
iC)4 .53 Minimum number of 2 1 multiplexers required
to realze the following function. f = ABC ABC
Q49 The toliowng an impiemented of
Assume thiat inputs are available only in true form
and Boolean constants 1 and O are availabie
D (a) 1
(C) 3
(b) 2
(d) 7
Q54 The number of full and haif-adder required to add
16-bit numbers is
(a) 8 haf-adders. 8 ful-adders
Sum of fu adder
(D) 1 haf-adder 15 full-addors
2 Carry of ralf acoer
(c) 16 haif-adders 0 full-adders
3 Derence of tu suotracter
d ) 4 half-adders 12 full-adders
 237
n t E R S Y
Digital Logic | Advance Level
many 3 to 8 lime decoderS with circuIt
an enable Q. 59 Consider the following
a r e needed fo construct a 6 to 64 line
i der wifhout tISing any other logic gates? D
(b)8
(d) 10
D
The following Ciret inplerments a two- input AND
be
narked box shouid
1 tautology the
gateusing fwo muitiplexers lo make it a
(b) AND gate
(a) OR gate
(d) EX-OR gate
ab (c) NAND gate
Q.60 Convert
2)
'yz 'Yz + x(y+
into a product of Sums
What are the values ot , . X
xz
(a)X, =b X, =0. X, = a (a) yz+ Y2+ xy +
y) (x 2)
x
+
(b) (r+y+ Z) (a' +Y +2)
+
( ) , =b. X, =1, X, =b
(c)X, = a X, = b (c) (x+ Z) (x+ y + 2)
(d) (y + 2) (r + y + Z)
()A = d X. =0. X, = b
is a
67 Consider excesS 3 code that is used to represent Q.61 The circuit given below
ntegers O through9 as shown below A
B
HAA oupu
Number Code (ABCD) HA -oE
Co
1100 (b) Full subtracter
(a) Full adder
0010 None of these
(c) Parity checker (d)
1010
of
0110
Q.62 The m-bit parallel adder consists
(a) m full adder
1110
(b) Sum of all previous bits
0001
(c) carry from (K - 1 yh bit
1001 (d) Sum of previous bit
0101
Q.63 The full adder adds the K'h bits of two numbers
B 1101
to the
9
0011
(a) Difference of the previous bits
IS the correct
Which of the following expressions (b) Sum of all previous bits
one for an invalid code? (c) Carry from (K - 1 h bit
a) bc' d + cd (d) Sum of previous bit
(b) bc' d + acd
(c) b'c' d+ bcd+ acd+ b Cd Q.64 For the logic circuit shown in the figure below the
Output y Is equal to
(d) bc d+ bC d+ aC.d
.8 What logic function is performed by the Circuit
D
shown below A D
B
A
K
B D y
Co
DD D
(1) ABCc (2) A+B+C
D (b) Ripple counter
(3) AB+ BC+ A+C (4) AB+BC
a) Ring counter (d) Half adder
(c) Fuli adder
 Multlple h o k e q u e l
4. Sequential circu
arit 12
ustin71
238 1 ancP
only
Answor
(b) inkad
thene
( ) 1oriy the
1 (d) All
arnt
(o) 1
an12
verth
a i l a ry
helow
cire i t given
The ogh
Q 65
code y, , ,
ater
1 tue
Q 7 1 h e e iital
stale ,
(a) Fxces8 3ronde
(h) irayr
(f) Ham1ifgcode
(c) BCD code (ia)
is
fhe figure
beow (
in
showr
Q 66 The circuit
(1irerit statg
after
t ityx
Wat will t th
D Q72
uisen furlter fronro
the r n i t 9 r of puiser, tar e
abovo jestiori
D fron the
(a) (911
(h 100
(d) 110
(C) 101
as shoW tigure if in
The divide by N counter
D Q73
nitially ,-0,,-1, , -0
What is the valie
(b) A subtracter
(a) An adder of N?
Comparator
(c) Parity generator (d)
Q67 All digital circuits can
be realized using only
(a) EX-OR gates
(b) Multipiexers
(c) Half adders
Clock
(d) OR gates
(a))5 (b) 6
68 The simultaneous equations on the Boolean
(c) 3 (d) 4
variables x y. zand w
y+= 1
Q.74 Cornsider the circuit givern below with initial state
xy = 0
xZ + W = 1
1. , , -0 The state ofthe circut is
given by the value 4Q, + 4Q, + Q
xy+ =0
have the following
solutior for y 2 and w
respectively
a) 100 (b) 1101
0
D
(c) 1011 (d) 1000
K
69 How many NAND and LSB
NOR gates MSB
to
construct a full adder?
are
required Clock
(a) 9,9
(b) 8,6 Which
(C) 6 one of the following is the correct state
(d) 5.5
Q.70 How Sequence of the circuit?
many to 1 2 (a) 1,3, 4
multiplexers are 6, 7,5, 2
Constructa64 to 1 multiplexer? required to
(b) 12,5, 3. 7, 6, 4
(a) 63
(b) 62 (C)
(c) 65 12. 7 3,5, 6, 4
(d) 64 (d) 1 6. 5, 7, 2,
3, 4
 239
Advance Level
Digital Logic | below
A O EE R S S y giver1
Consider
the figure
Q.79
finite state
foliowing
diagram represents a
number
takes as Input a binary
The +5V
machine ine which
significant bit CLK
east
the CLK
trom FFO
)/1
input CLK
jCLK
O/0 Pulses K CLR
K CLR ciock
1/1 1/0 How many
cleared
are before
flip-flops
Iitiallyall
systerm
to the
applied level?
TRUE have to be HIGH
the foliowing is pulse a
one of b e c o m e s
Which of the input from FF 3
1s Complement the output
(b) 4
lt computes
a number
(a) 2 (d) B
2s complement of the input (c) 6
computes a3-bit
b)It belowis
showrn
number circuit
Q.80 The logic
increments
the input number.
c) It
decrements
the input number
d ) it FFC
FFB
circuit
FFA
76
Consider thefollowing CLK
CLK
CLK
D Clock
input
D CLK

DOY
(a) Shift register
binary
up-counter
Asychronous
(b) down-counter
Asynchronous
birnary
(C) counter
Synchronous binary up
(d)
are positive edge triggered DFFs shown below
are
The flip-flops
as a two bit string Q, of the J-K flip-flop,
Q.81 The inputs
Each state is designated K= O0
state be 00.
The state transition PRESET =
CLEAR =1; J= device will
Let the initial
clock pulse is applied the
seauence iS
lfa single
PRESET
a 00 11
(b) 0001 CLK
C) 0 0 1 0 0 1 > 1 1
CLEAR
10 (b) Set
d) 0011 01
(a) Toggle states
(c) Reset (d) Not change
SR fip-flop and
difference between control Circuit
which
7 The functional Q.82 Consider the following
JK fip-flop is that JK flip-flop 3-bit register and a
black box with
contains a
flip-flop
(a) Is faster than SR some combinational logic
(b) Has feed back path
a
1
C) Accepts both inputs
external ciocK
a) Does not require
CLOCKD1 D2 D3 Black box of
combinational logicC
flip-flops required
in a
moduloN
CLOCK 01 Q2 Q3
. h e number of
COunter is
a) log,(N) + 1
000
The initial state of the circuit is Q1Q203 =
(b) iog,( The circuit generates the control sequence
(010)(110) > (001)>(001)> (001)
(o)og(
(d) log,(N 1)
 Muttipe Chotee questions: CSS DE ERS4
R a ip-fiop we have d =a n
and K
Assurarg the i p ioD was initially claa
heyr
cleared ard
ved for 6 pulses the sequernce
t t will t e
enice at the
,
toy f - 1
(a) 1 5 b (D) 011001
(c.) 01010 (d) 010101
9 0 The tiorik diagrarn shOwn
Delow represents
(a) The rurriterae rvisitie try
ty9
(a) Moduo-3 ripple counter
'a4, s isitie ty 3 (b) Moduo-5 ripple counter
a chr with firre terieT sA wit n stage (c) Moduio-7 rippie counter
sPuft r6str (d) Moduo-7 synchronous counter
te t f finai stage wil be
O.91 The tircuit shown in the
figure given below
t rilT s
1211) se Output
(a) Is an
oscillating circuit and its output is a
square wave
(D) ls one whose
output
state
remains stable in
C)Is one having output remains stable 0 state
(d) Having a single pulse of 3 times
propagation
a 1, I delay
A92 Arnod-2 couriter followed
by a mod-5 counter s
(a) Sarne as a rmod-5 counter followed a mod
by
2counter
(b) A decade cournter
(C) A mod-7 counter
(d) None of these
Q.93 A 4 Dit
synchronous counter uses flip-fiops W
propagation delay tirne of 25 ns each
mainurm possible tirne required for change
't11 state will be
r 1111 (a) 25 1s
(b) 50 ns
()75 rs (d) 100 ns
MADE ERSY
Digital Logic Advance Level 241
a 94 I f the
state achine described in
below, shouldhave
h
the figure
a stable state 5. Logic Family and Memories
the restriction
on the inputs is given by
Q.97 The refreshing rate of dynamc RAMG
( a 1out 1 a 0/out 2
approximately once in
(a) Two rmicro seconds
(b) Two milli seconds
(b 0Vout 1 (b 1 out 2
(c) Fifty mili seconds
a. b 1 (b) a +b= 1
(a)
=
(d) Two seconds
(c) a+b=0 (d) ab= 1 stored
.98 The number of Dits that are typically
each track of a magnetic dis s usualy
Q.95 Consider the following circuit with initial state
The (a) The sarme
O= Q, 0. =
DFlip-Flops are positive edge (b) Different
triggered and have set up times 20 nanosecond
DE Siored
(C) Depend on the program to
and hald times 0.
(d) Fifty
sgven Dy
D 1DD Q.99 The figure of mert of a logc 'amily
(a) Gain bandwidth product
Clock Clock (Power disspaton
C (b) (Propagation delay tme
*
de ay tme
(C) (Fan-out) (Propagation
Consider the following timing diagrams of Xand
(d) (Noise margin)
(Power diss Dation
C, the clock period of C2 40 nanosecond Which
16 K bytes s reaured
Q.100 A memory system of
size
one is the correct plot of Y?
chips which nave
memory
tobe designed using 4 data the
(a) 12 lines and
address ines eacn
such chips reauired to oesgr the
number of
(b) L memory system sS
a) 2 )
16
(c) (C)8
over bD0 ar
MOS devices
Q.101 The advantage of
(d) devices is that
and a'so coS:
described by the bit oensities
state machine (a) It allows higher
Q.96 The Finite state.
A as starting effective
following diagram with
state
stands tabricate
as rly and r b) It is easy to
arrows are labelled ODerationai SDeed
where and
stands for 2-bit output (c) Its higher-impedance
for 1-bit input and y these
(d) All oft
1/10
O/00 0/01
shown in tigure s
c Q.102 The gate
(A101 B110 0/01

oVcC
and the
of the present
sum
the
(a) Outputs input
previous
bits of the sequence
whenever
the input
01
(b) Outputs
Contains 11 sequence
whenever
the input
00 (b) NAND gate
(C) Output (a) AND gate
contains 10
(c) NOT gate
(a)OR gate
(d) None of these
Explanatien Digital Lep
i e MS8 Eer
00m00
.
There s u m b e r 2s comciermert
tor positve
4 8-
Birary representator
e Now tae 2s compe
e ae catec atcYd
Sirce n 1s compwe euery t s cumcw
so rumoer et a c e c o m
same whue h compee
Cecamua e34
So sgn tut s a 3 be 0 unce namber s p