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TLE 6361 G
Multi-Voltage Processor Power Supply

Data Sheet

1 Overview

1.1 Features
• High efficiency regulator system
• Wide input voltage range, up to 60V
• Stand-by mode with low current consumption
• Suitable for standard 12V, 24V and 42V PowerNets
• Step down converter as pre-regulator: P-DSO-36-12
5.5V / 1.5A
• Step down slope control for lowest EME
• Switching loss minimization
• Three high current linear post-regulators with
selectable output voltages:
5V / 800mA
3.3V or 2.6V / 500mA
5V or 3.3V / 350mA
• Six independent voltage trackers (followers):
5V / 17mA each
• Stand-by regulator with 1mA current capability
• Three independent undervoltage detection circuits
(e.g. reset, early warning) for each linear post-regulator
• Power on reset functionality
• Window watchdog triggered by SPI
• Tracker control and diagnosis by SPI
• All outputs protected against short-circuit
• Power-DSO-36 package

Type Ordering Code Package

TLE 6361 G Q 67007-A9466 P-DSO-36-12
SMD = Surface Mounted Device

Data Sheet, Rev. 1.31 1 2004-10-12

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TLE 6361 G

1.2 Short functional description

The TLE 6361 G is a multi voltage power supply system especially designed for
automotive applications using a standard 12V or 24V battery as well as the new 42V
powernet. The device is intended to supply 32 bit micro-controller systems which require
different supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for external
sensors are also provided.

The TLE 6361 G cascades a Buck converter block with a linear regulator and tracker
block on a single chip to achieve lowest power dissipation thus being able to power the
application even at very high ambient temperatures.
The step-down converter delivers a pre-regulated voltage of 5.5V with a minimum
current capability of 1.5A.
Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V,
or 2.6V of output voltages depending on the configuration of the device with current
capabilities of 800mA, 500mA and 350mA.
In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their
outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to
drive a current of 17mA each. The trackers can be turned on and off individually by a 16
bit serial peripheral interface (SPI). Through this interface also the status information of
each tracker (i.e. short circuit) can be read out.

To monitor the output voltage levels of each of the linear regulators three independent
undervoltage detection circuits are available which can be used to implement the reset
or an early warning function. The supervision of the µC is managed by the SPI-triggered
window watchdog.

For energy saving reasons while the motor is turned off, the TLE 6361 G offers a stand-
by mode, where the quiescent current does not exceed 30µA typically. In this stand-by
mode just the stand-by regulator remains active.

The TLE 6361 G is based on Infineon Power technology SPT  which allows bipolar ,
CMOS and Power DMOS circuitry to be integrated on the same monolithic circuitry.

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1.3 Pin configuration

P-DSO-36-12

GND 1 36 GND

CLK 2 35 SLEW

CS 3 34 WAKE

DI 4 33 BOOST

DO 5 32 IN

ERR 6 31 SW

Q_STB 7 30 IN

Q_T1 8 29 SW

Q_T2 9 28 Bootstrap

Q_T3 10 27 Q_LDO1

Q_T4 11 26 FB/L_IN

Q_T5 12 25 FB/L_IN

Q_T6 13 24 Q_LDO2

Q_LDO3 14 23 SEL

R3 15 22 CCP

R2 16 21 C+

R1 17 20 C-

GND 18 19 GND

Figure 1 Pin Configuration (Top View),

bottom heatslug and GND corner pins are connected

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TLE 6361 G

1.4 Pin definitions and functions

Pin No. Symbol Function
1,18,19, GND Ground; to reduce thermal resistance place cooling areas on
36 PCB close to this pins. Those pins are connected internally to the
heatslug at the bottom.
2 CLK SPI Interface Clock input; clocks the shiftregister; CLK has an
internal active pull down and requires CMOS logic level
inputs;see also chapter SPI
3 CS SPI Interface chip select input; CS is an active low input; serial
communication is enabled by pulling the CS terminal low; CS
input should only be switched when CLK is low; CS has an
internal active pull up and requires CMOS logic level inputs ;see
also chapter SPI

4 DI SPI Interface Date input; receives serial data from the control
device; serial data transmitted to DI is a 16 bit control word with
the Least Significant Bit (LSB) being transferred first; the input
has an active pull down and requires CMOS logic level inputs; DI
will accept data on the falling edge of CLK-signal; see also
chapter SPI
5 DO SPI Interface Data output; this tristate output transfers
diagnosis data to the controlling device; the output will remain 3-
stated unless the device is selected by a low on Chip-Select CS;
see also the chapter SPI
6 ERR Error output; push-pull output. Monitors failures in parallel to the
SPI diagnosis word, reset via SPI. ERR is a latched output.
7 Q_STB Standby Regulator Output; the output is active even when the
buck regulator and all other circuitry is in off mode
8 Q_T1 Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
9 Q_T2 Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
10 Q_T3 Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.

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1.4 Pin definitions and functions (cont’d)

Pin No. Symbol Function
11 Q_T4 Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
12 Q_T5 Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
13 Q_T6 Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a
1µF ceramic capacitor for stability. It is switched on and off by
SPI command. Keep open, if not needed.
14 Q_LDO3 Voltage Regulator Output 3; 5V or 3.3V output; ouput voltage
is selected by pin SEL (see also 3.4.2); For stability a ceramic
capacitor of 470nF to GND is sufficient.
15 R3 Reset output 3, undervoltage detection for output Q_LDO3;
open collector output; an external pullup resistor of 10kΩ is
required
16 R2 Reset output 2, undervoltage detection for output Q_LDO2;
open collector output; an external pullup resistor of 10kΩ is
required
17 R1 Reset output 1, undervoltage detection for output Q_LDO1 and
watchdog failure reset; open collector output ; an external pullup
resistor of 10kΩ is required
20 C- Charge pump capacitor connection; Add the fly-capacitor of
100nF between C+ and C-
21 C+ Charge pump capacitor connection; Add the fly-capacitor of
100nF between C+ and C-
22 CCP Charge Pump Storage Capacitor Output; Add the storage
capacitor of 220nF between pin CCP and GND.
23 SEL Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3
(see also 2.2.2)
24 Q_LDO2 Voltage Regulator Output 2; 3.3V or 2.6V output; output
voltage is selected by pin SEL (see also 3.4.2); For stability a
ceramic capacitor of 470nF to GND is sufficient.
25, 26 FB/L_IN Feedback and Linear Regulator Input; input connection for
the Buck converter output

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1.4 Pin definitions and functions (cont’d)

Pin No. Symbol Function
27 Q_LDO1 Voltage Regulator Output 1; 5V output; acts as the reference
for the voltage trackers.The SPI and window watchdog logic is
supplied from this voltage. For stability a ceramic capacitor of
470nF to GND is sufficient.
28 Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW
and pin Bootstrap, the capcitance value should be not lower
than 2% of the Buck converter output capacitance
29, 31 SW Switch Output; connect both pins externally through short lines
directly to the cathode of the catch diode and the Buck circuit
inductance.
30, 32 IN Supply Voltage Input; connect both pins externally through
short lines to the input filter/the input capacitors.
33 BOOST Boost Input; for switching loss minimization connect a diode
(cathode directly to boost pin) in series with a 100nF ceramic
capacitor to the IN pin and from the anode of the diode to the
buck converter output a 22Ω resistor. Recommended for 42V
applications, in 12/24V applications connect boost directly to IN
34 WAKE Wake Up Input; a positive voltage applied to this pin turns on
the device
35 SLEW Slew control Input; a resistor to GND defines the current slope
in the buck switch for reduced EME

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TLE 6361 G

1.5 Basic block diagram

TLE 6361
Standby Q_STB
Regulator
2.5V

Boost

SW
2*
IN
2* BUCK
REGULATOR

Slew Bootstrap
Driver

Internal
Error- Reference
OSZ PWM Amplifier
feedback

FB/L_IN
2*

C+

Charge C-
Pump

Protection CCP

Wake Power
Down
Logic

SEL

R1
Linear Q_LDO1
Reg. 1

R2 Reset µ-controller /
Q_LDO2
Logic Linear memory
Reg. 2
supply
R3 Q_LDO3
Linear
Reg. 3

ref
Tracker Q_T1
Window 5V
Watchdog
ref
Tracker Q_T2
5V

CLK ref
Tracker Q_T3
Sensor
5V
supplies
CS ref
(off board
Q_T4
Tracker supplies)
SPI 5V
16 bit
DI ref
Q_T5
Tracker
5V

DO ref
Q_T6
Tracker
5V

ERR
GND

4*

Figure 2 Block Diagram

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TLE 6361 G

2 Detailed circuit description

In the following major buck regulator blocks, the linear voltage regulators and trackers,
the undervoltage reset function, the watchdog and the SPI are described in more detail.
For applications information e.g. choice of external components, please refer to
section .

2.1 Buck Regulator

The diagram below shows the internal implemented circuit of the Buck converter, i. e. the
internal DMOS devices, the regulation loop and the other major blocks.

IN
5V Int. voltage Int. charge 14V
regulator pump
150µA

to
8 to 10V current sense
amplifier

FB/L_IN
C+ CCP
Gate driver
Main switch ON/OFF

Main
DMOS IN
under-
voltage
lockout

C-
BOOT- SW
STRAP

Slope switch
charge signal
BOOST
switching frequency 330kHz
Divider Slope
DMOS
Slope switch
Oscillator Slope discharge signal
1.4MHz compensation
Gate off signal
from overtemp or
sleep command
Trigger for SW
Lowpass
gate on
Voltage
feedback
Zero cross
amplifier PWM logic Slope logic
Current detection
comparator
Trigger for
Vref=6V
gate off

Lowpass

from Current Delay unit

sense +
current sensing amplifier

Slope
control

SLEW
external components pins

Figure 3 Detailed Buck regulator diagram

The 1.5A Buck regulator consists of two internal DMOS power stages including a current
mode regulation scheme to avoid external compensation components plus additional
blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how

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the gate driver supply is managed by the combination of internal charge pump, external
charge pump and bootstrap capacitor.

2.1.1 Current mode control scheme

The regulation loop is located at the left lower corner in the schematic, there you find the
voltage feedback amplifier which gives the actual information of the actual output voltage
level and the current sense amplifier for the load current information to form finally the
regulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% the
slope compensation block is necessary.
The control signal formed out of those three blocks is finally the input of the PWM
regulator for the DMOS gate turn off command, which means this signal determines the
duty cycle. The gate turn on signal is set by the oscillator periodically every 3µs which
leads to a Buck converter switching frequency around 330kHz.
With decreasing input voltage the device changes to the so called pulse skipping mode
which means basically that some of the oscillator gate turn off signals are ignored. When
the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and
its gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pin
the device is turned off.During normal switching operation the gate driver is supplied by
the bootstrap capacitor.

2.1.2 Start-up procedure

To guarantee a device startup even under full load condition at the linear regulator
outputs a special start up procedure is implemented. At first the bootstrap capacitor is
charged by the internal charge pump. Afterwards the outpuput capacitor is charged
where the driver supply in that case is maintained only by the bootstrap capacitor. Once
the output capacitor of the buck converter is charged the external charge pump is
activated being able to supply the linear regulators and finally the linear regulators are
released to supply the loads.

2.1.3 Reduction of electromagnetic emission

In figure 3 it is recognized that two internal DMOS switches are used, a main switch and
an auxiliary switch. The second implemented switch is used to adjust the current slope
of the switching current. The slope adjustment is done by a controlled charge and
discharge of the gate of this DMOS. By choosing the external slew resistor appropriate
the current transition time can be adjusted between 20ns and 100ns.

2.1.4 Reducing the switching losses

The second purpose of the slope DMOS is to minimise the switching losses. Once being
in freewheeling mode of the buck regulator the output voltage level is sufficient to force
the load current to flow, the input voltage level is not needed in the first moment. By a
feedback network consisting of a resistor and a diode to the boost pin (connection see
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section ) the output voltage level is present at the drain of the switch. As soon as the
voltage at the SW pin passes zero volts the handover to the main switch occurs and the
traditional switching behaviour of the Buck switch can be observed.

2.2 Linear Voltage Regulators

The Linear regulators offer voltage rails of 5V, 3.3V and 2.6V which can be determined
by a hardware connection (see table at 2.2.2) for proper power up procedure. Being
supplied by the output of the Buck pre-regulator the power loss within the three linear
regulators is minimized.
All voltage regulators are short circuit protected which means that each regulator
provides a maximum current according to its current limit when shorted. Together with
the external charge pump the NPN pass elements of the regulators allow low dropout
voltage operation. By using this structure the linear regulators work stable even with a
minimum of 470nF ceramic capacitors at their output.
Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmable
output voltage of 3.3V or 2.6V and Q_LDO3 is programmable to 5V or 3.3V (see 2.2.2).
All three regulators are on all the time, if one regulator is not needed a base load resistor
in parallel to the output capacitance for controlled power down is recommended.

2.2.1 Startup Sequence Linear Regulators

When acting as 32 bit µC supply the so-called power sequencing (the dependency of the
different voltage reails to each other) is important. Within the TLE 6361 G the following
Startup-Sequence is defined (see also figure 4):
VQ_LDO2 ≤ VQ_LDO1; VQ_LDO3 ≤ VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V and VQ_LDO3 = 3.3V
and
VQ_LDO2 ≤ VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V/3.3V and VQ_LDO3 = 5V

The power sequencing refers to the regulator itself, externally voltages applied at
Q_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lower
than those outputs.
That means for the power down sequencing if different output capacitors and different
loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and
Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this
behaviour three Schottky diodes have to be connected between the three outputs of the
linear regulators in that way that the cathodes of the diodes are always connected to the
higher nominal rail.

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Power Sequencing
VFB/L_IN

VLDO_EN

VQ_LDO1
5V
VRth5
3.3V
2.6V

VQ_LDO2 (2.6V Mode)

0.7V
5V LDO 5V LDO
2.6V
VRth2.6
0.7V
t

VQ_LDO3 (3.3V Mode)

5V LDO 5V LDO
3.3V
VRth3.3
+/- 50mV
+/- 50mV
t

Figure 4 Power-up and -down sequencing of the regulators

2.2.2 Q_LDO2 and Q_LDO3 output voltage selection*

To determine the output voltage levels of the three linear regulators, the selection pin
(SEL, pin 23) has to be connected according to the matrix given in the table below.
Definition of Output voltage Q_LDO2 and Q_LDO3
Select Pin SEL Q_LDO2 Q_LDO3
connected to output voltage output voltage
GND 3.3 V 5V
Q_LDO1 2.6 V 3.3 V
Q_LDO2 2.6 V 5V

* for different output voltages please refer to the multi voltage supply TLE6368

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2.3 Voltage Trackers

For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output
current capability each are available. The output voltages match Q_LDO1 within
+5 / -15mV. They can be individually turned on and off by the appropriate SPI command
word sent by the microcontroller. A ceramic capacitor with the value of 1µF at the output
of each tracker is sufficient for stable operation without oscillation.
The tracker outputs can be connected in parallel to obtain a higher output current
capability, no matter if only two or up to all six trackers are tied together. For uniformly
distributed current density in each tracker internal balance resistors at each output are
foreseen internally. By connecting twice three trackers in parallel two sensors with more
than 50mA each can be supplied, all six in parallel give more than 100mA.
The tracker outputs can withstand short circuits to GND or battery in a range from -5 to
+60V. A short circuit to GND at is detected and indicated individually for each tracker in
the SPI status word. Also an open load condition might be recognised and indicated as
a failure condition in the SPI status word. A minimum load current of 2mA is required to
avoid open load failure indication. In case of connecting several trackers to a common
branch balancing currents can prevent proper operation of the failure indication.

2.4 Standby Regulator

The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output
current which is on all the time. It is intended to supply the microcontroller in stop mode
and requires then only a minimum of quiescent current (<30µA) to extend the battery
lifetime.

2.5 Charge Pump

The 1.6 MHz charge pump with the two external capacitors will serve to supply the base
of the NPN linear regulators Q_LDO1 and Q_LDO3 as well as the gate of the Buck
DMOS transistor in 100% duty cycle operation at low battery condition. The charge pump
voltage in the range of 8 to 10V can be measured at pin 22 (CCP) but is not intended to
be used as a supply for additional circuitry.

2.6 Power On Reset

A power on reset is available for each linear voltage regulator output. The reset output
lines R1, R2 and R3 are active (low) during start up and turn inactive with a reset delay
time after Q_LDO1, Q_LDO2 and Q_LDO3 have reached their reset threshold. The
reset outputs are open collector, three pull up resistors of 10kΩ each have to be
connected to the I/O rail (e.g. Q_LDO1) of the µC. All three reset outputs can be linked
in parallel to obtain a wired-OR.
The reset delay time is 64 ms by default and can be set to lower values as 8 ms, 16 ms
or 32 ms by SPI command. At each power up of the device when the output voltage at

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Q_LDO1 has decreased below 3.3V (max.) the default settings are valid, means the
64ms delay time. If the voltage on Q_LDO1 during sleep or power off mode was kept
above 3.3V the delay time set by the last SPI command is valid.

VFB/L_IN

< trr t
VQ_LDOx
VRTH,Q_LDOx

trr t
VRx tRES tRES tRES tRES

t
thermal under over
shutdown voltage load

Figure 5 Undervoltage reset timing

2.7 RAM good flag

A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops
below 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAM
good flags can be read after power up to determine if a cold or warm start needs to be
processed. Both RAM good flags will be reset after each SPI cycle.

2.8 ERR Pin

An hardware error pin indicates any fault conditions on the chip. It should be connected
to an interrupt input of the microcontroller. A low signal indicates an error condition. The
microcontroller can read the root cause of the error by reading the SPI register.

2.9 Window Watchdog

The on board window watchdog for supervision of the µC works in combination with the
SPI. The window watchdog logic is triggered when CS is low and Bit WD-Trig in the SPI
command word is set to “1”. The watchdog trigger is recognized with the low to high
transition of the CS signal. To allow reading the SPI at any time without getting a reset
due to misinterpretation the WD-Trig bit has to be set to “0” to avoid false trigger
conditions. To disable the window watchdog the WD-OFF bits need to be set to “010”.

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tSR = tOW/2 tWDR = tRES

tCW=tCW tOW=tCW (not the same scale) (not the same scale)

definition closed window open window reset delay time without trigger

reset start delay time after window reset duration time after window
definition watchdog timeout watchdog time-out

tECW t EOW = end of open window

Example with:
tCW=128ms
fOSC=fOSCmax t EOW, w.c.= ( tCW+tOW )(1-∆)
∆=25% (oscillator deviation)
worst cases
tECW, w.c. = 128(1.25) = 160ms
fOSC=fOSCmin t ECW, w.c.= tCW (1+∆)
tEOW, w.c = (128+128)(0.75) = 192ms

t OWmin towmin = 32ms

Minimum open window time: t OWmin= tOW - ∆ * ( tOW + 2* tCW )

Figure 6 Window watchdog timing definition

Figure 6 shows some guidelines for designing the watchdog trigger timing taking the
oscillator deviation of different devices into account. Of importance is the maximum
(w.c.) of the closed window and the minimum of the open window in which the trigger has
to occur.
The length of the OW and CW can be modified by SPI command. If a change of the
window length is desired during the Watchdog function is operating please send the SPI
command with the new timing with a ’Watchdog trigger Bit’ D15=1.In this case the next
CW will directly start with the new length.
A minimum time gap of > 1/48 of the actual OW/CW time between a ’Watchdog disable’
and ’Watchdog enable’ SPI-command should be maintained. This allows the internal
Watchdog counters to be resetted. Thus after the enable command the Watchdog will
start properly with a full CW of the adjusted length.

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Perfect triggering after Power on Reset

VQ_LDO1
VRth1

1V
t

tRES
R1

Watchdog tCW tSR

window
CW OW CW OW CW CW OW
t

CS
with WD-
trig=1
t

ERR

Incorrect triggering
Watchdog
window
CW OW
t

CS
with WD-
trig=1
t
1) 2)

1) Pretrigger
2) Missing trigger

Legend: OW = Open window

CW = Closed window

Figure 7 Window watchdog timing

Figure 7 gives some timing information about the window watchdog. Looking at the
upper signals the perfect triggering of the watchdog is shown. When the 5V linear
regulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before

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the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect
on the reset line and/or error pin is observed. With the missing watchdog trigger signal
the error signal turns low immediately where the reset is asserted after another delay of
half the closed window time.
Also shown in the figure are two typical failure modes, one pretrigger and one missing
signal. In both cases the error signal will go low immediately the failure is detected with
the reset following after the half closed window time.

2.10 Overtemperature Protection

At a chip temperature of more than 130° an error and temperature flag is set and can be
read through the SPI. The device is switched off if the device reaches the
overtemperature threshold of 170°C. The overtemperature shutdown has a hysteresis to
avoid thermal pumping.

2.11 Power Down Mode

The TLE 6361 G is started by a static high signal at the wake input or a high pulse with
a minimum of 50µs duration at the Wake input (pin 34). In order to avoid instabilities of
the device voltages applied to the Wake pin (pin 34) have to have a certain slope, i.e.
1V/3µs. Voltages in the range between the turn on and turn off thresholds for a few 100µs
must be avoided!
By SPI command (“Sleep”-bit, D8, equals zero) all voltage regulators including the
switching regulator except the standby regulator can be turned off completely only if the
wake input is low. In the case the Wake input is permanently connected to battery the
device cannot be turned off by SPI command, it will always turn on again.
For stable “on” operation of the device the “Sleep”-bit, D8 has to be set to high at each
SPI cycle!
When powering the device again after power down the status of the SPI controlled
devices (e.g. trackers, watchdog etc.) depends on the output voltage on Q_LDO1. Did
the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section)
is set otherwise the last SPI command defines the status.

2.12 Serial Peripheral Interface

A standard 16bit SPI is available for control and diagnostics. It is capable to operate in a
daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPI
interface.
The 16-bit control word (write bit assignment, see figure 8) is read in via the data input DI,
synchronous to the clock input CLK supplied by the µC. The diagnosis word appears in
the same way synchronously at the data output DO (read bit assignment, see figure 9),
so with the first bit shifted on the DI line the first bit appears on the DO line.

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The transmission cycle begins when the TLE 6361 G is selected by the “not chip select”
input CS (H to L). After the CS input returns from L to H, the word that has been read in
at the DI line becomes the new control word. The DO output switches to tristate status at
this point, thereby releasing the DO bus circuit for other uses. For details of the SPI
timing please refer to figures 10 to 13.
The SPI will be reset to default values given in the following table “write bit meaning” if
the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V).
The reset will be active as long as the power on reset is present so during the reset delay
time at power up no SPI commands are acceptable.
The register content of the SPI - including watchdog timings and reset delay timings - is
maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not
decrease below 3.3V).

2.12.1 Write mode

The following tables show the bit assignment to the different control functions, how to
change settings with the right bit combination and also the default status at power up.

2.12.2 Write mode bit assignment

BIT DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D 15

WD_OF NOT T1- T2- T6- T4- T5- T6- WD_OF WD_OF
Name F1 assigned control control control control control control
sleep
F2
reset 1 reset 2 WD 1 WD 2
F3
WD-Trig

Default 1 X 0 0 0 0 0 0 1 1 0 0 0 0 1 0

Figure 8 Write Bit assignment

Write Bit meaning

Function Bit Combination Default
Not assigned D1 X X
Tracker 1 to 6 - control: D2 0: OFF 0
turn on/off the individual trackers D3 1: ON
D4
D5
D6
D7
Power down: D8 0: SLEEP 1
send device to sleep 1: NORMAL

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Write Bit meaning

Function Bit Combination Default
Reset timing: D10D11 00: 64ms 00
Reset delay time tRES valid at warm start 10: 32ms
01: 16ms
11: 8ms
Window watchdog timing: D12D13 00: 128ms 00
Open window time tOW and 10: 64ms
closed window time tCW valid at warm start 01: 32ms
11: 16ms
Window watchdog function: D0D9D14 010: OFF 111
Enable /disable window watchdog 1xx: ON
x0x: ON
xx1: ON
Window watchdog trigger: D15 0: not triggered 1
Enable / disable window watchdog trigger 1: triggered

2.12.3 Read mode

Below the status information word and the bit assignments for diagnosis are shown.

2.12.3.1 Read mode bit assignment

BIT DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D 15

temp_ T1- T2- T3- T4- T5- T6- RAM RAM WD WD DC/DC
Name ERROR
warn status status status status status status Good 1 Good 2 Window
R-Error1 R-Error2 R-Error3
Error status

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Figure 9 Read Bit assignment

Error bit D0:

The error bit indicates fail function and turns high if the temperature prewarning, the
watchdog error is active, further if one RAM good indicates a cold start or if a voltage
tracker does not settle within 1ms when it is turned on.
In addition to the error indication by software the ERR pin atcs as a hardware error flag.

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Read Bit meaning

Function Type Bit Combination Default
Error indication, Latched D0 0: normal operation 0
explanation see below this 1: fail function
table
Overtemperature warning Not latched D1 0: normal operation 0
1: prewarning
Status of Tracker Output Not latched D2 1: settled output 0
Q_T[1:6],only if output is D3 voltage
ON D4 0:Tracker turned
D5 off or
D6 shorted output.
D7 Also open load
may possibly be
indicated as 0.1)
Indication of cold start/ Latched D8 0: cold start 0
warm start, Q_LDO1 1: warm start
Indication of cold start/ Latched D9 0: cold start 0
warm start, Q_LDO2 1: warm start
Indication for open or Not latched D10 0: open window 0
closed window 1: closed window
Reset condition at output Not latched D11 0: normal operation 0
Q_LDO1 1: Reset R1
Reset condition at output Not latched D12 0: normal operation 0
Q_LDO2 1: Reset R2
Reset condition at output Not latched D13 0: normal operation 0
Q_LDO3 1: Reset R3

Watchdog Error Latched D14 0: normal operation 0

1: WD error
DC/DC converter status Not latched D15 0: off 1
1: on
1)
Min. load current to avoid ’0’ signal caused by open load is 2mA.

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2.12.4 SPI Timings

CS High to Low & rising edge of CLK: DO is enabled.

Status information is transferred to Output Shift Register

CS

CS Low to High: Data from Register time

are transferred to e.g. Trackers

CLK 0 1 2 3 13 14 15 0 1

Data In (N) Data In (N+1)

D0 D1
DI D0 D1 D2 D3 D13 D14 D15
+ +
DI: Data will be accepted on the falling edge of CLK-Signal

Data Out (N-1) Data Out (N)

DO D0 D1 D2 D3 D13 D14 D15 D0 D1

DO: State will change on the rising edge of CLK-Signal

e.g.
Tracker-
Setting (N-1) Setting (N)
control

e.g.
Tracker-
Status (N-1) Status (N)
status

Figure 10 SPI Data Transfer Timing

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Figure 11 SPI-Input Timing

trIN tfIN <10ns

0.7 VQ_LDO1
CLK 50%
0.2 VQ_LDO1

trDO

90%
DO (low to high)
10%
tVADO

tfDO

90%
DO (high to low)
10%

Figure 12 DO Valid Data Delay Time and Valid Time

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tfIN trIN <10ns

0.7 VQ_LDO1
CS 50%
0.2 VQ_LDO1

10kΩ
DO Pullup
50%
to VQ_LDO1
tENDO tDISDO

10kΩ
Pulldown 50%
DO to GND

Figure 13 DO Enable and Disable Time

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3 Characteristics

3.1 Absolute Maximum Ratings

Item Parameter Symbol Limit Values Unit Test Condition

Min. Max.
3.1.1 Supply Voltage Input IN
Voltage VVS -0.5 60 V –
Current IVS – – –
3.1.2 Buck-Switch Output SW
Voltage VSW -2 VS+0.5 V –
Current ISW – – –
3.1.3 Feedback and Linear Voltage Regulator Input
Voltage VFB/L_IN -0.5 8 V –
Current IFB/L_IN – – –
3.1.4 Bootstrap Connector Bootstrap
Voltage VBootstrap VSW- VSW+ V
0.5V 10V
Voltage VBootstrap -0.5 70 V
Current IBootstrap – – – Internally Limited
3.1.5 Boost Input
Voltage VBoost -0.5 60 V –
Current IBoost – – – Internally Limited
3.1.6 Slope Control Input Slew
Voltage VSlew -0.5 6 V –
Current ISlew – – – Internally Limited
3.1.7 Charge Pump Capacitor Connector C-
Voltage VCL -0.5 VFB/L_IN V
+0.5
Current ICL -150 +150 mA

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3.1.8 Charge Pump Capacitor Connector C+

Voltage VCH -0.5 13 V
Current ICH -150 +150 mA

3.1.9 Charge Pump Storage Capacitor CCP

Voltage VCCP -0.5 12 V
Current ICCP -150 – mA
3.1.10 Standby Voltage Regulator output Q_STB
Voltage VQ_Stb -0.5 6 V –
Current IQ_Stb – – – Internally limited
3.1.11 Voltage Regulator output voltage Q_LDO1
Voltage VQ_LDO1 -0.5 6 V –
Current IQ_LDO1 – – – Internally limited
3.1.12 Voltage Regulator output voltage Q_LDO2
Voltage VQ_LDO2 -0.5 6 V –
Current IQ_LDO2 – – – Internally limited
3.1.13 Voltage Regulator output voltage Q_LDO3
Voltage VQ_LDO3 -0.5 6 V –
Current IQ_LDO3 – – – Internally limited
3.1.14 Voltage Tracker output voltage Q_T1
Voltage VQ_T1 -5 60 V –
Current IQ_T1 – – mA Internally limited
3.1.15 Voltage Tracker output voltage Q_T2
Voltage VQ_T2 -5 60 V –
Current IQ_T2 – – mA Internally limited
3.1.16 Voltage Tracker output voltage Q_T3
Voltage VQ_T3 -5 60 V –
Current IQ_T3 – – mA Internally limited
3.1.17 Voltage Tracker output voltage Q_T4
Voltage VQ_T4 -5 60 V –
Current IQ_T4 – – mA Internally limited

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3.1.18 Voltage Tracker output voltage Q_T5

Voltage VQ_T5 -5 60 V –
Current IQ_T5 – – mA Internally limited
3.1.19 Voltage Tracker output voltage Q_T6
Voltage VQ_T6 -5 60 V –
Current IQ_T6 – – mA Internally limited
3.1.20 Select Input SEL
Voltage VSEL -0.5 6 V –
Current ISEL – – – Internally limited
3.1.21 Wake Up Input Wake
Voltage VWake -0.5 60 V –
Current IWake – – –
3.1.22 Reset Output R1
Voltage VR1 -0.5 6 V –
Current IR1 – – –
3.1.23 Reset Output R2
Voltage VR2 -0.5 6 V –
Current IR2 – – –
3.1.24 Reset Output R3
Voltage VR3 -0.5 6 V –
Current IR3 – – –
3.1.25 SPI Data Input DI
Voltage VDI -0.5 6 V –
Current IDI – – –
3.1.26 SPI Data Output DO
Voltage VDO -0.5 6 V –
Current IDO – – – Internally limited
3.1.27 SPI Clock Input CLK
Voltage VCLK -0.5 6 V –
Current ICLK – – –

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3.1.28 SPI Chip Select Not Input CS

Voltage VCS -0.5 6 V –
Current ICS – – –
3.1.29 Error Output Pin
Voltage VError -0.5 6 V –
Current IError – – – Internally limited
3.1.30 Thermal Resistance
1)
Junction- Rthja 37 K/W PCB heat sink area
ambient 300mm2
1)
Junction- Rthja 29 K/W PCB heat sink area
ambient 600mm2
Junction- Rthjc – 2 K/W
case
3.1.31 Temperature
Junction Tj -40 150 °C
temperature
Junction Tjt 175 °C lifetime=TBD
temperature
transient
Storage Tstg -50 150 °C
temperature

3.1.32 ESD - Protection (Human Body Model; 1.5kΩ; C=100pF)

Electrostatic VESD -1 1 kV All pins
discharge
voltage

1) Package mounted on FR4 47x50x1.5mm3; 70µ Cu, zero airflow

Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.

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3.2 Functional Range

-40°C < Tj < 150 °C
Item Parameter Symbol Limit Values Unit Condition
min. max.
Supply VIN 5.5 V To achieve VIN,min an
Voltage initial startup with
VIN >8V is required;
Supply VIN 60 V
Voltage
Ripple at VFB/L_IN 0 150 mVPP
FB/L_IN ripple

Note: Within the functional range the IC can be operated . The electrical characteristics,
however, are not guaranteed over this full functional range

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3.3 Recommended Operation Range

-40°C < Tj < 150 °C
Item Parameter Symbol Limit Values Unit Condition
min. typ. max.
1)
Buck LB 18 100 µH
Inductor
Buck CB 10 µF ESR <0.15 Ω,
Capacitor ceramic
capacitor (X7R)
recommended1)
Bootstrap CBTP 2 % of CB
Capacitor
SLEW RSLEW 0 20 kΩ
resistor
Linear CQ_LDO1-3 470 nF ceramic
regulator capacitor (X7R)
capacitors
Tracker CQ_T1-6 1 µF ceramic
bypass capacitor (X7R)
capacitors
SPI rise and tr,f 200 ns
fall timings,
CS, DI, CLK
1)
CB, min needs a Buck inductance LB=47µH to avoid instabilities

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3.4 Electrical Characteristics

The electrical characteristics involve the spread of values guaranteed within the
specified supply voltage and ambient temperature range. Typical values represent the
median values at room temperature, which are related to production processes.
-40 < Tj <150 °C; VIN=13.5V unless otherwise specified
Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Buck regulator
3.4.1 Switching fSW 280 370 425 kHz
frequency
3.4.2 Current tr_I_SW 20 ns RSL=0Ω 1)
transition
time, min.,
rising edge
3.4.3 Current tr_I_SW 100 ns RSL=20kΩ 1)
transition
time, max.,
rising edge
3.4.4 Current tf_I_SW 20 ns RSL=0Ω 1)
transition
time, min.,
falling edge
3.4.5 Current tf_I_SW 100 ns RSL=20kΩ 1)
transition
time, max.,
falling edge
1)
3.4.6 Voltage rise / tf_V_SW 25 ns
fall time
3.4.7 Static on RON 160 mΩ Tj=25°C
resistance in static operation
3.4.8 Static on RON 280 400 mΩ Tj=150°C
resistance in static operation
3.4.9 Current limit IMAX 1.5 3.2 A VFB/L_IN=5.4V
3.4.10 Output VOUT 5.4 6.3 V IOUT=0.1A
voltage VIN=13.5 V
3.4.11 Output VOUT 5.4 6.05 V IOUT=1.5A
voltage VIN=13.5 V

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.12 Bootstrap IBTSTR 80 160 220 µA
charging
current at
start-up
3.4.13 Bootstrap VBTSTR 10 17 V VFB/L_IN=6.5V,
voltage Buck converter
(internal off
charge
pump)
3.4.14 Bootstrap VBTSTR, 5 9 V
undervoltage turn on
lockout, Buck
turn on
threshold
3.4.15 Bootstrap VBTSTR, 2.5 V
undervoltage turn on -
lockout, VBTSTR,
hysteresis turn off

3.4.16 Charge VCCP 7.9 11.0 V IQ_LDO1 = 800mA,

pump VFB/L_IN=6.0V,
voltage CFLY=100nF,
CCCP=220nF
3.4.17 Max. Duty dutymax 95 % Switching
Cycle operation
3.4.18 Min. Duty dutymin 0 % Static-off
Cycle operation
Voltage Regulator Q_LDO1
3.4.19 Output VQ1 4.9 5.1 V 100mA < IQ_LDO1
voltage < 800mA
3.4.20 Output VQ1 5.0 V IQ_LDO1 = 800mA
voltage
3.4.21 Load ∆VQ_LDO1 40 mV 100mA< IQ_LDO1
Regulation <800mA;
VFB/L_IN=5,5V
3.4.22 Current limit IQ_LDO1limit 800 1050 1400 mA VQ_LDO1=4V

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.23 Ripple PSRR1 26 40 dB f=330kHz; 1)
rejection
3.4.24 Output CQ_LDO1 470 nF Ceramic type,
Capacitor value for stability
Voltage Regulator Q_LDO2
3.4.25 Output VQ_LDO2 3.14 3.46 V 50mA < IQ_LDO2 <
voltage 3.3V 400mA;
3.3V mode
3.4.26 Output VQ_LDO2 3.32 V IQ_LDO2 =400mA;
voltage 3.3V 3.3V mode
3.4.27 Output VQ_LDO2 2.500 2.750 V 50mA < IQ_LDO2 <
voltage 2.6V 400mA;
2.6V mode
3.4.28 Output VQ_LDO2 2.62 V IQ_LDO2 =400mA;
voltage 2.6V 2.6V mode
3.4.29 Load ∆VQ_LDO2 50 mV 50mA< IQ_LDO3
Regulation <400mA;
VFB/L_IN=5.5V
3.3V mode
3.4.30 Load ∆VQ_LDO2 50 mV 50mA< IQ_LDO2
Regulation <400mA;
VFB/L_IN=5.5V
2.6V mode
3.4.31 Current limit IQ_LDO2limit 500 650 850 mA VQ_LDO2= 2.8V;
3.3V mode
3.4.32 Current limit IQ_LDO2limit 500 650 850 mA VQ_LDO2= 2V;
2.6V mode
3.4.33 Ripple PSRR2 26 40 dB f=330kHz; 1)
rejection
3.4.34 Output CQ_LDO2 470 nF Ceramic type,
Capacitor value for stability
Voltage Regulator Q_LDO3

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.35 Output VQ_LDO3 4.8 5.2 V 20mA < IQ_LDO3 <
voltage 5V 300mA;
5V mode
3.4.36 Output VQ_LDO3 5.0 V IQ_LDO3 =300mA;
voltage 5V 5V mode
3.4.37 Output VQ_LDO3 3.14 3.46 V 20mA < IQ_LDO3 <
voltage 3.3V 300mA;
3.3V mode
3.4.38 Output VQ_LDO3 3.32 V IQ_LDO3 =300mA;
voltage 3.3V 3.3V mode
3.4.39 Load ∆VQ_LDO3 100 mV 20mA< IQ_LDO3
Regulation <300mA;
VFB/L_IN=5,5V
5V mode
3.4.40 Load ∆VQ_LDO3 50 mV 20mA< IQ_LDO3
Regulation <300mA;
VFB/L_IN=5,5V
3.3V mode
3.4.41 Current limit IQ_LDO3 350 500 600 mA VQ_LDO3=4V;
limit 5V mode
3.4.42 Current limit IQ_LDO3 350 500 600 mA VQ_LDO3=2.8V;
limit 3.3V mode
3.4.43 Ripple PSRR3 26 40 dB f=330kHz; 1)
rejection
3.4.44 Output CQ_LDO3 470 nF Ceramic type,
Capacitor value for stability
Voltage Tracker Q_T1
3.4.45 Output ∆VQ_T1 -15 5 mV VQ_T1-VQ_LDO1;
voltage 1mA < IQ_T1 <
tracking 17mA
accuracy
3.4.46 Output ∆VQ_T1 -10 mV VQ_T1-VQ_LDO1;
voltage IQ_T1 = 17mA
tracking
accuracy

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.47 Overvoltage VOVQ_T1 VQ_T1, mV IQ_T1 = 0mA; 1)
threshold nom
1)
3.4.48 Undervoltage VUVQ_T1 VQ_T1- mV
threshold 15mV
3.4.49 Current limit IQ_T1 limit 17 30 mA VQ_T1=4V
3.4.50 Ripple PSRR 26 dB f=330kHz; 1)
rejection
3.4.51 Tracker load CQ_T1 1 µF Ceramic type,
capacitor minimum for
stability
Voltage Tracker Q_T2
3.4.52 Output ∆VQ_T2 -15 5 mV VQ_T2-VQ_LDO1;
voltage 1mA < IQ_T2 <
tracking 17mA
accuracy
3.4.53 Output ∆VQ_T2 -10 mV VQ_T2-VQ_LDO2;
voltage IQ_T2 = 17mA
tracking
accuracy
3.4.54 Overvoltage VOVQ_T2 VQ_T2, mV IQ_T2 = 0mA;1)
threshold nom
1)
3.4.55 Undervoltage VUVQ_T2 VQ_T2- mV
threshold 15mV
3.4.56 Current limit IQ_T2 limit 17 30 mA VQ_T2=4V
3.4.57 Ripple PSRR 26 dB f=330kHz; 1)
rejection
3.4.58 Tracker load CQ_T2 1 µF Ceramic type,
capacitor minimum for
stability

Voltage Tracker Q_T3

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.59 Output ∆VQ_T3 -15 5 mV VQ_T3-VQ_LDO1;
voltage 1mA < IQ_T3 <
tracking 17mA
accuracy
3.4.60 Output ∆VQ_T3 -10 mV VQ_T3-VQ_LDO3;
voltage IQ_T3 = 17mA
tracking
accuracy
3.4.61 Overvoltage VOVQ_T3 VQ_T3, mV IQ_T3 = 0mA; 1)
threshold nom
1)
3.4.62 Undervoltage VUVQ_T3 VQ_T3- mV
threshold 15mV
3.4.63 Current limit IQ_T3 limit 17 30 mA VQ_T3=4V
3.4.64 Ripple PSRR 26 dB f=330kHz; 1)
rejection
3.4.65 Tracker load CQ_T3 1 µF Ceramic type,
capacitor minimum for
stability
Voltage Tracker Q_T4
3.4.66 Output ∆VQ_T4 -15 5 mV VQ_T4-VQ_LDO1;
voltage 1mA < IQ_T4 <
tracking 17mA
accuracy
3.4.67 Output ∆VQ_T4 -10 mV VQ_T4-VQ_LDO4;
voltage IQ_T4 = 17mA
tracking
accuracy
3.4.68 Overvoltage VOVQ_T4 VQ_T4, mV IQ_T4 = 0mA; 1)
threshold nom
1)
3.4.69 Undervoltage VUVQ_T4 VQ_T4- mV
threshold 15mV
3.4.70 Current limit IQ_T4 limit 17 30 mA VQ_T4=4V
3.4.71 Ripple PSSR 26 dB f=330kHz; 1)
rejection

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.72 Tracker load CQ_T4 1 µF Ceramic type,
capacitor minimum for
stability
Voltage Tracker Q_T5
3.4.73 Output ∆VQ_T5 -15 5 mV VQ_T5-VQ_LDO1;
voltage 1mA < IQ_T5 <
tracking 17mA
accuracy
3.4.74 Output ∆VQ_T5 -10 mV VQ_T5-VQ_LDO5;
voltage IQ_T5 = 17mA
tracking
accuracy
3.4.75 Overvoltage VOVQ_T5 VQ_T5, mV IQ_T5 = 0mA; 1)
threshold nom
1)
3.4.76 Undervoltage VUVQ_T5 VQ_T5- mV
threshold 15mV
3.4.77 Current limit IQ_T5 limit 17 30 mA VQ_T5=4V
3.4.78 Ripple PSRR 26 dB f=330kHz; 1)
rejection
3.4.79 Tracker load CQ_T5 1 µF Ceramic type,
capacitor minimum for
stability
Voltage Tracker Q_T6
3.4.80 Output ∆VQ_T6 -15 5 mV VQ_T6-VQ_LDO1;
voltage 1mA < IQ_T6 <
tracking 17mA
accuracy
3.4.81 Output ∆VQ_T6 -10 mV VQ_T6-VQ_LDO6;
voltage IQ_T6 = 17mA
tracking
accuracy
3.4.82 Overvoltage VOVQ_T6 VQ_T6, mV IQ_T6 = 0mA; 1)
threshold nom

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
1)
3.4.83 Undervoltage VUVQ_T6 VQ_T6- mV
threshold 15mV
3.4.84 Current limit IQ_T6 limit 17 30 mA VQ_T6=4V
3.4.85 Ripple PSRR 26 dB f=330kHz; 1)
rejection
3.4.86 Tracker load CQ_T6 1 µF Ceramic type,
capacitor minimum for
stability
Standby Regulator
3.4.87 Output VQ_STB 2.2 2.4 2.6 V 0µA
voltage <IQ_STB<500µA

3.4.88 Current limit IQ_STB limit 1 3 6 mA VQ_STB=2V

3.4.89 Standby CQ_STB 100 nF Ceramic type,
load minimum for
capacitor stability
Off-Mode
3.4.90 Supply Iq,off 10 30 µA VIN=13.5V,
current from Vwake=0V,
battery IQ_STB=0µA
3.4.91 Supply Iq,off 10 30 µA VIN=42V,
current from Vwake=0V
battery IQ_STB=0µA
3.4.92 Turn on Vwake th, on 2.4 2.8 V Vwake increasing
Wake-up
threshold
3.4.93 Turn off Vwake th, off 1.8 2.35 V Vwake decreasing
Wake-up
threshold
3.4.94 Wake-up Iwake 50 150 µA Vwake=5V
input current
3.4.95 Wake up twake,min 4 10 50 µs Vwake >
input on time Vwake th, on max; 1)
Reset R1

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-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.96 Reset VRTH 4.5 4.65 4.8 V VQ_LDO1
threshold Q_LDO1, de decreasing
Q_LDO1
3.4.97 Reset VRTH 4.55 4.70 4.9 V VQ_LDO1
threshold Q_LDO1, in increasing
Q_LDO1
3.4.98 Reset output VR1 L 0.4 V IR1=1.6mA;
low voltage VQ_LDO1 =5V
3.4.99 Reset output VR1 L 0.3 V IR1=0.3mA;
low voltage VQ_LDO1 =1V
3.4.100 Reset High IR1 H 1 µA
leakage
current
Reset R2
3.4.101 Reset VRTH 2.6 2.8 3.0 V 3.3V mode;
threshold Q_LDO2, de VQ_LDO2
Q_LDO2 decreasing
3.4.102 Reset VRTH 40 mV 3.3V mode
threshold Q_LDO2, in -
hysteresis VRTH
Q_LDO2 Q_LDO2, de

3.4.103 Reset VRTH 2.3 2.4 2.5 V 2.6V mode;

threshold Q_LDO2, de VQ_LDO2
Q_LDO2 decreasing
3.4.104 Reset VRTH 40 mV 2.6V mode
threshold Q_LDO2, in -
hysteresis VRTH
Q_LDO2 Q_LDO2, de

3.4.105 Reset output VR2 L 0.4 V IR2=1.6mA;

low voltage VQ_LDO2 =2.5V
3.4.106 Reset output VR2 L 0.3 V IR2=0.3mA;
low voltage VQ_LDO2 =1V
3.4.107 Reset High IR2 H 1 µA
leakage
current

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TLE 6361 G

-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Reset R3
3.4.108 Reset VRTH 2.7 2.85 3.0 V 3.3V mode;
threshold Q_LDO3, de VQ_LDO3
Q_LDO3 decreasing
3.4.109 Reset VRTH 40 mV 3.3V mode
threshold Q_LDO3, in -
hysteresis VRTH
Q_LDO3 Q_LDO3, de

3.4.110 Reset VRTH 4.0 4.2 4.5 V 5V mode;

threshold Q_LDO3, de VQ_LDO3
Q_LDO3 decreasing
3.4.111 Reset VRTH 40 mV 5V mode
threshold Q_LDO3, in -
hysteresis VRTH
Q_LDO3 Q_LDO3, de

3.4.112 Reset output VR3 L 0.4 V IR3=1.6mA;

low voltage VQ_LDO3 =3.3V
3.4.113 Reset output VR3 L 0.3 V IR3=0.3mA;
low voltage VQ_LDO3 =1V
3.4.114 Reset High IR3 H 1 µA
leakage
current
1)
3.4.115 Reset trr 1 2 10 µs
reaction time Valid for R1, R2
and R3
3.4.116 Reset Delay tNORM,RES 0.75 1 1.25 1
Norm factor
3.4.117 Reset Delay tRES 0.75 1 1.25 tRES(SPI) Valid for R1, R2
time and R3; tRES (SPI)
is defined by the
SPI word (see
section 2.12)
RAM Good
3.4.118 VQ1 threshold VTh Q1 2.3 2.8 3.3 V

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TLE 6361 G

-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.119 VQ2 threshold VTh Q2 1.2 1.4 1.7 V 3.3V mode
3.4.120 VQ2 threshold VTh Q2 1.2 1.4 1.7 V 2.6V mode; 1)
Window Watchdog
3.4.121 Closed tCW_tol 0.75 1 1.25 Multiply with
window time watchdog
tolerance window time set
by SPI to obtain
the limits (2.12)
3.4.122 Open tOW_tol 0.75 1 1.25 Multiply with
window time watchdog
tolerance window time set
by SPI to obtain
the limits (2.12)
3.4.123 Watchdog tWRL tRES
reset low
time
3.4.124 Watchdog tSR tCW/2
reset delay
time
Error Output ERR
3.4.125 H-output VERR,H VQ_LDO1 VQ_LDO1 – V IERR, H = 1 mA
voltage level – 2.0 – 0.7
3.4.126 L-output VERR,L – 0.3 0.5 V IERR, L = – 1.6 mA
voltage level

SPI
3.4.127 SPI clock fCLK 0 2.5 MHz Production test
frequency up to 1MHz;
2.5MHz 1)
SPI Input DI

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TLE 6361 G

-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.128 H-input VIH – 40 70 % of –
voltage VQ_LDO1
threshold
3.4.129 L-input VIL 20 36 – % of –
voltage VQ_LDO1
threshold
3.4.130 Hysteresis of VIHY 50 200 500 mV 1)

input voltage
3.4.131 Pull down II 5 25 100 µA VDI = 0.2 *
current VQ_LDO1
3.4.132 Input CI – 10 15 pF 0 V < VQ_LDO1 <
capacitance 5.25 V
1)
3.4.133 Input signal tr – – 200 ns
rise time
1)
3.4.134 Input signal tf – – 200 ns
fall time
SPI Clock Input CLK
3.4.135 H-input VIH – 40 70 % of –
voltage VQ_LDO1
threshold
3.4.136 L-input VIL 20 36 – % of –
voltage VQ_LDO1
threshold
3.4.137 Hysteresis of VIHY 50 200 500 mV 1)

input voltage
3.4.138 Pull down II 5 25 100 µA VCLK = 0.2 *
current VQ_LDO1
3.4.139 Input CI – 10 15 pF 0 V < VQ_LDO1 <
capacitance 5.25 V
1)
3.4.140 Input signal tr – – 200 ns
rise time
1)
3.4.141 Input signal tf – – 200 ns
fall time
SPI Chip Select Input CS

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TLE 6361 G

-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.142 H-input VIH – 39 70 % of –
voltage VQ_LDO1
threshold
3.4.143 L-input VIL 20 35 – % of –
voltage VQ_LDO1
threshold
3.4.144 Hysteresis of VIHY 50 200 500 mV 1)

input voltage
3.4.145 Pull up II, CS – 100 – 25 –5 µA VCS = 0.2 *
current at pin VQ_LDO1
CS
3.4.146 Input CI – 10 15 pF 0 V < VQ_LDO1 <
capacitance 5.25 V
1)
3.4.147 Input signal tr – – 200 ns
rise time
1)
3.4.148 Input signal tf – – 200 ns
fall time

Logic Output DO

3.4.149 H-output VDOH VQ_LDO1 VQ_LDO1 – V IDOH = 1 mA

voltage level – 1.0 – 0.8
3.4.150 L-output VDOL – 0.2 0.4 V IDOL = – 1.6 mA
voltage level
3.4.151 Tri-state IDO_TRI – 10 – 10 µA VCS = VQ_LDO1;
leakage 0 V < VDO <
current VQ_LDO1
3.4.152 Tri-state CDO – 10 15 pF VCS = VQ_LDO1
input 0 V < VQ_LDO1 <
capacitance 5.25 V

Data Input Timing

1)
3.4.153 Clock period tpCLK 1000 – – ns

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TLE 6361 G

-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
1)
3.4.154 Clock high tCLKH 500 – – ns
time
3.4.155 Clock low tCLKL 500 – – ns 1)

time
3.4.156 Clock low tbef 500 – – ns 1)

before CS
low
1)
3.4.157 CS setup tlead 500 – – ns
time
1)
3.4.158 CLK setup tlag 500 – – ns
time
1)
3.4.159 Clock low tbeh 500 – – ns
after CS high
1)
3.4.160 DI setup time tDISU 250 – – ns
1)
3.4.161 DI hold time tDIHO 250 – – ns

Data Output Timing

3.4.162 DO rise time trDO – 50 100 ns CL = 100 pF

3.4.163 DO fall time tfDO – 50 100 ns CL = 100 pF

3.4.164 DO enable tENDO – – 250 ns low impedance

time
3.4.165 DO disable tDISDO – – 250 ns high impedance
time
3.4.166 DO valid time tVADO – 100 250 ns VDO < 10%
VDO > 90%
CL = 100 pF

General
2)
3.4.167 Temperature TJ,Flag 140 °C
warning flag
3.4.168 Over TJ,Shutdown 150 170 200 °C
Temperature
shutdown

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TLE 6361 G

-40 < Tj <150 °C; VIN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
3.4.169 Over- ∆Tsd_hys 30 K
Temperature
shutdown
Hysteresis
3.4.170 DeltaTW to TJ,Shutdown 20 K
TSD - TJ,Flag
1)
Specified by design, not subject to production test

2)
Simulated at wafer test only, not absolutely measured

4 Typical performance charcteristics

Buck converter switching frequency
vs. junction temperature
420
fSW

kHz
400

380

360

340

320

300

280
-50 -20 10 40 70 100 130 160
Tj

°C

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TLE 6361 G

Buck converter output voltage at 1.5A load Buck converter current limit
vs. junction temperature vs. junction temperature
6.0 4.0
VFB/L_IN IMAX

V A
5.9 3.5

5.8 3.0

5.7 2.5

5.6 2.0

5.5 1.5

5.4 1.0

5.3 0.5
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Buck converter DMOS on-resistance Start-up bootstrap charging current

vs. junction temperature vs. junction temperature
400 280
RON IBTSTR

mΩ µA
350 240

300 200

250 160

200 120

150 80

100 40

50 0
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj
°C °C

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TLE 6361 G

Bootstrap UV lockout, turn on threshold Q_LDO1 output voltage at 800mA load

vs. junction temperature vs. junction temperature
VBTSTR, 8.5 5.20
turn on VQ_LDO1

V V
8.0 5.15

7.5 5.10

7.0 5.05

6.5 5.00

6.0 4.95

5.5 4.90

5.0 4.85
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Device wake up thresholds Reset1 threshold at drecreasing V_LDO1

vs. junction temperature vs. junction temperature
2.8 VRTH 4.80
Vwake th
Q_LDO1, de

V V
2.7 4.75

2.6 4.70

2.5 4.65

V wake th, on
2.4 4.60

2.3 4.55

Vwake th, off

2.2 4.50

2.1 4.45
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

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TLE 6361 G

Q_LDO1 current limit Q_LDO2 current limit (2.6V mode)

vs. junction temperature vs. junction temperature
1400 850
IQ_LDO1 IQ_LDO2

V V
1300 800

1200 750

1100 700

1000 650

900 600

800 550

700 500
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Q_LDO2 output voltage at 400mA load Q_LDO3 output voltage at 300mA load
(2.6V mode) vs. junction temperature (3.3V mode) vs. junction temperature
2.80 3.50
VQ_LDO2 VQ_LDO3
V V
2.75 3.45

2.70 3.40

2.65 3.35

2.60 3.30

2.55 3.25

2.50 3.20

2.45 3.15
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

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TLE 6361 G

Reset2 threshold at decreasing V_LDO2 Reset3 threshold at decreasing V_LDO3

(2.6V mode) vs. junction temperature (3.3V mode) vs. junction temperature
VRTH 2.60 VRTH 3.00
Q_LDO2, de Q_LDO3, de

V V
2.55 2.95

2.50 2.90

2.45 2.85

2.40 2.80

2.35 2.75

2.30 2.70

2.25 2.65
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Q_LDO3 current limit (3.3V mode) Tracker current limit

vs. junction temperature vs. junction temperature
600 32
IQ_LDO3 IQ_Tx

V mA
550 30

500 28

450 26

400 24

350 22

300 20

250 18
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj
°C °C

Data Sheet, Rev. 1.31 47 2004-10-12

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TLE 6361 G

Tracker accuracy with respect to V_LDO1 Q_STB current limit

vs. junction temperature vs. junction temperature
4 4.0
dVQ_Tx IQ_STB

mV mA
2 3.5

0 3.0

-2 2.5

-4 2.0

-6 1.5

-8 1.0

-10 0.5
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Q_STB output voltage at 500µA load Device current consumption in off mode
vs. junction temperature vs. junction temperature
2.8 35
VQ_STB Iq, off

V µA
2.7 30

2.6 25

2.5 20

2.4 15

2.3 10

2.2 5

2.1 0
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Data Sheet, Rev. 1.31 48 2004-10-12

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TLE 6361 G

5 Application Information

5.1 Application Diagram

RBoost

22 Ω

DBOOST TLE 6361

Standby Q_STB
Regulator
2.5 V CSTB
100 nF
CBOOST
LI BOOST Buck
Up to 100 nF LB
SW 2* Output
47 µH 2* IN
Battery 47 µH CB
CI1 + CI2 CI3 Buck CBTSTR DB + > 10 µF
100 nF 47 µF 10 to Regulator 680 nF 3 A, ceramic or
100 nF SLEW 60 V
BOOTSTRAP > 20 µF
Driver low ESR
RSlew tantalum
0 to Error-
20 kΩ Amplifier
Internal
OSZ PWM Reference
Feedback

To FB/L_IN 2*
IGN
C+
Protection CFLY
10 kΩ
Charge C- 100 nF
Pump
Q_LDO1 Power CCP
WAKE
Down CCCP
Logic
10 kΩ 10 kΩ 10 kΩ SEL 220 nF
R1
Lin. Reg. Q_LDO1
5V CLDO1,1 + CLDO1,2
R2 470 nF 4.7 µF
To Reset Q_LDO2
Lin. Reg. µ-Controller/
µC Logic 3.3/2.6 V CLDO2,1 + CLDO2,2 Memory
470 nF 4.7 µF Supply
R3 Q_LDO3
Lin. Reg.
5/3.3 V CLDO3,1 + CLDO3,2
470 nF 4.7 µF
Ref
Tracker Q_T1
Window 5V CT1
Watchdog 1 µF
Ref
Tracker Q_T2
5V CT2
Ref 1 µF
10 kΩ CLK Q_T3
Tracker
5V CT3
1 µF Sensor
10 kΩ Ref Supplies
CS Tracker Q_T4
(off board
5V CT4
SPI supplies)
16 Bit Ref 1 µF
To 10 kΩ DI Q_T5
Tracker
µC 5V CT5
Ref 1 µF
1 kΩ DO Q_T6
Tracker
5V CT6
ERR 1 µF
GND
4*
AEA03380_6361ZR.VSD

Figure 14 Application Diagram

Data Sheet, Rev. 1.31 49 2004-10-12

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TLE 6361 G

5.2 Buck converter circuit

A typical choice of external components for the buck converter is given in figure 14. For
basic operation of the buck converter the input capacitor CI2, the bootstrap capacitor
CBTP, the catch diode DB, the induuctance LB, the output capacitor CB and the charge
pump capacitors CFLY and CCCP are necessary.
The additional components shown on top of the circuit lower the electromagnetic
emission (LI, CI1, CI3, RSlew) and the switching losses (RBoost, CBoost, DBoost). For 12V
battery systems the switching loss minimization feature might not be used. In that case
the Boost pin (33) is connected directly to the IN pins (32, 30) and the components
RBoost, CBoost and DBoost are left away

5.2.1 Buck inductance (LB) selection:

The inductance value determines together with the input voltage, the output voltage and
the switching frequency the current ripple which occurs during normal operation of the
step down converter. This current ripple is important for the all over ripple at the output
of the switching converter.
As a rule of thumb this current ripple ∆I is chosen between 10% and 50% of the load
current.

( V I – V OUT ) ⋅ V OUT
L = --------------------------------------------------
-
f SW ⋅ V I ⋅ ∆I

For optimum operation of the control loop of the Buck converter the inductance value
should be in the range indicated in section 3.3, recommended operation range.
When picking finally the inductance of a certain supplier (Epcos, Coilcraft etc.) the
saturation current has to be considered. With a maximum current limit of the Buck
converter of 3.2A an inductance with a minimum saturation current of 3.2A has to be
chosen.

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TLE 6361 G

5.2.2 Buck output capacitor (CB) selection:

The choice of the output capacitor effects straight to the minimum achievable ripple
which is seen at the output of the buck converter. In continuous conduction mode the
ripple of the output voltage equals:

V Ripple = ∆I ⋅  R ESRCB + ----------------------------

1
 8⋅f ⋅C 
SW B

From the formula it is recognized that the ESR has a big influence in the total ripple at
the output, so ceramic types or low ESR tantalum capacitors are recommended for the
application.
One other important thing to note are the requirements for the resonant frequency of the
output LC-combination. The choice of the components L and C have to meet also the
specified range given in section 3.3 otherwise instabilities of the regulation loop might
occur.

5.2.3 Input capacitor (CI2) selection:

At high load currents, where the current through the inductance flows continuously, the
input capacitor is exposed to a square wave current with its duty cycle VOUT/VI. To
prevent a high ripple to the battery line a capacitor with low ESR should be used. The
maximum RMS current which the capacitor has to withstand is calculated to:

V OUT ∆I 2
⋅ 1 + --- ⋅  -----------------------
1
IRMS = I LOAD ⋅ --------------
V IN 3  2 ⋅ I LOAD

5.2.4 Freewheeling diode / catch diode (DB)

For lowest power loss in the freewheeling path Schottky diodes are recommended. With
those types the reverse recovery charge is negligible and a fast handover from
freewheeling to forward conduction mode is possible. Depending on the application (12V
battery systems) 40V types could be also used instead of the 60V diodes.
A fast recovery diode with recovery times in the range of 30ns can be also used if smaller
junction capacitance values (smaller spikes) are desired, the slew resistor should be set
in this case between 10 and 20kΩ.

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TLE 6361 G

5.2.5 Bootstrap capacitor (CBTP)

The voltage at the Bootstrap capacitor does not exceed 15V, a ceramic type with a
minimum of 2% of the buck output capacitance and voltage class 16V would be
sufficient.

5.2.6 External charge pump capacitors (CFLY, CCCP)

Out of the feedback voltage the charge pump generates a voltage between 8 and 10V.
The fly capacitor connected between C+ and C- is charged with the feedback voltage
level and discharged to achieve the (almost) double voltage level at CCP. CFLY is chosen
to 100nF and CCCP to 220nF, both ceramic types.
The connection of CCP to a voltage source of e.g. 7V (take care of the maximum
ratings!) via a diode improves the start-up behavior at very low battery voltage. The diode
with the cathode on CCP has to be used in order to avoid any influence of the voltage
source to the device’s operation and vice versa.

5.2.7 Input filter components for reduced EME (CI1, CI2, CI3, LI, RSlew)
At the input of Buck converters a square wave current is observed causing
electromagnetical interference on the battery line. The emission to the battery line
consists on one hand of components of the switching frequency (fundamental wave) and
its harmonics and on the other hand of the high frequency components derived from the
current slope. For proper attenuation of those interferers a π-type input filter structure is
recommended which is built up with inductive (LI) and capacitive components (CI1, CI2,
CI3). The inductance can be chosen up to the value of the Buck converter inductance,
higher values might not be necessary, CI1 and CI3 should be ceramic types and for CI2 an
input capacitance with very low ESR should be chosen and placed as close to the input
of the Buck converter as possible.
Inexpensive input filters show due to their parasitrics a notch filter characteristic, which
means basically that the lowpass filter acts from a certain frequency as a highpass filter
and means further that the high frequency components are not attenuated properly. For
that reason the TLE 6361 G offers the possibility of current slope adjustment. The current
transistion time can be set by the external slew resistor to times between 20ns and 80ns
by varying the resistor value bewteen 0Ω (fastest transition) and 20kΩ (slowest
transistion).

5.2.8 Feedback circuit for minimum switching loss (RBoost, CBoost, DBoost)
To decrease the switching losses to a mininum the external components RBoost, CBoost
and DBoost are needed. The current through the feedback resistor RBoost is about a few
mA where the Diode DBoost and the capacitor CBoost run a part of the load current.
If this feature is not needed the three components are not needed and the Boost pin (33)
can be connected directly to the IN pins(32, 30).

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TLE 6361 G

5.3 Reverse polarity protection

The Buck converter is due to the parasitic source drain diode of the DMOS not reverse
polarity protected. Therefore, as an example, the reverse polarity diode is shown in the
application circuit, in general the reverse polarity protection can be done in different
ways.

5.4 Linear voltage regulators (CLDO1, 2, 3)

As indicated before the linear regulators show stable operation with a minimum of 470nF
ceramic capacitors. To avoid a high ripple at the output due to load steps this output cap
might have to be increased to some few µF capacitors.

5.5 Linear voltage trackers (CT1,2,3,4,5,6)

The voltage trackers require at their outputs 1µF ceramic capacitors each to avoid some
oscillation at the output. If needed the tracker outputs can be connected in parallel, in
that the output capacitor increases linear according to the number of parallel outputs.

5.6 Reset outputs (R1,2,3)

The undervoltage/watchdog reset outputs are open drain structures and require external
pull up resistors in the range of 10kΩ to the µC I/O voltage rail.

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TLE 6361 G

5.7 Components recommendation - overview

Device Type Supplier Remark

LI B82479 series EPCOS 10-1000µH; 4.3-0.56A
B82464-A4 series EPCOS 1-1000µH; 6.8-0.3A
DO3340P series Coilcraft 10-1000µH; 8.0-0.8A
DO5022P series Coilcraft 1-1000µH; 20.0-1.0A
DS5022P series Coilcraft 10-1000µH; 8.0-0.8A
SLF1275T-330M3R2 TDK 33µH, 3.2A
CI1 Ceramic various 100nF, 60V
CI2 Low ESR tantalum various 47µF, 60V
CI3 Ceramic various 10nF to 100nF, 60V
DBoost S3B various
LB B82479 series EPCOS 10-1000µH; 4.3-0.56A
B82464-A4 series EPCOS 1-1000µH; 6.8-0.3A
DO3340P series Coilcraft 10-1000µH; 8.0-0.8A
DO5022P series Coilcraft 1-1000µH; 20.0-1.0A
DS5022P series Coilcraft 10-1000µH; 8.0-0.8A
CBTP Ceramic various 100nF, 10V
DB MBRD360 Motorola Schottky, 60V, 3A
MBRD340 Motorola Schottky, 40V, 3A
SS34 various Schottky, 40V, 3A
CB B45197-A2226 EPCOS Low ESR Tantalum, 22µF, 10V,
C-case
2 * LMK316BJ475ML Taiyo Yuden Ceramic X7R, 4.7µF, 10V
C3216X7R1C106M TDK Ceramic X7R, 10µF, 16V
TPSC476K010R350 AVX Low ESR Tantalum, 47µF, 10V,
C-case
CLDOx Ceramic various 470nF, 10V
CTx Ceramic various 1µF, 60V

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TLE 6361 G

5.8 Layout recommendation

The most sensitive points for Buck converters - when considering the layout - are the
nodes at the input and the output of the Buck switch, the DMOS transistor.
For proper operation the external catch diode and Buck inductance have to be
connected as close as possible to the SW pins (29, 31). Best suitable for the connection
of the cathode of the Schottky diode and one terminal of the inductance would be a small
plain located next to the SW pins.
The GND connection of the catch diode must be also as short as possible. In general the
GND level should be implemented as surface area over the whole PCB as second layer,
if necessary as third layer.
The pin FB/L_IN is sensitive to noise. With an appropriate layout the Buck output
capacitor helps to avoid noise coupling to this pin. Also filtering of steep edges at the
supply voltage pin e.g. as shown in the application diagram is mandatory. CI2 may either
be a low ESR Tantalum capacitor or a ceramic capacitor. A minimum capacitance of
10µF is recommended for CI2.
To obtain the optimum filter capability of the input π-filter it has to be located also as
close as possible to the IN pins, at least the ceramic capacitor CI3 should be next to those
pins.

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TLE 6361 G

Package Outlines
P-DSO-36-12
SMD = Surface Mounted Device
Dimensions in mm

11 ±0.15 1)

3.5 MAX.
B
3.25 ±0.1

+0.07
2.8

-0.02
1.1 ±0.1
0 +0.1

0.25

5˚ ±3˚
15.74 ±0.1 1.3 6.3
0.65 (Heatslug) Heatslug
0.1 C (Mold)
36x 0.95 ±0.15
0.25 +0.13
0.25 M A B C 14.2 ±0.3
0.25 B

Bottom View

(Metal)

(Metal)
5.9 ±0.1
36 19 19 36 3.2 ±0.1

Index Marking

1 18 1 Heatslug
10
1 x 45˚ 13.7 -0.2
15.9 ±0.1 1) (Metal)
A
(Mold)
1)
Does not include plastic or metal protrusion of 0.15 max. per side

see also: http://www.infineon.com -> Products -> Packages

Data Sheet, Rev. 1.31 56 2004-10-12

www.DataSheet4U.com
TLE 6361 G

Published by Infineon Technologies AG ,

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D-81541 München
© Infineon Technologies AG 2003
All Rights Reserved.

Attention please!
The information herein is given to describe certain components and shall not be considered as warranted char-
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Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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For further information on technology, delivery terms and conditions and prices please contact your nearest In-
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Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the fail-
ure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life sup-
port devices or systems are intended to be implanted in the human body, or to support and/or maintain and sus-
tain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons
may be endangered.

Data Sheet, Rev. 1.31 57 2004-10-12