TS30041/42

High Efficiency 1A/2A Current-Mode

Synchronous Buck Converter, 1MHz

TRIUNE PRODUCTS

Features Description
• Fixed output voltage choices: 1.5V, 1.8V, 2.5V, 3.3V, and 5V The TS30041 (1A) and TS30042 (2A) are DC/DC synchronous
with +/- 2% output tolerance
switching regulators with fully integrated power switches,
• Adjustable version output voltage range: 0.9V to (VCC - internal compensation, and full fault protection. The switching
1V) with +/- 1.5% reference
frequency of 1MHz enables the use of small filter components
• Wide input voltage range: 4.5V to 40V (42V Abs Max) resulting in minimal board space and reduced BOM costs.
• 1MHz +/- 10% fixed switching frequency
• Continuous output current: 1A (TS30041), 2A (TS30042) The TS30041/42 utilizes current mode feedback in normal
• High efficiency up to 95% regulation PWM mode. When the regulator is placed in
standby (EN is low), the device draws less than 10uA quiescent
• Current mode PWM control with PFM mode for improved
light load efficiency current.

• Voltage supervisor for VOUT reported at the Power Good

(PG) pin The TS30041/42 integrates a wide range of protection circuitry
including input supply under-voltage lockout, output voltage
• Input supply under voltage lockout
soft start, current limit, and thermal shutdown.
• Soft start for controlled startup with no overshoot
• Full protection for over-current, over-temperature, and The TS30041/42 includes supervisory reporting through
VOUT over-voltage the PG (Power Good) open drain output to interface other
• SYNC function on EN/SYNC pin to control switching fre- components in the system.
quency
• Less than 10uA in standby mode
• Low external component count Summary Specification
• Junction operating temperature -40 °C to 125 °C
Applications • Packaged in a 16pin QFN (3x3)
• On-card switching regulators • ROHS: “Product is lead-free, Halogen Free, RoHS/WEEE
compliant”
• Set-top box, DVD, LCD, LED supply
• Industrial power supplies
Typical Application Circuit

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Final Datasheet Rev 2.2
July 27, 2016
Pin Configuration

Figure 1: 16 Lead 3x3 QFN, Top View

Pin Description

Pin # Pin Symbol Function Description

1 VSW Switching Voltage Node Connected to 4.7uH (typical) inductor

2 VCC Input Voltage Input voltage

3 VCC Input Voltage Input voltage

4 GND GND Primary ground for the majority of the device except the low-side power FET
Regulator FB Voltage. Connects to VOUT for fixed mode and the output
5 FB Feedback Input
resistor divider for adjustable mode
6 NC No Connect Not Connected

7 NC No Connect Not Connected

8 PG Power Good Output Open-drain output

Above 2.2V the device is enabled. GND the pin to put device in standby
9 EN/SYNC Enable & Sync Input
mode. Includes internal pull-up. Also used for SYNC function
Bootstrap capacitor for the high-side FET gate driver. A ceramic capacitor in
10 BST Bootstrap Capacitor
the range 15 nF - 200 nF from BST pin to VSW pin
11 VCC Input Voltage Input Voltage

12 VSW Switching Voltage Node Connected to 4.7uH (typical) inductor

13 VSW Switching Voltage Node Connected to 4.7uH (typical) inductor

14 PGND Power GND GND supply for internal low-side FET/integrated diode

15 PGND Power GND GND supply for internal low-side FET/integrated diode

16 VSW Switching Voltage Node Connected to 4.7uH (typical) inductor

17 PAD Power PAD Power GND

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Functional Block Diagrams

Figure 2: TS30041/42 Block Diagram

Figure 3: Monitor & Control Logic Functionality

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Absolute Maximum Ratings
Over operating free–air temperature range unless otherwise noted(1,2,3)

Parameter Value Unit

VCC -0.3 to 42 V
BST -0.3 to (VCC+6) V
VSW -1 to 42 V
EN, PG,FB -0.3 to 6 V
Electrostatic Discharge – Human Body Model +/-2k V
Electrostatic Discharge – Charge Device Model +/-500 V
O
Lead Temperature (soldering, 10 seconds) 260 C
Note 1: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
Note 2: All voltage values are with respect to network ground terminal.
Note 3: MOSFETs minimum breakdown voltage is 48V.

Thermal Characteristics
Over operating free–air temperature range unless otherwise noted(1,2)

Symbol Parameter Value Unit

θJA Thermal Resistance Junction to Air (Note 1) 34.5 °C/W
θJC Thermal Resistance Junction to Case (Note 1) 2.5 °C/W
TSTG Storage Temperature Range -65 to 150 °C
TJ MAX Maximum Junction Temperature 150 °C
TJ Operating Junction Temperature Range -40 to 125 °C
Note 1: Assumes 16LD 3x3 QFN with hi-K JEDEC board and 13.5 inch2 of 1 oz Cu and 4 thermal vias connected to PAD.

Recommended Operating Conditions

Symbol Parameter Min Typ Max Units

VCC Input Operating Voltage 4.5 12 40 V

CBST Bootstrap Capacitor 15 22 200 nF

LOUT Output Filter Inductor Typical Value (Note 1) 3.76 4.7 5.64 uH

COUT Output Filter Capacitor Typical Value (Note 2) 33 44 (2 x 22) uF

COUT-ESR Output Filter Capacitor ESR 2 100 mΩ

CBYPASS Input Supply Bypass Capacitor Typical Value (Note 3) 8 10 uF

Note 1: For best performance, an inductor with a saturation current rating higher than the maximum VOUT load requirement plus the inductor current ripple.
Note 2: For best performance, a low ESR ceramic capacitor should be used.
Note 3: For best performance, a low ESR ceramic capacitor should be used. If CBYPASS is not a low ESR ceramic capacitor, a 0.1uF ceramic capacitor should
be added in parallel to CBYPASS

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Final Datasheet Rev 2.2
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Electrical Characteristics
Electrical Characteristics, TJ = -40C to 125C, VCC = 12V (unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

VCC Supply Voltage

Input Supply Voltage VCC 4.5 40 V

Quiescent current Normal Mode ICC-NORM VCC = 12V, ILOAD = 0A 3.6 mA

Quiescent current Normal Mode VCC=12V, ILOAD=0A,

ICC-NOSWITCH 2.5 mA
– Non-switching Non-switching
Quiescent current Standby Mode ICC-STBY VCC = 12V, EN = 0V 5 10 uA

VCC Under Voltage Lockout

Input Supply Under Voltage Threshold VCC-UV VCC Increasing 4.3 4.5 V
Input Supply Under Voltage Threshold VCC-UV_HYST 350 mV
Hysteresis

OSC

Oscillator Frequency (Internal) fOSC 0.9 1 1.1 MHz

SYNC Frequency (1) fSYNC 0.3 2.2 MHz

PG Open Drain Output

PG Release Timer tPG 10 ms

High-Level Output Leakage IOH-PG VPG = 5V 0.5 uA
Low-Level Output Voltage VOL-PG IPG = -0.3mA 0.01 V

EN/Sync Input Voltage Thresholds

High Level Input Voltage VIH-EN 2.2 V

Low Level Input Voltage VIL-EN 0.8 V
Input Hysteresis VHYST-EN 480 mV
VEN=5V 3.5 uA
Input Leakage IIN-EN
VEN=0V -1.5 uA

Thermal Shutdown

Thermal Shutdown Junction Temperature TSD Note: not tested in production 150 170 °C

TSD Hysteresis TSDHYST Note: not tested in production 10 °C

Note 1: SYNC frequency range is tested with a square wave. Operation with a 200ns minimum high pulse is required.

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Regulator Characteristics
Electrical Characteristics, TJ = -40C to 125C (unless otherwise noted)

Parameter Symbol Condition Min Type Max Units

Switch Mode Regulator: L=4.7uH and C=2 x 22uF

Output Voltage Tolerance in

VOUT-PWM ILOAD =1A VOUT – 2% VOUT VOUT + 2% V
PWM Mode
Output Voltage Tolerance in
VOUT-PFM ILOAD = 0A VOUT – 1% VOUT + 1% VOUT + 3.5% V
PFM Mode
High Side Switch On Resistance IVSW = -1A (Note 1) 180 mΩ
RDSON
Low Side Switch On Resistance IVSW = 1A (Note 1) 120 mΩ
TS30042 (Note 4) 2 A
Output Current IOUT
TS30041 (Note 4) 1 A

Over Current Detect TS30042 2.4 2.8 3.4 A

IOCD
(High Side Switch Current) TS30041 1.4 1.8 2.4 A
Feedback Reference
FBTH (Note 3) 0.886 0.9 0.914 V
(Adjustable Mode)
Feedback Reference Tolerance FBTH-TOL (Note 3) -1.5 1.5 %
Soft start Ramp Time TSS Guaranteeed by Design 4 ms
PFM Mode FB Comparator
Threshold FBTH-PFM VOUT + 1% V

VOUT Under Voltage Threshold VOUT-UV 91% VOUT 93% VOUT 95% VOUT
VOUT Under Voltage Hysteresis VOUT-UV_HYST 1.5% VOUT
VOUT Over Voltage Threshold VOUT-OV 103% VOUT
VOUT Over Voltage Hysteresis VOUT-OV_HYST 1% VOUT
Max Duty Cycle DUTYMAX (Note 2) 95% 97% 99%
Minimum On Time T0N-MIN Not tested in production 100 ns
Note 1: RDSON is characterized at 1A and tested at lower current in production.
Note 2: Regulator VSW pin is forced off for 240ns every 16 cycles to ensure the BST cap is replenished.
Note 3: For the adjustable version, the ratio of VCC/Vout cannot exceed 16.
Note 4: Based on Over Current Detect testing

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Typical Performance Characteristics
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)

Figure 4. Startup Response Figure 5. 100mA to 1A Load Step (VCC=12V, VOUT=3.3V)

VOUT
VOUT 100mV/div
5V/div

EN
IOUT
1V/div
500mA/div

5ms/div 100us/div

Figure 6. 100mA to 2A Load (VCC=12V, VOUT=3.3V) Figure 7. 100mA to 1A Load Step (VCC=12V, VOUT=1.8V)

VOUT VOUT
100mV/div 100mV/div

IOUT IOUT
1A/div 500mA/div

100us/div 100us/div

Figure 8. 100mA to 2A Load Step (VCC=12V, VOUT=1.8V) Figure 9. Line Transient Response (VCC=12V, VOUT=3.3V)

VIN
VOUT 5V/div
100mV/div

VOUT
0.5V/div
IOUT
1A/div

100us/div 10ms/div

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Final Datasheet Rev 2.2
Typical Performance Characteristics continued
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)

Figure 10. Load Regulation Figure 11. Line Regulation (IOUT=1A)

Figure 12. Efficiency vs. Output Current ( VOUT = 3.3V) Figure 13. Efficiency vs. Output Current ( VOUT = 5V)

Figure 14. Efficiency vs. Output Current ( VOUT = 1.8V) Figure 15. Efficiency vs. Input Voltage (VOUT = 3.3V)

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Final Datasheet Rev 2.2
Typical Performance Characteristics continued
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)

Figure 16. Standby Current vs. Input Voltage Figure 17. Standby Current vs. Temperature

Figure 18. Output Voltage vs. Temperature Figure 19. Oscillator Frequency vs. Temperature (IOUT=300mA)

Figure 20. Quiescent Current vs. Temperature (No load)

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Final Datasheet Rev 2.2
Functional Description Detailed Pin Description
The TS30041/42 current-mode synchronous step-down power Unregulated input, VCC
supply product is ideal for use in the commercial, industrial, This terminal is the unregulated input voltage source for the
and automotive market segments. It includes flexibility to be IC. It is recommended that a 10uF bypass capacitor be placed
used for a wide range of output voltages and is optimized for close to the device for best performance. Since this is the main
high efficiency power conversion with low RDSON integrated supply for the IC, good layout practices need to be followed for
synchronous switches. A 1MHz internal switching frequency this connection.
facilitates low cost LC filter combinations. Additionally, the
fixed output versions enable a minimum external component Bootstrap control, BST
count to provide a complete regulation solution with only 4 This terminal will provide the bootstrap voltage required for
external components: an input bypass capacitor, an inductor, the upper internal NMOS switch of the buck regulator. An
an output capacitor, and the bootstrap capacitor. The regulator external ceramic capacitor placed between the BST input
automatically transitions between PFM and PWM mode to terminal and the VSW pin will provide the necessary voltage
maximize efficiency for the load demand. for the upper switch. In normal operation the capacitor is
The TS30041/42 was designed to provide these system re-charged on every low side synchronous switching action.
benefits: In the case of where the switch mode approaches 100% duty
• Reduced board real estate cycle for the high side FET, the device will automatically reduce
the duty cycle switch to a minimum off time on every 16th
• Lower system cost
cycle to allow this capacitor to re-charge.
s Lower cost inductor
s Low external parts count Sense feedback, FB
• Ease of design This is the input terminal for the output voltage feedback.
s Bill of Materials and suggested board layout provided
s Power Good output For the fixed mode versions, this should be hooked directly
s Integrated compensation network to VOUT. The connection on the PCB should be kept as short
s Wide input voltage range as possible, and should be made as close as possible to the
• Robust solution capacitor. The trace should not be shared with any other
s Over current, over voltage and over temperature connection. (Figure 22)
protection
For adjustable mode versions, this should be connected to
the external resistor divider. To choose the resistors, use the
following equation:
VOUT = 0.9 (1 + RTOP/RBOT )

The input to the FB pin is high impedance, and input current

should be less than 100nA. As a result, good layout practices
are required for the feedback resistors and feedback traces.
When using the adjustable version, the feedback trace should
be kept as short as possible and minimum width to reduce
stray capacitance and to reduce the injection of noise.

For the adjustable version, the ratio of VCC/Vout cannot

exceed 16.

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Final Datasheet Rev 2.2
Switching output, VSW Under extended over current conditions (such as a short),
This is the switching node of the regulator. It should be the device will automatically disable. Once the over current
connected directly to the 4.7uH inductor with a wide, short condition is removed, the device returns to normal opera-
trace and to one end of the Bootstrap capacitor. It is switching tion automatically. (Alternately the factory can configure the
between VCC and PGND at the switching frequency. device’s NVM to shutdown the regulator if an extended over
current event is detected and require a toggle of the Enable
Ground, GND
pin to return the device to normal operation.)
This ground is used for the majority of the device including the
analog reference, control loop, and other circuits. Thermal Shutdown
If the temperature of the die exceeds 170°C (typical), the VSW
Power Ground, PGND
outputs will tri-state to protect the device from damage. The
This is a separate ground connection used for the low side
PG and all other protection circuitry will stay active to inform
synchronous switch to isolate switching noise from the rest of
the system of the failure mode. Once the device cools to 160°C
the device. (Figure 22)
(typical), the device will start up again, following the normal
Enable/Synchronize, high-voltage, EN/SYNC soft start sequence. If the device reaches 170°C, the shutdown/
This is the input terminal to activate the regulator. The input restart sequence will repeat.
threshold is TTL/CMOS compatible. It also has an internal pull-
up to ensure a stable state if the pin is disconnected. Reference Soft Start
After a sequence of three rising edge pulses having a The reference in this device is ramped at a rate of 4ms to
frequency greater than or equal to FSync-Min, the switcher prevent the output from overshoot during startup. This ramp
synchronizes to the frequency of the signal provided on the restarts whenever there is a rising edge sensed on the Enable
EN/SYNC pin. SYNC frequency range is tested with a square pin. This occurs in both the fixed and adjustable versions.
wave and a high pulse of minimum 200ns duration is required During the soft start ramp, current limit is still active, and will
for proper operation. For highier frequencies of operation a still protect the device in case of a short on the output.
2.2uH inductor and for lower frequencies of operation a 10uH Output Overvoltage
inductor is recommended. If the output of the regulator exceeds 103% of the regulation
Power Good Output, PG voltage, the VSW outputs will tri-state to protect the device
This is an open drain, active low output. The switched mode from damage. This check occurs at the start of each switching
output voltage is monitored and the PG line will remain low cycle. If it occurs during the middle of a cycle, the switching
until the output voltage reaches the VOUT-UV threshold. for that cycle will complete, and the VSW outputs will tri-state
Once the internal comparator detects the output voltage at the beginning of the next cycle.
is above the desired threshold, an internal delay timer is VCC Under-Voltage Lockout
activated and the PG line is de-asserted to high once this The device is held in the off state until VCC reaches 4.3V
delay timer expires. In the event the output voltage decreases (typical). There is a 350mV hysteresis on this input, which
below VOUT-UV, the PG line will be asserted low and remain requires the input to fall below 4.0V (typical) before the device
low until the output rises above VOUT-UV and the delay timer will disable.
times out. See Figure 3 for the circuit schematic for the PG
signal.
Transient Response
Internal Protection Details
TS30041/42 has been designed to work under a wide range
Internal Current Limit of input and output voltages, supporting different values and
The current through the high side FET is sensed on a cycle types of output capacitance. By design, TS30041/42 adjustable
by cycle basis and if current limit is reached, it will abbreviate output version has lower bandwidth than fixed version. For
the cycle. In addition, the device senses the FB pin to identify adjustable output version designs, with a high slew rate load
hard short conditions and will direct the VSW output to skip 4 requirement using a 10nF feed-forward capacitor in parallel
cycles if current limit occurs when FB is low. This allows current with the RTOP feedback resistor is recommended.
built up in the inductor during the minimum on time to decay
sufficiently. Current limit is always active when the regulator
is enabled. Soft start ensures current limit does not prevent
regulator startup.

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Final Datasheet Rev 2.2
Typical Application Schematic

Figure 21: TS30041/42 Application Schematic

A minimal schematic suitable for most applications is shown on page 1. Figure 21 includes optional components that may be
considered to address specific issues as listed in the External Component Selection section.

PCB Layout
For proper operation and minimum EMI, care must be taken during PCB layout. An improper layout can lead to issues such as poor
stability and regulation, noise sensitivity and increased EMI radiation. (Figure 22) The main guidelines are the following:
• provide low inductive and resistive paths for loops with high di/dt,
• provide low capacitive paths with respect to all the other nodes for traces with high di/dt,
• sensitive nodes not assigned to power transmission should be referenced to the analog signal ground (GND) and be
always separated from the power ground (PGND).

The negative ends of CBYPASS, COUT and the Schottky diode DCATCH (optional) should be placed close to each other and
connected using a wide trace. Vias must be used to connect the PGND node to the ground plane. The PGND node must be placed
as close as possible to the TS30041/42 PGND pins to avoid additional voltage drop in traces.

The bypass capacitor CBYPASS (optionally paralleled to a 0.1µF capacitor) must be placed close to the VCC pins of TS30041/42.

The inductor must be placed close to the VSW pins and connected directly to COUT in order to minimize the area between the
VSW pin, the inductor, the COUT capacitor and the PGND pins. The trace area and length of the switching nodes VSW and BST
should be minimized.

For the adjustable output voltage version of the TS30041/42, feedback resistors RBOT and RTOP are required for Vout settings
greater than 0.9V and should be placed close to the TS30041/42 in order to keep the traces of the sensitive node FB as short as
possible and away from switching signals. RBOT should be connected to the analog ground pin (GND) directly and should never
be connected to the ground plane. The analog ground trace (GND) should be connected in only one point to the power ground
(PGND). A good connection point is under the TS30041/42 package to the exposed thermal pad and vias which are connected to
PGND. RTOP will be connected to the VOUT node using a trace that ends close to the actual load.

For fixed output voltage versions of the TS30041/42, RBOT and RTOP are not required and the FB pin should be connected directly to
the Vout.

The exposed thermal pad must be soldered to the PCB for mechanical reliability and to achieve good power dissipation. Vias must
be placed under the pad to transfer the heat to the ground plane.

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Final Datasheet Rev 2.2
 Figure 22: TS30041/42 PCB Layout, Top View

External Component Bill of Material

Suggested
Designator Function Description Manufacturer Code Qty
Manufacturer
CBYPASS Input Supply Bypass Capacitor 10uF 10% 50V 1

COUT TDK C2012X5R1A226K125AB

Output Filter Capacitor 22uF 10% 10V 2
Wurth 885 012 208 019
SLF7045T-4R7M2R0-PF
LOUT Output Filter Inductor (1A) 4.7uH 2A TDK
7447745047
TDK VLC5045T-4R7M
LOUT Output Filter Inductor (2A) 4.7uH 3A
Wurth 744774047
1

CBST TDK C1005X7R1C223K

Boost Capacitor 22nF 10V 1
Wurth 885 012 205 033
Voltage Feedback Resistor
RTOP 17.8K (Note 1) 1
(optional)
Voltage Feedback Resistor
RBOT 10K (Note 1) 1
(optional)
RPLP PG Pin Pull-up Resistor (optional) 10K 1

30V 2A On
DCATCH Catch Diode (optional, 1A) MBR230LSFT1G 1
SOD-123FL Semiconductor
40V 3A NXP
DCATCH Catch Diode (optional, 2A) PMEG4030ER,115 1
SOD-123 Semiconductors
Note 1: The voltage divider resistor values are calculated for an output voltage of 2.5V. For fixed output versions, the FB pin is connected directly to VOUT
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Final Datasheet Rev 2.2
External Component Selection
The 1MHz internal switching frequency of the TS30041/42 facilitates low cost LC filter combinations. Additionally, the fixed
output versions enable a minimum external component count to provide a complete regulation solution with only 4 external
components: an input bypass capacitor, an inductor, an output capacitor, and the bootstrap capacitor. The internal compensation
is optimized for a 44uF output capacitor and a 4.7uH inductor.
For best performance, a low ESR ceramic capacitor should be used for CBYPASS. If CBYPASS is not a low ESR ceramic capacitor, a
0.1uF ceramic capacitor should be added in parallel to CBYPASS.
The minimum allowable value for the output capacitor is 33uF. To keep the output ripple low, a low ESR (less than 35mOhm)
ceramic is recommended. Multiple capacitors can be paralleled to reduce the ESR.
The inductor range is 4.7uH +/-20%. For optimal over-current protection, the inductor should be able to handle up to the
regulator current limit without saturation. Otherwise, an inductor with a saturation current rating higher than the maximum IOUT
load requirement plus the inductor current ripple should be used.
For high current modes, the optional Schottky diode will improve the overall efficiency and reduce the heat. It is up to the user to
determine the cost/benefit of adding this additional component in the user’s application. The diode is typically not needed.
For the adjustable output version of the TS30041/42, the output voltage can be adjusted by sizing RTOP and RBOT feedback
resistors. The equation for the output voltage is

For the adjustable version, the ratio of VCC/Vout cannot exceed 16.
RPUP is only required when the Power Good signal (PG) is utilized.

Thermal Information
TS30041/42 is designed for a maximum operating junction temperature Tj of 125°C. The maximum output power is limited by
the power losses that can be dissipated over the thermal resistance given by the package and the PCB structures. The PCB must
provide heat sinking to keep the TS30041/42 cool. The exposed metal on the bottom of the QFN package must be soldered to a
ground plane. This ground should be tied to other copper layers below with thermal vias. Adding more copper to the top and the
bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. For a hi-K JEDEC board
and 13.5 square inch of 1 oz Cu, the thermal resistance from junction to ambient can be reduced to θJA = 34.5°C/W. The power
dissipation of other power components (catch diode, inductor) cause additional copper heating and can further increase what the
TS30041/42 sees as ambient temperature.

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Package Mechanical Drawings (all dimensions in mm)

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Recommended PCB Land Pattern

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Marking and Ordering Information

Tape & Reel (3300 parts/reel)

Tape & Reel (3300 parts/reel)

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Final Datasheet Rev 2.2
IMPORTANT NOTICE

Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right
to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders
and should verify that such information is current and complete. Semtech warrants performance of its products to the specifications applicable at the time
of sale, and all sales are made in accordance with Semtech’s standard terms and conditions of sale.

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names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products described in this document
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© Semtech 2016

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Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com

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Final Datasheet Rev 2.2
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