SN54HC14, SN74HC14

SCLS085L – DECEMBER 1982 – REVISED FEBRUARY 2025

SNx4HC14 Hex Inverters with Schmitt-Trigger Inputs

1 Features 3 Description
• Buffered inputs This device contains six independent inverters
• Wide operating voltage range: 2V to 6V with Schmitt-trigger inputs. Each gate performs the
• Wide operating temperature range: -40°C to +85°C Boolean function Y = A in positive logic.
• Supports fanout up to 10 LSTTL loads
Device Information
• Significant power reduction compared to LSTTL PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
logic ICs D (SOIC, 14) 8.65mm × 6mm 8.65mm × 3.9mm

2 Applications DB (SSOP, 14) 6.2 mm × 7.8mm 6.2mm × 5.30mm

SN74AHC14 N (PDIP, 14) 19.3mm × 9.4mm 19.3mm × 6.35mm
• Synchronize inverted clock inputs NS (SOP, 14) 10.2mm x 7.8mm 10.3mm x 5.3mm
• Debounce a switch PW (TSSOP, 14) 5mm × 6.4mm 5mm × 4.4mm
• Invert a digital signal J (CDIP, 14) 19.56mm × 7.9mm 19.56mm × 6.67mm
SN54AHC14 W (CFP, 14) 9.21mm x 9mm 9.21mm × 6.3mm
FK (LCCC, 20) 8.9mm × 8.9mm 8.9mm × 8.9mm

(1) For more information, see Section 11.

(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
not include pins.

1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
4 11
2Y 5A
3A 5 10 5Y
3Y 6 9 4A
7 8
GND 4Y

Functional pinout

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram........................................... 9
2 Applications..................................................................... 1 7.3 Feature Description.....................................................9
3 Description.......................................................................1 7.4 Device Functional Modes..........................................10
4 Pin Configuration and Functions...................................3 8 Application and Implementation.................................. 11
5 Specifications.................................................................. 4 8.1 Application Information..............................................11
5.1 Absolute Maximum Ratings........................................ 4 8.2 Typical Application.................................................... 11
5.2 ESD Ratings............................................................... 4 8.3 Power Supply Recommendations.............................13
5.3 Recommended Operating Conditions.........................4 8.4 Layout....................................................................... 13
5.4 Thermal Information....................................................4 9 Device and Documentation Support............................14
5.5 Electrical Characteristics - 74..................................... 5 9.1 Documentation Support............................................ 14
5.6 Electrical Characteristics - 54..................................... 5 9.2 Support Resources................................................... 14
5.7 Switching Characteristics - 74.....................................6 9.3 Trademarks............................................................... 14
5.8 Switching Characteristics - 54.....................................7 9.4 Electrostatic Discharge Caution................................14
5.9 Operating Characteristics........................................... 7 9.5 Glossary....................................................................14
5.10 Typical Characteristics.............................................. 7 10 Revision History.......................................................... 14
6 Parameter Measurement Information............................ 8 11 Mechanical, Packaging, and Orderable
7 Detailed Description........................................................9 Information.................................................................... 14
7.1 Overview..................................................................... 9

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4 Pin Configuration and Functions

1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y

Figure 4-1. D, DB, N, NS, PW, J, or W Package 14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP Top
View
1Y 1A NC VCC 6A

3 2 1 20 19
2A 4 18 6Y
NC 5 17 NC
2Y 6 16 5A
NC 7 15 NC
3A 8 14 5Y
9 10 11 12 13

3Y GND NC 4Y 4A

Figure 4-2. FK Package 20-Pin LCCC Top View

Pin Functions
PIN
D, DB, N, I/O DESCRIPTION
NAME NS, PW, J, FK
or W
1A 1 2 Input Channel 1, Input A
1Y 2 3 Output Channel 1, Output Y
2A 3 4 Input Channel 2, Input A
2Y 4 6 Output Channel 2, Output Y
3A 5 8 Input Channel 3, Input A
3Y 6 9 Output Channel 3, Output Y
GND 7 10 — Ground
4Y 8 12 Output Channel 4, Output Y
4A 9 13 Input Channel 4, Input A
5Y 10 14 Output Channel 5, Output Y
5A 11 16 Input Channel 5, Input A
6Y 12 18 Output Channel 6, Output Y
6A 13 19 Input Channel 6, Input A
VCC 14 20 — Positive Supply
1, 5, 7, 11, 15,
NC — Not internally connected
17

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Junction temperature(3) 150 °C
Tstg Storage temperature –60 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
5.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC
±1500
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
SN54HC14 –55 125
TA Operating free-air temperature °C
SN74HC14 –40 85

5.4 Thermal Information

SN74HC14
THERMAL METRIC(1) D (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Junction-to-ambient thermal
RθJA 133.6 114.8 60.7 122.6 151.7 °C/W
resistance
Rθ Junction-to-case (top) thermal
89 64.5 47.8 81.8 79.4 °C/W
JC(top) resistance
Junction-to-board thermal
RθJB 89.5 65.1 40.6 83.8 94.7 °C/W
resistance
Junction-to-top characterization
ΨJT 45.5 23.7 26.9 45.4 25.2 °C/W
parameter
Junction-to-board
ΨJB 89.1 64.4 40.5 83.4 94.1 °C/W
characterization parameter

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SN74HC14
THERMAL METRIC(1) D (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Rθ Junction-to-case (bottom)
N/A N/A N/A N/A N/A °C/W
JC(bot) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.5 Electrical Characteristics - 74
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C -40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 0.7 1.2 1.5 0.7 1.5
Positive
VT+ switching 4.5 V 1.55 2.5 3.13 1.55 3.13 V
threshold
6V 2.1 3.3 4.2 2.1 4.2
2V 0.3 0.6 1 0.3 1
Negative
VT- switching 4.5 V 0.9 1.6 2.45 0.9 2.45 V
threshold
6V 1.2 2 3.2 1.2 3.2
2V 0.2 0.6 1.2 0.2 1.2
Hysteresis (VT+ -
ΔVT 4.5 V 0.4 0.9 2.1 0.4 2.1 V
VT-)
6V 0.5 1.3 2.5 0.5 2.5
2V 1.9 1.998 1.9
IOH = –20 µA 4.5 V 4.4 4.499 4.4
High-level VI = VIH
VOH 6V 5.9 5.999 5.9 V
output voltage or VIL
IOH = –4 mA 4.5 V 3.98 4.3 3.84
IOH = –5.2 mA 6V 5.48 5.8 5.34
2V 0.002 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1
Low-level output VI = VIH
VOL 6V 0.001 0.1 0.1 V
voltage or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.33
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 µA
current
VI = VCC
ICC Supply current IO = 0 6V 2 20 µA
or 0
Input
Ci 5V 3 10 10 pF
capacitance

5.6 Electrical Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 0.7 1.2 1.5 0.7 1.5 0.7 1.5
Positive
VT+ switching 4.5 V 1.55 2.5 3.13 1.55 3.13 1.55 3.13 V
threshold
6V 2.1 3.3 4.2 2.1 4.2 2.1 4.2

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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 0.3 0.6 1 0.3 1 0.3 1
Negative
VT- switching 4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 V
threshold
6V 1.2 2 3.2 1.2 3.2 1.2 3.2
2V 0.2 0.6 1.2 0.2 1.2 0.2 1.2
Hysteresis (VT+ -
ΔVT 4.5 V 0.4 0.9 2.1 0.4 2.1 0.4 2.1 V
VT-)
6V 0.5 1.3 2.5 0.5 2.5 0.5 2.5
2V 1.9 1.998 1.9 1.9
IOH = –20
4.5 V 4.4 4.499 4.4 4.4
µA
6V 5.9 5.999 5.9 5.9
High-level VI = VIH or
VOH V
output voltage VIL IOH = –4
4.5 V 3.98 4.3 3.84 3.7
mA
IOH = –5.2
6V 5.48 5.8 5.34 5.2
mA
2V 0.002 0.1 0.1 0.1
IOL = 20
4.5 V 0.001 0.1 0.1 0.1
µA
Low-level output VI = VIH or 6V 0.001 0.1 0.1 0.1
VOL V
voltage VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.33 0.33
IOL = 5.2
6V 0.15 0.26 0.33 0.33
mA
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 ±1 µA
current
VI = VCC or
ICC Supply current IO = 0 6V 2 20 40 µA
0
Input 2 V to
Ci 3 10 10 10 pF
capacitance 6V

5.7 Switching Characteristics - 74

over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 55 125 155
tpd Propagation delay A Y 4.5 V 12 25 31 ns
6V 11 21 26
2V 38 75 95
tt Transition-time Y 4.5 V 8 15 19 ns
6V 6 13 16

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5.8 Switching Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 55 125 155 190
tpd Propagation delay A Y 4.5 V 12 25 31 38 ns
6V 11 21 26 22
2V 38 75 95 110
tt Transition-time Y 4.5 V 8 15 19 22 ns
6V 6 13 16 19

5.9 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 2 V to 6 V 20 pF
per gate

5.10 Typical Characteristics

TA = 25°C

7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)
Figure 5-1. Typical output voltage in the high state Figure 5-2. Typical output voltage in the low state
(VOH) (VOL)

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6 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.

Test VCC
90% 90%
Point
Input
10% 10%
0V
From Output tr(1) tf(1)
Under Test
VOH
CL(1) 90% 90%
Output
10% 10%
VOL
A. CL= 50 pF and includes probe and jig capacitance. tr(1) tf(1)

Figure 6-1. Load Circuit A. tt is the greater of tr and tf.

Figure 6-2. Voltage Waveforms Transition Times
VCC
Input 50% 50%
0V
tPLH(1) tPHL(1)
VOH
Output 50% 50%
VOL
tPHL(1) tPLH(1)
VOH
Output 50% 50%
VOL
A. The maximum between tPLH and tPHL is used for tpd.
Figure 6-3. Voltage Waveforms Propagation Delays

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7 Detailed Description
7.1 Overview
This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean
function Y = A in positive logic.
7.2 Functional Block Diagram

xA xY

7.3 Feature Description

7.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The SN74HC14 can drive a load with a total capacitance less than or equal to the maximum load listed in
the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the
provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between
the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
7.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground
in parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is
calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input
leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Cahracteristics -
74, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs slowly will also increase dynamic current consumption of the device. For additional information regarding
Schmitt-trigger inputs, please see Understanding Schmitt Triggers.

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7.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 7-1.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.

VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 7-1. Electrical Placement of Clamping Diodes for Each Input and Output

7.4 Device Functional Modes

Table 7-1. Function Table
INPUT OUTPUT
A Y
L H
H L

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

This device can be used to add an additional stage to a counter with an external flip-flop. Because counters
use a negative edge trigger, the flip-flop's clock input must be inverted to provide this function. This function
only requires one of the six available inverters in the device, so the remaining channels can be used for other
applications needing an inverted signal or improved signal integrity. Unused inputs must be terminated at VCC or
GND. Unused outputs can be left floating.
8.2 Typical Application
Counter 20
21
Clear CLR
22
Input 23

CLR Q 24

D-Typ e
Flip-Flop

D Q

Figure 8-1. Typical application schematic

8.2.1 Design Requirements

8.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC14 plus the maximum supply current, ICC, listed in the Electrical Characteristics - 74. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.

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8.2.1.2 Input Considerations

Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74HC14, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC14 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics - 74. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
8.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics - 74. Similarly,
the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics 74.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description for additional information regarding the outputs for this device.
8.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC14
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
8.2.3 Application Curves

23 Input ± 32 kHz
24 ± 1 kHz
23

24

Figure 8-2. Typical application timing diagram

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8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 8-3.
8.4 Layout
8.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
8.4.2 Layout Example
GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to
0.1 F the device

Unused input
1A 1 14 VCC Unused input
tied to GND
1Y 2 13 6A tied to VCC
Unused output
2A 3 12 6Y
left floating
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
Avoid 90°
corners for GND 7 8 4Y
signal lines

Figure 8-3. Example layout for the SN74HC14

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9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision K (June 2021) to Revision L (July 2024) Page

• Added package sizes to Device Information table..............................................................................................1
• Updated thermal values for N package from ΨJB = 40.3 to 40.5, all values in °C/W ....................................... 4

Changes from Revision J (October 2016) to Revision K (June 2021) Page

• Updated the numbering format for tables, figures and cross-references throughout the document.................. 1
• Updated to new data sheet standards................................................................................................................1
• Updated package sizing for DB package in Device Information table................................................................1
• Increased D (86 to 133.6), DB (96 to 114.8), NS (76 to 122.6), and PW (113 to 151.7); decreased N (80 to
60.7) °C/W.......................................................................................................................................................... 4

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

14 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: SN54HC14 SN74HC14

 PACKAGE OPTION ADDENDUM

www.ti.com 8-Jan-2025

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8409101VCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8409101VC Samples
& Green A
SNV54HC14J
5962-8409101VDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8409101VD Samples
& Green A
SNV54HC14W
84091012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84091012A Samples
& Green SNJ54HC
14FK
8409101CA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101CA Samples
& Green SNJ54HC14J
8409101DA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101DA Samples
& Green SNJ54HC14W
JM38510/65702BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65702BCA
JM38510/65702BDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65702BDA
M38510/65702BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65702BCA
M38510/65702BDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65702BDA
SN54HC14J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC14J Samples
& Green
SN74HC14D OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC14
SN74HC14DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14DRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14DT OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC14

SN74HC14N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC14N Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 8-Jan-2025

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HC14NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC14N Samples

SN74HC14NSR ACTIVE SOP NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14NSRE4 ACTIVE SOP NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14PW OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HC14

SN74HC14PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 Samples

SN74HC14PWT OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HC14

SNJ54HC14FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84091012A Samples
& Green SNJ54HC
14FK
SNJ54HC14J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101CA Samples
& Green SNJ54HC14J
SNJ54HC14W ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101DA Samples
& Green SNJ54HC14W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 8-Jan-2025

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC14, SN54HC14-SP, SN74HC14 :

• Catalog : SN74HC14, SN54HC14

• Automotive : SN74HC14-Q1, SN74HC14-Q1
• Military : SN54HC14
• Space : SN54HC14-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC14DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC14DRG3 SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC14DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC14NSR SOP NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC14NSR SOP NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC14PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC14DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74HC14DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC14DRG3 SOIC D 14 2500 366.0 364.0 50.0
SN74HC14DRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74HC14NSR SOP NS 14 2000 367.0 367.0 38.0
SN74HC14NSR SOP NS 14 2000 356.0 356.0 35.0
SN74HC14PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC14PWRG4 TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8409101VDA W CFP 14 25 506.98 26.16 6220 NA
84091012A FK LCCC 20 55 506.98 12.06 2030 NA
8409101DA W CFP 14 25 506.98 26.16 6220 NA
JM38510/65702BDA W CFP 14 25 506.98 26.16 6220 NA
M38510/65702BDA W CFP 14 25 506.98 26.16 6220 NA
SN74HC14N N PDIP 14 25 506 13.97 11230 4.32
SN74HC14N N PDIP 14 25 506 13.97 11230 4.32
SN74HC14NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC14NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ54HC14FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54HC14W W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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