SN54ACT04, SN74ACT04

SCAS518D – JULY 1995 – REVISED JANUARY 2023

SNx4ACT04 Hex Inverters

1 Features 3 Description
• VCC operation of 4.5 V to 5.5 V The ‘ACT04 devices contain six independent
• Inputs accept voltages to 5.5 V inverters. The devices perform the Boolean function
• Max tpd of 8.5 ns at 5 V Y = A.
• Inputs are TTL-voltage compatible
Package Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)

• Synchronize inverted clock inputs DB (SSOP, 14) 6.2 mm × 5.3 mm

• Debounce a switch D (SOIC, 14) 8.65 mm × 3.9 mm
SNx4ACT04
• Invert a digital signal NS (SO, 14) 10.3 mm × 5.3 mm
PW (TSSOP, 14) 5 mm × 4.4 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54ACT04, SN74ACT04
SCAS518D – JULY 1995 – REVISED JANUARY 2023 www.ti.com

Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagram........................................... 7
2 Applications..................................................................... 1 8.3 Feature Description.....................................................7
3 Description.......................................................................1 8.4 Device Functional Modes............................................7
4 Revision History.............................................................. 2 9 Application Information Disclaimer............................... 8
5 Pin Configuration and Functions...................................3 9.1 Power Supply Recommendations...............................9
6 Specifications.................................................................. 4 9.2 Layout......................................................................... 9
6.1 Absolute Maximum Ratings........................................ 4 10 Device and Documentation Support..........................10
6.2 ESD Ratings............................................................... 4 10.1 Documentation Support.......................................... 10
6.3 Recommended Operating Conditions.........................4 10.2 Receiving Notification of Documentation Updates..10
6.4 Thermal Information....................................................4 10.3 Support Resources................................................. 10
6.5 Electrical Characteristics.............................................5 10.4 Trademarks............................................................. 10
6.6 Switching Characteristics............................................5 10.5 Electrostatic Discharge Caution..............................10
6.7 Operating Characteristics........................................... 5 10.6 Glossary..................................................................10
7 Parameter Measurement Information............................ 6 11 Mechanical, Packaging, and Orderable
8 Detailed Description........................................................7 Information.................................................................... 10
8.1 Overview..................................................................... 7

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2003) to Revision D (January 2023) Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1

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5 Pin Configuration and Functions

Figure 5-1. SN54ACT04 J or W Package;

SN74ACT04 D, DB, N, NS, or PW Package Top View

Figure 5-2. SN54ACT04 FK Package Top View

PIN
D, DB, N,
I/O DESCRIPTION
NAME NS, PW, J, FK
or W
1A 1 2 Input Channel 1, Input A
1Y 2 3 Output Channel 1, Output Y
2A 3 4 Input Channel 2, Input A
2Y 4 6 Output Channel 2, Output Y
3A 5 8 Input Channel 3, Input A
3Y 6 9 Output Channel 3, Output Y
GND 7 10 — Ground
4Y 8 12 Output Channel 4, Output Y
4A 9 13 Input Channel 4, Input A
5Y 10 14 Output Channel 5, Output Y
5A 11 16 Input Channel 5, Input A
6Y 12 18 Output Channel 6, Output Y
6A 13 19 Input Channel 6, Input A
VCC 14 20 — Positive Supply
1, 5, 7, 11, 15,
NC — Not internally connected
17

Figure 5-3. Pin Functions

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
VI Input voltage range(1) –0.5 VCC + 0.5 V
VO Output voltage range(1) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 or VI > VCC ±20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±50 mA
Continuous current through VCC or GND ±200 mA
Tstg Storage temperature range –60 150 °C

(1) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±300
C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

SN54ACT04 SN74ACT04
UNIT
MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
IOH High-level output current –24 –24 mA
IOL Low-level output current 24 24 mA
∆t/∆v Input transition rise or fall rate 8 8 ns/V
TA Operating free-air temperature –55 125 –40 85 °C

6.4 Thermal Information

SNx4ACT04
D DB N NS PW
THERMAL METRIC(1) UNIT
(SOIC) (SSOP) (PDIP) (SOP) (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 86 96 80 76 113 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54ACT04 SN74ACT04
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
4.5 V 4.4 4.49 4.4 4.4
IOH = –50 µA
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
VOH IOH = –24 mA V
5.5 V 4.86 4.7 4.76
IOH = –50 mA(1) 5.5 V 3.85
IOH = –75 mA(1) 5.5 V 3.85
4.5 V 0.001 0.1 0.1 0.1
IOL = 50 µA
5.5 V 0.001 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
VOL IOL = 24 mA V
5.5 V 0.36 0.5 0.44
IOL = 50 mA(1) 5.5 V 1.65
IOL = 75 mA(1) 5.5 V 1.65
II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
ICC VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA
One input at 3.4 V,
∆ICC (2) 5.5 V 0.6 1.6 1.5 mA
Other inputs at GND or VCC
Ci VI = VCC or GND 5V 4.5 pF

(1) Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

6.6 Switching Characteristics

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 7-1)
FROM TO TA = 25°C SN54ACT04 SN74ACT04
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
tPLH 1 6 8.5 1 9 1 9
A Y ns
tPHL 1 5.5 8 1 8.5 1 8.5

6.7 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF f = 1 MHz 45 pF

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7 Parameter Measurement Information

7.1

A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.

Figure 7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description
8.1 Overview
This device contains six independent inverters. Each gate performs the Boolean function Y = A in positive logic.
8.2 Functional Block Diagram

Logic Diagram (Positive Logic)

8.3 Feature Description

The SNx4ACT04 devices have an operating VCC range from 4.5 V to 5.5 V.
8.4 Device Functional Modes
Function Table lists the function modes of the SNx4ACT04.
Function Table
(Each Inverter)
INPUT OUTPUT
A Y
H L
L H

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9 Application Information Disclaimer

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

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9.1 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section
6.3.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
9.2 Layout
9.2.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Layout Diagram specifies the rules that must be observed under all circumstances. All unused inputs
of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level
that should be applied to any particular unused input depends on the function of the device. Generally they will
be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output
section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when
disabled.
9.2.1.1 Layout Example

Figure 9-1. Layout Diagram

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10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 10-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54ACT04 Click here Click here Click here Click here Click here
SN74ACT04 Click here Click here Click here Click here Click here

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 20-Dec-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-89734012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 89734012A
SNJ54ACT
04FK
5962-8973401CA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8973401CA Samples
& Green SNJ54ACT04J
5962-8973401DA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8973401DA Samples
& Green SNJ54ACT04W
5962-8973401VCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8973401VC Samples
& Green A
SNV54ACT04J
5962-8973401VDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8973401VD Samples
& Green A
SNV54ACT04W
SN74ACT04DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD04 Samples

SN74ACT04DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT04 Samples

SN74ACT04N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74ACT04N Samples

SN74ACT04NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT04 Samples

SN74ACT04NSRG4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT04 Samples

SN74ACT04PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD04 Samples

SN74ACT04PWRE4 LIFEBUY TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD04
SN74ACT04PWRG4 LIFEBUY TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD04
SNJ54ACT04FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 89734012A
SNJ54ACT
04FK
SNJ54ACT04J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8973401CA Samples
& Green SNJ54ACT04J
SNJ54ACT04W ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8973401DA Samples
& Green SNJ54ACT04W

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Dec-2023

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ACT04, SN54ACT04-SP, SN74ACT04 :

• Catalog : SN74ACT04, SN54ACT04

• Enhanced Product : SN74ACT04-EP, SN74ACT04-EP
• Military : SN54ACT04

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Dec-2023

• Space : SN54ACT04-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 10-Jan-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ACT04DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74ACT04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ACT04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ACT04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74ACT04PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 10-Jan-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ACT04DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74ACT04DR SOIC D 14 2500 333.2 345.9 28.6
SN74ACT04DR SOIC D 14 2500 356.0 356.0 35.0
SN74ACT04NSR SO NS 14 2000 356.0 356.0 35.0
SN74ACT04PWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 10-Jan-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-89734012A FK LCCC 20 55 506.98 12.06 2030 NA
5962-8973401DA W CFP 14 25 506.98 26.16 6220 NA
5962-8973401VDA W CFP 14 25 506.98 26.16 6220 NA
SN74ACT04N N PDIP 14 25 506 13.97 11230 4.32
SN74ACT04N N PDIP 14 25 506 13.97 11230 4.32
SNJ54ACT04FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54ACT04W W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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