SN74ACT07

SCASE28 – NOVEMBER 2024

SN74ACT07 Hex Buffers with TTL-Compatible Inputs and Open-Drain Outputs

1 Features 3 Description
• Operating voltage range of 4.5V to 5.5V The SN74ACT07 device contains six independent
• TTL-compatible inputs CMOS logic buffers with TTL-compatible inputs and
• Continuous 24mA output drive at 5V open-drain outputs.
• Supports up to 75mA output drive at 5V
Device Information
in short bursts PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
• Drives 50Ω transmission lines BQA (WQFN, 14) 3mm × 2.5mm 3mm × 2.5mm
• Fast operation with delay of 8.3ns max SN74ACT07
PW (TSSOP, 14) 5mm × 6.4mm 5mm × 4.4mm

2 Applications (1) For more information, see Section 11.

(2) The package size (length × width) is a nominal value and
• Drive an indicator LED includes pins, where applicable.
• Level-shift using open-drain outputs (3) The body size (length × width) is a nominal value and does
• Control a relay not include pins.

xA xY

Functional Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes............................................8
2 Applications..................................................................... 1 8 Application and Implementation.................................... 9
3 Description.......................................................................1 8.1 Application Information............................................... 9
4 Pin Configuration and Functions...................................3 8.2 Typical Application...................................................... 9
5 Specifications.................................................................. 4 8.3 Power Supply Recommendations.............................12
5.1 Absolute Maximum Ratings........................................ 4 8.4 Layout....................................................................... 12
5.2 ESD Ratings............................................................... 4 9 Device and Documentation Support............................14
5.3 Recommended Operating Conditions.........................4 9.1 Documentation Support............................................ 14
5.4 Thermal Information....................................................4 9.2 Receiving Notification of Documentation Updates....14
5.5 Electrical Characteristics.............................................5 9.3 Support Resources................................................... 14
5.6 Switching Characteristics............................................5 9.4 Trademarks............................................................... 14
5.7 Typical Characteristics................................................ 5 9.5 Electrostatic Discharge Caution................................14
6 Parameter Measurement Information............................ 6 9.6 Glossary....................................................................14
7 Detailed Description........................................................7 10 Revision History.......................................................... 14
7.1 Description.................................................................. 7 11 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram........................................... 7 Information.................................................................... 14
7.3 Feature Description.....................................................7

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4 Pin Configuration and Functions

1A VCC
1A 1 14 VCC
1Y 2 13 6A 1 14
2A
1Y 2 13 6A
3 12 6Y
2Y 4 11 5A 6Y
2A 3 12
3A 5 10 5Y
3Y 6 9 4A 2Y 4 PAD 11 5A
GND 7 8 4Y
3A 5 10 5Y
Figure 4-1. PW Package, 14-Pin TSSOP (Top View)
3Y 6 9 4A
7 8
GND 4Y
Figure 4-2. BQA Package, 14-Pin WQFN (Top View)

Table 4-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
1A 1 Input Channel 1, Input A
1Y 2 Output Channel 1, Output Y
2A 3 Input Channel 2, Input A
2Y 4 Output Channel 2, Output Y
3A 5 Input Channel 3, Input A
3Y 6 Output Channel 3, Output Y
GND 7 — Ground
4Y 8 Output Channel 4, Output Y
4A 9 Input Channel 4, Input A
5Y 10 Output Channel 5, Output Y
5A 11 Input Channel 5, Input A
6Y 12 Output Channel 6, Output Y
6A 13 Input Channel 6, Input A
VCC 14 — Positive Supply
The thermal pad can be connected to GND or left floating. Do not connect to any other
Thermal Pad(1) —
signal or supply

(1) BQA package only.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range -0.5 7 V
VI Input voltage range(2) -0.5 VCC + 0.5V V
VO Output voltage range(2) -0.5 7 V
VI < -0.5V or VI >
IIK Input clamp current ±20 mA
VCC + 0.5V
IOK Output clamp current VO < -0.5V -50 mA
IO Continuous output current VO = 0 to 5.5V 50 mA
Continuous output current through VCC or GND ±200 mA
Tstg Storage temperature -65 150 °C
TJ Junction temperature 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

VALUE UNIT

Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

V(ESD) V
discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
Spec Description Condition MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-Level input voltage 0.8 V
VI Input Voltage 0 VCC V
VO Output Voltage 0 5.5 V
IOL Low-level output current 24 mA
Δt/Δv Input transition rise or fall rate 20 ns/V
TA Operating free-air temperature -40 125 °C

5.4 Thermal Information

THERMAL METRIC(1)
PACKAGE PINS UNIT
RθJA RθJC(top) RθJB ΨJT ΨJB RθJC(bot)
PW (TSSOP) 14 132.2 64.8 88.4 11.9 87.4 N/A °C/W
BQA (WQFN) 14 85.4 89.0 54.8 9.1 54.7 31.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

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5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
-40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX
4.5V 0.001 0.1
IOL = 50µA
5.5V 0.001 0.1
VOL IOL = 24mA 4.5V 0.5 V
IOL = 24mA 5.5V 0.5
IOL = 75mA(1) 5.5V 1.65
II VI = 5.5V or GND 0 to 5.5V ±1 µA
ICC VI = VCC or GND, IO = 0 5.5V 2 µA
ΔICC VI = VCC – 2.1; Any Input 4.5 to 5.5V 1.5 mA
CI VI = VCC or GND 5V 2 pF
CO VO = VCC or GND 5V 3 pF
CPD CL = 50pF, F = 1MHz 5V 12 pF

(1) Duration not to exceed 2ms

5.6 Switching Characteristics

CL = 50 pF; over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See
Parameter Measurement Information.
-40°C to 125°C
PARAMETER FROM (INPUT) TO (OUTPUT) VCC UNIT
MIN TYP MAX
tPLZ A Y 5V 1.9 2.9 ns
tPZL A Y 5V 6.1 8.3 ns

5.7 Typical Characteristics

TA = 25°C (unless otherwise noted)

100 0.4
90 0.36
80 0.32
70 0.28
60 0.24
ICC (nA)

VOL (V)

50 0.2
40 0.16
30 0.12
20 0.08 25°C
25 °C
10 125 °C 0.04 125°C
-40 °C -40°C
0 0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 5 10 15 20 25 30 35 40 45 50
VCC (V) IOL (mA)
Figure 5-1. Supply Current Across Supply Voltage Figure 5-2. Output Voltage vs Current in LOW State; 5V Supply

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6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All
input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns,
Vt = 1.5V.
The outputs are measured individually with one input transition per measurement.
TEST S1 RL CL ΔV VLOAD

tPLZ, tPZL CLOSED 500Ω 50pF 0.3V 2×VCC

Test VLOAD VCC

Point Input Vt Vt
S1 0V
RL
From Output tPLZ(1) tPZL(2)
Under Test
VOH
CL(1) RL Output
50%
Waveform 1 10% VCC
VOL
(1) CL includes probe and test-fixture capacitance. tPZL (2)
tPLZ (1)

Figure 6-1. Load Circuit for Open-Drain Outputs VOH

Output
50%
Waveform 2 10%
VOL
(1) tPLZ is the same as tdis.
(2) tPZL is the same as ten.
Figure 6-2. Voltage Waveforms Propagation Delays

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7 Detailed Description
7.1 Description
This device contains six independent buffers with open-drain outputs. Each gate performs the Boolean function
Y = A in positive logic.
7.2 Functional Block Diagram

xA xY

7.3 Feature Description

7.3.1 Open-Drain CMOS Outputs
This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in
the high logical state, open-drain outputs will be in a high-impedance state. The drive capability of this device
may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
When placed into the high-impedance state, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to
the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected
to the output to provide a known voltage at the output while it is in the high-impedance state. The value of
the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations.
Typically, a 10kΩ resistor can be used to meet these requirements.
Unused open-drain CMOS outputs should be left disconnected.
7.3.2 TTL-Compatible CMOS Inputs
This device includes TTL-compatible CMOS inputs. These inputs are specifically designed to interface with TTL
logic devices by having a reduced input voltage threshold.
TTL-compatible CMOS inputs are high impedance and are typically modeled as a resistor in parallel with
the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the
maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given
in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
TTL-compatible CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in the Implications of Slow or Floating CMOS Inputs application report.
Do not leave TTL-compatible CMOS inputs floating at any time during operation. Unused inputs must be
terminated at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down
resistor can be added to provide a valid input voltage during these times. The resistor value will depend on
multiple factors; however, a 10kΩ resistor is recommended and typically will meet all requirements.
7.3.3 Clamp Diode Structure
The inputs to this device have both positive and negative clamping diodes, and the outputs to this device have
negative clamping diodes only as depicted in Figure 7-1.

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CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

Figure 7-1. Electrical Placement of Clamping Diodes for Each Input and Output

7.4 Device Functional Modes

Table 7-1 lists the functional modes of the SN74ACT07.
Table 7-1. Function Table
INPUTS(1) OUTPUT(2)
A Y

L L
H Z

(1) H = High voltage level, L =

Low voltage level
(2) L = Driving low, Z = High-
impedance state

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

Open-drain outputs like those available in the SN74ACT07 provide the ability to discharge a voltage node to
ground without otherwise loading the node significantly. It is recommended to add a series resistor between
the output and any capacitance larger than 50pF as shown in the Typical Application Block Diagram to prevent
damage to the device.
The required resistor value can be determined using the maximum capacitor voltage and the maximum
continuous current for the output from the equation: R ≥ VC/IO(max).
For any given RC combination, the discharge time can be determined using the discharge plot provided in the
Application Timing Diagram and the equation τ = R × C. For example, to discharge a capacitor to 10% of the
starting value, it takes approximately 2.303 × τ = 2.303 × R × C seconds.
8.2 Typical Application
R
VC
C

Figure 8-1. Typical Application Block Diagram

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8.2.1 Design Requirements

8.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions.
The supply voltage sets the device's electrical characteristics of the device as described in the Electrical
Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the maximum static supply current, ICC,
listed in the Electrical Characteristics, and any transient current required for switching.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74ACT07 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is not
exceeded.
The SN74ACT07 can drive a load with a total capacitance less than or equal to 50pF while still meeting all of
the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed
50pF.
The SN74ACT07 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOL. When outputting in the HIGH state, the output
voltage in the equation is defined as the difference between the measured output voltage and the supply voltage
at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.

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8.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74ACT07 (as specified
in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10kΩ resistor
value is often used due to these factors.
The SN74ACT07 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
8.2.1.3 Output Considerations
The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Open-drain outputs can be connected together directly to produce a wired-AND configuration or for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.

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8.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will optimize
performance. This can be accomplished by providing short, appropriately sized traces from the SN74ACT07
to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this will prevent the maximum
output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive
load measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
8.2.3 Application Curves
100
90 (0.693 , 50%)
80
Capacitor voltage (%)

70
(1 , 36.8%)
60
(2.303 , 10%)
50
40 (5 , 0.7%)
30
(6 , 0.2%)
20
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
Time (

Figure 8-2. Application Timing Diagram

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass
capacitors to reject different frequencies of noise. The 0.1μF and 1μF capacitors are commonly used in parallel.
The bypass capacitor should be installed as close to the power terminal as possible for best results.
8.4 Layout
8.4.1 Layout Guidelines
• Bypass capacitor placement
– Place near the positive supply terminal of the device
– Provide an electrically short ground return path
– Use wide traces to minimize impedance
– Keep the device, capacitors, and traces on the same side of the board whenever possible
• Signal trace geometry
– 8mil to 12mil trace width
– Lengths less than 12cm to minimize transmission line effects
– Avoid 90° corners for signal traces
– Use an unbroken ground plane below signal traces
– Flood fill areas around signal traces
– For traces longer than 12cm
• Use impedance controlled traces

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• Source-terminate using a series damping resistor near the output

• Avoid branches; buffer signals that must branch separately
8.4.2 Layout Example
WORST BETTER BEST

2W

W
≥
≥ 5W

W
W

Figure 8-3. Example Trace Corners for Improved Signal Integrity

GND VCC VCC GND

0.1
F
0.1
F
VCC
1 14 VCC
1 20
2 13 2 19
3 12 3 18
4 11 4 17
5 10
5 16
6 9
6 GND 15
GND 7 8
7 14
Figure 8-4. Example Bypass Capacitor Placement 8 13
for TSSOP and Similar Packages
9 12
10 11
GND

Figure 8-5. Example Bypass Capacitor Placement

for WQFN and Similar Packages

GND VCC
0.1
F
1 6 VCC
2 5
GND 3 4

Figure 8-6. Example Bypass Capacitor Placement for SOT, SC70 and Similar Packages

Transmitting Port Receiving Port

22
Long controlled-impedance trace

Figure 8-7. Example Damping Resistor Placement for Improved Signal Integrity

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
• Texas Instruments, Designing With Logic application report
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application report
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
November 2024 * Initial release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

SN74ACT07BQAR Active Production WQFN (BQA) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 AD07
SN74ACT07BQAR.A Active Production WQFN (BQA) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM See SN74ACT07BQAR AD07
SN74ACT07PWR Active Production TSSOP (PW) | 14 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 AD07
SN74ACT07PWR.A Active Production TSSOP (PW) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM See SN74ACT07PWR AD07

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74ACT07 :

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• Automotive : SN74ACT07-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ACT07BQAR WQFN BQA 14 3000 180.0 12.4 2.8 3.3 1.1 4.0 12.0 Q1
SN74ACT07PWR TSSOP PW 14 3000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ACT07BQAR WQFN BQA 14 3000 210.0 185.0 35.0
SN74ACT07PWR TSSOP PW 14 3000 353.0 353.0 32.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
BQA 14 WQFN - 0.8 mm max height
2.5 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4227145/A

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 PACKAGE OUTLINE
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

2.6 A
B 2.4

3.1
PIN 1 INDEX AREA 2.9

0.8 C
0.7

SEATING PLANE
0.05 1.1 0.08 C
0.00 0.9
2X 0.5 (0.2) TYP
7 8
8X 0.5
6
9

SYMM
2X 1.6
2 15 1.4

13
2
14X 0.3
0.2
PIN 1 ID 1 14 0.1 C A B
(OPTIONAL) SYMM 14X 0.5
0.3 0.05 C

4224636/A 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(1)
2X (0.5)
1 14

2 13
8X (0.5)

2X (0.5) SYMM
(2) (1.5) (2.8)

9
6
14X (0.25)
(Ø0.2) VIA
TYP 14X (0.6)
7 8
SYMM

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

0.07 MAX 0.07 MIN METAL UNDER

ALL AROUND ALL AROUND SOLDER MASK

METAL
EXPOSED METAL

SOLDER MASK SOLDER MASK

EXPOSED METAL
OPENING OPENING

NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

4224636/A 11/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(0.95)
2X (0.5)
1 14

2 13
8X (0.5)

SYMM
(2) (1.38) (2.8)

9
6
14X (0.25)

14X (0.6)
7 8
SYMM

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
88% PRINTED COVERAGE BY AREA
SCALE: 20X

4224636/A 11/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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 PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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 EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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