SN74LVC244A

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SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020
SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020

SN74LVC244A Octal Buffer or Driver With 3-State Outputs

1 Features 3 Description
• Operates From 1.65 V to 3.6 V These octal bus buffers are designed for 1.65-V to
• Inputs Accept Voltages to 5.5 V 3.6-V VCC operation. The SN74LVC244A devices are
• Specified From –40°C to +85°C and designed for asynchronous communication between
–40°C to +125°C data buses.
• Maximum tpd of 5.9 ns at 3.3 V Device Information
• Typical VOLP (Output Ground Bounce) PART NUMBER PACKAGE(1) BODY SIZE (NOM)
< 0.8 V at VCC = 3.3 V, TA = 25°C SN74LVC244AN PDIP (20) 25.40 mm × 6.35 mm
• Typical VOHV (Output VOH Undershoot) SN74LVC244ANS SO (20) 12.60 mm × 5.30 mm
> 2 V at VCC = 3.3 V, TA = 25°C SN74LVC244ADB SSOP (20) 7.50 mm × 5.30 mm
• Supports Mixed-Mode Signal Operation on SN74LVC244ADGV TVSOP (20) 5.00 mm × 4.40 mm
All Ports (5-V Input or Output Voltage With SN74LVC244ADW SOIC (20) 12.80 mm × 7.50 mm
3.3-V VCC) SN74LVC244ARGY VQFN (20) 4.50 mm × 3.50 mm
• Ioff Supports Live Insertion, Partial-Power-Down SN74LVC244AZQN BGA (20) 3.00 mm × 4.00 mm
Mode, and Back-Drive Protection SN74LVC244APW TSSOP (20) 6.50 mm × 4.40 mm
• Can Be Used as a Down Translator to Translate SN74LVC244ARWP X1QFN (20) 2.50 mm × 3.30 mm
Inputs From a Maximum of 5.5 V Down
(1) For all available packages, see the orderable addendum at
to the VCC Level the end of the data sheet.
• Available in Ultra Small Logic QFN Package (0.5
mm Maximum Height)
1 19
1OE 2OE

• Latch-Up Performance Exceeds 250 mA Per 1A1

2 18
1Y1 2A1
11 9
2Y1

JESD 17
• ESD Protection Exceeds JESD 22
4 16 13 7
1A2 1Y2 2A2 2Y2

– 2000-V Human-Body Model 1A3

6 14
1Y3 2A3
15 5
2Y3

– 1000-V Charged-Device Model

8 12 17 3

2 Applications
1A4 1Y4 2A4 2Y4

Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.

• Servers
Logic Diagram (Positive Logic)
• LED Displays
• Network Switches
• Telecom Infrastructure
• Motor Drivers
• I/O Expanders

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................11
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................11
3 Description.......................................................................1 9 Application and Implementation.................................. 12
4 Revision History.............................................................. 2 9.1 Application Information............................................. 12
5 Pin Configuration and Functions...................................3 9.2 Typical Application.................................................... 12
6 Specifications.................................................................. 5 10 Power Supply Recommendations..............................13
6.1 Absolute Maximum Ratings........................................ 5 11 Layout........................................................................... 14
6.2 ESD Ratings............................................................... 5 11.1 Layout Guidelines................................................... 14
6.3 Recommended Operating Conditions.........................6 11.2 Layout Example...................................................... 14
6.4 Thermal Information....................................................6 12 Device and Documentation Support..........................15
6.5 Electrical Characteristics.............................................7 12.1 Receiving Notification of Documentation Updates..15
6.6 Switching Characteristics............................................8 12.2 Support Resources................................................. 15
6.7 Operating Characteristics........................................... 8 12.3 Trademarks............................................................. 15
6.8 Typical Characteristics................................................ 9 12.4 Electrostatic Discharge Caution..............................15
7 Parameter Measurement Information.......................... 10 12.5 Glossary..................................................................15
8 Detailed Description...................................................... 11 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 11 Information.................................................................... 15
8.2 Functional Block Diagram......................................... 11

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision AB (November 2016) to Revision AC (October 2020) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Changes from Revision AA (June 2016) to Revision AB (November 2016) Page

• Changed A2 to A4 for 2 OE in Pin Functions table.............................................................................................3
• Added ambient temperature, TA for BGA package and all other packages in Recommended Operating
Conditions ..........................................................................................................................................................6

Changes from Revision Z (January 2015) to Revision AA (May 2016) Page

• Updated Device Information table to show all available packages.....................................................................1
• Added RWP Package ........................................................................................................................................ 3
• Deleted GQN package from Pin Functions table................................................................................................3
• Added RWP thermal information to Thermal Information table and updated all thermal information for existing
packages............................................................................................................................................................ 6
• Updated all values for ZQN column in Thermal Information table...................................................................... 6
• Added package type in Thermal Information table............................................................................................. 6

Changes from Revision Y (September 2010) to Revision Z (January 2015) Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the
datasheet............................................................................................................................................................ 1
• Updated Features............................................................................................................................................... 1

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5 Pin Configuration and Functions

1 2 3 4

1OE 1 20 VCC
A 1A1 1OE VCC 2OE
1A1 2 19 2OE
2Y4 3 18 1Y1
B 1A2 2A4 2Y4 1Y1 1A2 4 17 2A4
2Y3 5 16 1Y2
1A3 6 15 2A3
C 1A3 2Y3 2A3 1Y2
2Y2 7 14 1Y3
1A4 8 13 2A2
D 1A4 2A2 2Y2 1Y3 2Y1 9 12 1Y4
GND 10 11 2A1

E GND 2Y1 2A1 1Y4 Not to scale

Figure 5-2. DB, DGV, DW, N, NS, and PW Packages
20-Pin SSOP, TVSOP, SOIC, PDIP, SO, and TSSOP
Not to scale Front View
Figure 5-1. ZQN Package 20-Pin BGA Top View
VCC

VCC
1OE

1OE

2OE
1Y1
1

20

20
19
18
17
1A1 2 19 2OE 1A1 1 16 2A4
2Y4 3 18 1Y1 2Y4 2 15 1Y2
1A2 4 17 2A4 1A2 3 Thermal 14 2A3
Pad
2Y3 5 Thermal 16 1Y2 2Y3 4 13 1Y3
Pad
1A3 6 15 2A3 1A3 5 12 2A2
2Y2 7 14 1Y3 2Y2 6 11 1Y4
10
7
8
9

1A4 8 13 2A2
2Y1 9 12 1Y4
10

11

1A4
2Y1
GND
2A1

Not to scale
GND

2A1

Figure 5-4. RWP Package 20-Pin X1QFN Top View

Not to scale
Figure 5-3. RGY Package 20-Pin VQFN Top View

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Table 5-1. Pin Functions

PIN
DB, DGV,
DW, N, NS, TYPE DESCRIPTION
NAME ZQN RWP
PW, and
RGY
1A1 2 A1 1 I Port 1 A1 input
1A2 4 B1 3 I Port 1 A2 input
1A3 6 C1 5 I Port 1 A3 input
1A4 8 D1 7 I Port 1 A4 input
1 OE 1 A2 20 I Output enable
1Y1 18 B4 17 O Port 1 Y1 output
1Y2 16 C4 15 O Port 1 Y2 output
1Y3 14 D4 13 O Port 1 Y3 output
1Y4 12 E4 11 O Port 1 Y4 output
2A1 11 E3 10 I Port 2 A1 input
2A2 13 D2 12 I Port 2 A2 input
2A3 15 C3 14 I Port 2 A3 input
2A4 17 B2 16 I Port 2 A4 input
2 OE 19 A4 18 I Output enable
2Y1 9 E2 8 O Port 2 Y1 output
2Y2 7 D3 6 O Port 2 Y2 output
2Y3 5 C2 4 O Port 2 Y3 output
2Y4 3 B3 2 O Port 2 Y4 output
GND 10 E1 9 — Ground
VCC 20 A3 19 — Power pin

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VI Input voltage(2) –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state(2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Ptot Power dissipation TA = –40°C to +125°C(4) (5) 500 mW
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Section 6.3 table.
(4) For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K.
(5) For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over recommended operating free-air temperature range (unless otherwise noted)(1)
TA = 25°C –40 TO +85°C –40 TO +125°C
UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC 0.65 × VCC 0.65 × VCC
High-level
VIH VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V
input voltage
VCC = 2.7 V to 3.6 V 2 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC 0.35 × VCC 0.35 × VCC
Low-level
VIL VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 V
input voltage
VCC = 2.7 V to 3.6 V 0.8 0.8 0.8
VI Input voltage 0 5.5 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC 0 VCC V
VCC = 1.65 V –4 –4 –4

High-level VCC = 2.3 V –8 –8 –8

IOH mA
output current VCC = 2.7 V –12 –12 –12
VCC = 3 V –24 –24 –24
VCC = 1.65 V 4 4 4

Low-level VCC = 2.3 V 8 8 8

IOL mA
output current VCC = 2.7 V 12 12 12
VCC = 3 V 24 24 24

Ambient BGA package –40 85

TA °C
temperature All other packages –40 125

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs , SCBA004.

6.4 Thermal Information

SN74LVC244A
DB(2) DGV(2) DW (2) ZQN(2) N(2) NS(2) PW(2) RGY(3) RWP(3)
THERMAL METRIC(1) UNIT
(SSOP) (TVSOP) (SOIC) (BGA) (PDIP) (SO) (TSSOP) (VQFN) (X1QFN)
20 PINS
Junction-to-ambient
RθJA 108.1 128.7 90.9 198.7 61.6 90.1 114.7 50.3 79.9 °C/W
thermal resistance
Junction-to-case (top)
RθJC(top) 70.2 43.7 55.3 106.8 46.5 56.4 48.4 58.4 63.2 °C/W
thermal resistance
Junction-to-board
RθJB 63.3 70.2 58.8 143.1 42.5 57.7 65.6 28.3 46.4 °C/W
thermal resistance
Junction-to-top
ψJT 30.6 3.1 29.1 24.1 34.6 28.4 6.8 4.9 2.6 °C/W
characterization parameter
Junction-to-board
ψJB 62.9 69.5 58.3 119.6 42.4 57.2 65.1 28.4 46.3 °C/W
characterization parameter
Junction-to-case (bottom)
RθJC(bot) — — — n/a — — — 22.7 27.3 °C/W
thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C –40 TO +85°C –40 TO +125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
1.65 V
IOH = –100 µA to VCC – 0.2 VCC – 0.2 VCC – 0.3
3.6 V
IOH = –4 mA 1.65 V 1.29 1.2 1.05
VOH IOH = –8 mA 2.3 V 1.9 1.7 1.55 V

2.7 V 2.2 2.2 2.05

IOH = –12 mA
3V 2.4 2.4 2.25
IOH = –24 mA 3V 2.3 2.2 2
1.65 V
IOL = 100 µA to 0.1 0.2 0.3
3.6 V
IOL = 4 mA 1.65 V 0.24 0.45 0.6
VOL V
IOL = 8 mA 2.3 V 0.3 0.7 0.75
IOL = 12 mA 2.7 V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.8
II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 µA
Ioff VI or VO = 5.5 V 0 ±1 ±10 ±20 µA
IOZ VO = 0 to 5.5 V 3.6 V ±1 ±10 ±20 µA
VI = VCC or GND 1 10 40
ICC IO = 0 3.6 V µA
3.6 V ≤ VI ≤ 5.5 V(1) 1 10 40
2.7 V
One input at VCC – 0.6 V,
ΔICC to 500 500 5000 µA
Other inputs at VCC or GND
3.6 V
Ci VI = VCC or GND 3.3 V 4 pF
Co VO = VCC or GND 3.3 V 5.5 pF

(1) This applies in the disabled state only.

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6.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
FROM TO TA = 25°C –40 TO +85°C –40 TO +125°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
1.5 V 1 7 14.4 1 14.9 1 16.4
1.8 V ± 0.15 V 1 5.9 10.4 1 10.9 1 12.4
tpd A Y 2.5 V ± 0.2 V 1 4.2 7.4 1 7.9 1 10 ns
2.7 V 1 4.2 6.7 1 6.9 1 8.2
3.3 V ± 0.3 V 1.5 3.9 5.7 1.5 5.9 1.5 7.2
1.5 V 1 8.3 17.8 1 18.3 1 19.8
1.8 V ± 0.15 V 1 6.4 12.1 1 12.6 1 14.1
ten OE Y 2.5 V ± 0.2 V 1 4.6 9.1 1 9.6 1 11.7 ns
2.7 V 1 5 8.4 1 8.6 1 10.3
3.3 V ± 0.3 V 1.5 4.5 7.4 1.5 7.6 1.5 9.4
1.5 V 1 7.2 15.6 1 16.1 1 17.6
1.8 V ± 0.15 V 1 5.8 11.6 1 12.1 1 13.6
tdis OE Y 2.5 V ± 0.2 V 1 3.7 7.3 1 7.8 1 9.9 ns
2.7 V 1 3.8 6.6 1 6.8 1 8.6
3.3 V ± 0.3 V 1.5 3.8 6.3 1.5 6.5 1.5 8
tsk(o) 3.3 V ± 0.3 V 1 1.5 ns

6.7 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
1.8 V 43
Outputs enabled f = 10 MHz 2.5 V 43
3.3 V 44
Cpd Power dissipation capacitance per buffer/driver pF
1.8 V 1
Outputs disabled f = 10 MHz 2.5 V 1
3.3 V 2

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6.8 Typical Characteristics

14 10
VCC = 3 V, VCC = 3 V,
TA = 25°C TA = 25°C
12

tpd – Propagation Delay Time – ns

One Output Switching
tpd – Propagation Delay Time – ns

One Output Switching

Four Outputs Switching 8 Four Outputs Switching
Eight Outputs Switching Eight Outputs Switching
10

8 6

6
4
4

2 2
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 6-1. Propagation Delay (Low to High Figure 6-2. Propagation Delay (High to Low
Transition) Transition)
vs Load Capacitance vs Load Capacitance

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.5 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 2 kΩ 0.1 V
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description
8.1 Overview
The SN74LVC244A device is organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs.
The device passes data from the A inputs to the Y outputs when OE is low. The outputs are in the high-
impedance state when OE is high. OE should be tied to VCC through a pullup resistor to ensure the high-
impedance state during power up or power down; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
8.2 Functional Block Diagram
1 19
1OE 2OE

2 18 11 9
1A1 1Y1 2A1 2Y1

4 16 13 7
1A2 1Y2 2A2 2Y2

6 14 15 5
1A3 1Y3 2A3 2Y3

8 12 17 3
1A4 1Y4 2A4 2Y4

Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.

Figure 8-1. Logic Diagram (Positive Logic)

8.3 Feature Description

• Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
• Inputs accept voltage levels up to 5.5 V
• It is available in ultra small logic 20 pin QFN package at 0.5 mm max height with 0.4 mm pitch.
8.4 Device Functional Modes
Table 8-1 lists the functional modes of the SN74LVC244A.
Table 8-1. Function Table
INPUTS OUTPUT
OE A Y

L H H
L L L
H X Hi-Z

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

SN74LVC244A is a high drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC
making it ideal for down translation.
9.2 Typical Application
Regulated 3 V

SN74LVC244A
1OE VCC

A1 Y1
uC
uC or System Logic
System LEDs
Logic A4 Y4

GND

Figure 9-1. Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive
currents in excess of maximum limits. The high drive will also create fast edges into light loads, so consider
routing and load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
• For rise time and fall time specification, see (Δt/ΔV) in the Section 6.3 table.
• For specified high and low levels, see (VIH and VIL) in the Section 6.3 table.
• Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Section 6.3 table at any valid
VCC.
2. Recommended maximum Output Conditions:
• Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Section 6.1 table.
• Outputs should not be pulled above VCC.

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9.2.3 Application Curves

100 60
TA = 25°C, VCC = 3 V, TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V, 40 VIH = 3 V, VIL = 0 V,
80 All Outputs Switching All Outputs Switching
20
60
0
I OL – mA

I OH – mA
40 –20

–40
20
–60
0
–80

–20 –100
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOL – V VOH – V

Figure 9-2. Output Drive Current (IOL) Figure 9-3. Output Drive Current (IOH)
vs LOW-level Output Voltage (VOL) vs HIGH-level Output Voltage (VOH)

10 Power Supply Recommendations

The power supply may be any voltage between the MIN and MAX supply voltage rating located in the Section
6.3 table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1 μF capacitor is
recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to
reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies
of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: SN74LVC244A
SN74LVC244A
SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 www.ti.com

11 Layout
11.1 Layout Guidelines
Inputs should not float when using multiple bit logic devices. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND
gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected
because the undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally, they will be tied to
GND or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC Input
Unused Input Output Unused Input Output

Input

Figure 11-1. Layout Diagram

14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: SN74LVC244A

 SN74LVC244A
www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN74LVC244A
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Feb-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC244ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244ADBRE4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244ADBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A

SN74LVC244ADWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A

SN74LVC244ADWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A

SN74LVC244ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LVC244A

SN74LVC244ADWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A

SN74LVC244AN ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type -40 to 125 SN74LVC244AN
Non-Green
SN74LVC244ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A

SN74LVC244APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWRG3 ACTIVE TSSOP PW 20 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244APWTE4 ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Feb-2021

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC244APWTG4 ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

SN74LVC244ARGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC244A

SN74LVC244ARGYRG4 ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC244A

SN74LVC244ARWPR ACTIVE X1QFN RWP 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Feb-2021

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC244A :

• Automotive: SN74LVC244A-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Feb-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC244ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LVC244ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC244ADWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74LVC244ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74LVC244ADWRG4 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74LVC244ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74LVC244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LVC244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC244APWRG3 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC244APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LVC244APWT TSSOP PW 20 250 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LVC244ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
SN74LVC244ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
SN74LVC244ARWPR X1QFN RWP 20 2000 178.0 13.5 2.85 3.65 0.75 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Feb-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC244ADBR SSOP DB 20 2000 853.0 449.0 35.0
SN74LVC244ADGVR TVSOP DGV 20 2000 853.0 449.0 35.0
SN74LVC244ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LVC244ADWR SOIC DW 20 2000 364.0 361.0 36.0
SN74LVC244ADWRG4 SOIC DW 20 2000 367.0 367.0 45.0
SN74LVC244ANSR SO NS 20 2000 367.0 367.0 45.0
SN74LVC244APWR TSSOP PW 20 2000 853.0 449.0 35.0
SN74LVC244APWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74LVC244APWRG3 TSSOP PW 20 2000 364.0 364.0 27.0
SN74LVC244APWRG4 TSSOP PW 20 2000 853.0 449.0 35.0
SN74LVC244APWT TSSOP PW 20 250 853.0 449.0 35.0
SN74LVC244ARGYR VQFN RGY 20 3000 355.0 350.0 50.0
SN74LVC244ARGYR VQFN RGY 20 3000 853.0 449.0 35.0
SN74LVC244ARWPR X1QFN RWP 20 2000 189.0 185.0 36.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RGY 20 VQFN - 1 mm max height
3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225264/A

www.ti.com
 PACKAGE OUTLINE
RGY0020A SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.65 B
A
3.35

PIN 1 INDEX AREA

4.65
4.35

1.0
0.8

SEATING PLANE
0.05
0.00 0.08 C
2.05 0.1

2X 1.5
(0.2) TYP
10 11 EXPOSED
THERMAL PAD
9
12
14X 0.5

2X SYMM 21
3.05 0.1
3.5

2
19
0.30
1 20 20X
PIN 1 ID 0.18
SYMM
0.1 C A B
0.5 0.05
20X
0.3
4225320/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.05)
SYMM
1 20
20X (0.6)

2
19

20X (0.24)

(1.275)

(4.3)
SYMM 21
(3.05)

14X (0.5)

(0.775) 12
9

(R0.05) TYP

( 0.2) TYP
VIA 10 11
(0.75) TYP

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225320/A 09/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

4X (0.92)

1 20 (R0.05) TYP

20X (0.6)

2
19

20X (0.24)

4X
(1.33)

21
SYMM

(4.3)
(0.77)

14X (0.5)

(0.56)
9 12

METAL
TYP
10 11
(0.75)
TYP
(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4225320/A 09/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
RWP0020A SCALE 4.200
X1QFN - 0.5 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2.6 B
A
2.4

PIN 1 INDEX AREA

3.4
3.2

0.5 MAX
C

SEATING PLANE
0.05
0.00 0.08

4X (0.36)
2X 1.2
(0.15) TYP
EXPOSED
7 10
THERMAL PAD
16X 0.4
6 11

2X
2 1.9±0.05

1.14±0.05

1
16
0.25
20X
0.15
PIN 1 ID 20 17 0.1 C A B
(OPTIONAL) (0.1) TYP 0.05

0.5
20X
0.3
4221912/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RWP0020A X1QFN - 0.5 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1.14)

SYMM
20 17

20X (0.6)
1
16

20X (0.2)

(0.7)
SYMM (3.1)
(1.9)

16X (0.4)

6
11

( 0.2) TYP
VIA

7 10
(R0.05)
TYP (2.3)

LAND PATTERN EXAMPLE

SCALE:20X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL
OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4221912/A 03/2015

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
RWP0020A X1QFN - 0.5 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (1.07)
(R0.05) TYP
20 17

20X (0.6)

1
16

20X (0.2)
2X
(0.85)

SYMM
(3.1)
(0.525)
16X (0.4)

METAL
TYP 6 11

7 10
SYMM

(2.3)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4221912/A 03/2015

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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