SN74AVC4T245

SCES576H – JUNE 2004 – REVISED MARCH 2024

SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation

and 3-State Outputs

1 Features The SN74AVC4T245 device is designed for

asynchronous communication between two data
• Control inputs VIH/VIL levels are referenced to
buses. The logic levels of the direction-control (DIR)
VCCA voltage
input and the output-enable (OE) input activate either
• Fully configurable dual-rail design allows each port
the B-port outputs or the A-port outputs or place
to operate over the full 1.2V to 3.6V power-supply
both output ports into the high-impedance mode. The
range
device transmits data from the A bus to the B bus
• I/Os Are 4.6V tolerant
when the B-port outputs are activated, and from the
• Ioff supports partial power-down-mode operation
B bus to the A bus when the A-port outputs are
• Maximum data rates:
activated. The input circuitry on both A and B ports
– 380Mbps (1.8V to 3.3V translation) is always active and must have a logic HIGH or LOW
– 200Mbps (< 1.8V to 3.3V translation) level applied to prevent excess ICC and ICCZ.
– 200Mbps (translate to 2.5V or 1.8V)
– 150Mbps (translate to 1.5V) The SN74AVC4T245 device is designed so that VCCA
– 100Mbps (translate to 1.2V) supplies the control pins (1DIR, 2DIR, 1 OE, and 2
• Latch-up performance exceeds 100mA per JESD OE).
78, Class II This device is fully specified for partial-power-down
• ESD protection exceeds JESD 22: applications using Ioff. The Ioff circuitry disables
– 8000V Human-Body Model (A114-A) the outputs, preventing damaging current backflow
– 150V Machine Model (A115-A) through the device when it is powered down.
– 1000V Charged-Device Model (C101)
The VCC isolation feature is designed so that if either
2 Applications VCC input is at GND, then both ports are in the high-
• Personal electronics impedance state.
• Industrial To put the device in the high-impedance state during
• Enterprise power up or power down, tie OE to VCC through a
• Telecom pullup resistor; the current-sinking capability of the
3 Description driver determines the minimum value of the resistor.

This 4-bit noninverting bus transceiver uses two Package Information

separate configurable power-supply rails. The A port PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
is designed to track VCCA. VCCA accepts any supply D (SOIC, 16) 9.9mm × 6mm
voltage from 1.2V to 3.6V. The B port is designed to DGV (TVSOP, 16) 3.6mm × 6.4mm
track VCCB. VCCB accepts any supply voltage from PW (TSSOP, 16) 5mm × 6.4mm
1.2V to 3.6V. The SN74AVC4T245 is optimized
SN74AVC4T245 RGY (WQFN, 16) 4mm × 3.5mm
to operate with VCCA/VCCB set at 1.4V to 3.6V.
RSV (UQFN, 16) 2.6mm × 1.8mm
It is operational with VCCA/VCCB as low as 1.2V.
This allows for universal low-voltage bidirectional BQB (WQFN, 16) 3.5mm × 2.5mm
translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, DYY (SOT, 16) 4.2mm × 2mm
and 3.3V voltage nodes.
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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DIR

OE

A1

B1

A2

B2

Logic Diagram (Positive Logic) for 1/2 of SN74AVC4T245

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Table of Contents
1 Features............................................................................1 7.1 Overview................................................................... 14
2 Applications..................................................................... 1 7.2 Functional Block Diagram......................................... 14
3 Description.......................................................................1 7.3 Feature Description...................................................15
4 Pin Configuration and Functions...................................3 7.4 Device Functional Modes..........................................15
5 Specifications.................................................................. 5 8 Application and Implementation.................................. 16
5.1 Absolute Maximum Ratings........................................ 5 8.1 Application Information............................................. 16
5.2 ESD Ratings............................................................... 5 8.2 Typical Application.................................................... 16
5.3 Recommended Operating Conditions.........................6 8.3 Power Supply Recommendations.............................17
5.4 Thermal Information....................................................7 8.4 Layout....................................................................... 18
5.5 Electrical Characteristics.............................................8 9 Device and Documentation Support............................19
5.6 Operating Characteristics........................................... 9 9.1 Receiving Notification of Documentation Updates....19
5.7 Switching Characteristics: VCCA = 1.2V...................... 9 9.2 Support Resources................................................... 19
5.8 Switching Characteristics: VCCA = 1.5V ± 0.1V.........10 9.3 Trademarks............................................................... 19
5.9 Switching Characteristics: VCCA = 1.8V ± 0.15V.......10 9.4 Electrostatic Discharge Caution................................19
5.10 Switching Characteristics: VCCA = 2.5V ± 0.2V....... 11 9.5 Glossary....................................................................19
5.11 Switching Characteristics: VCCA = 3.3V ± 0.3V....... 11 10 Revision History.......................................................... 19
5.12 Typical Characteristics............................................ 12 11 Mechanical, Packaging, and Orderable
6 Parameter Measurement Information.......................... 13 Information.................................................................... 20
7 Detailed Description......................................................14

4 Pin Configuration and Functions

Figure 4-1. D, DGV, or PW Package, 16-Pin SOIC,

TVSOP, or PW (Top View)

Figure 4-2. RGY Package, 16-Pin WQFN (Top View)

VCCA

16 VCCB
1

1DIR 2 15 1OE

2DIR 3 14 2OE

1A1 4 13 1B1
Thermal
Pad
1A2 5 12 1B2

2A1 6 11 2B1

2A2 7 10 2B2
GND 8

GND 9

Figure 4-4. BQB/WBQB Package, 16-Pin WQFN

(Transparent Top View)
Figure 4-3. RSV Package, 16-Pin UQFN (Top View)

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VCCA 1 16 VCCB

1DIR 2 15 1 OE

2DIR 3 14 2 OE

1A1 4 13 1B1
Thermal
1A2 5 Pad 12 1B2

2A1 6 11 2B1

2A2 7 10 2B2

GND 8 9 GND

Not to scale

Figure 4-5. DYY Package, 16-Pin SOT (Top View)

Table 4-1. Pin Functions

PIN NO.
D, DGV, TYPE(1) DESCRIPTION
NAME RSV
PW, RGY
1A1 4 6 I/O Input/output 1A1. Referenced to VCCA.
1A2 5 7 I/O Input/output 1A2. Referenced to VCCA.
1B1 13 15 I/O Input/output 1B1. Referenced to VCCB.
1B2 12 14 I/O Input/output 1B2. Referenced to VCCB.
1DIR 2 4 I Direction-control input for ‘1’ ports
3-state output-mode enables. Pull OE high to place ‘1’ outputs in 3-state
1 OE 15 1 I
mode. Referenced to VCCA.
2A1 6 8 I/O Input/output 2A1. Referenced to VCCA.
2A2 7 9 I/O Input/output 2A2. Referenced to VCCA.
2B1 11 13 I/O Input/output 2B1. Referenced to VCCB.
2B2 10 12 I/O Input/output 2B2. Referenced to VCCB.
2DIR 3 5 I Direction-control input for ‘2’ ports
3-state output-mode enables. Pull OE high to place ‘2’ outputs in 3-state
2 OE 14 16 I
mode. Referenced to VCCA.
GND 8, 9 10, 11 — Ground
VCCA 1 3 — A-port power supply voltage. 1.2V ≤ VCCA ≤ 3.6V
VCCB 16 2 — B-port power supply voltage. 1.2V ≤ VCCB ≤ 3.6V

(1) I = input, O = output

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN(1) MAX UNIT
VCCA
Supply voltage range –0.5 4.6 V
VCCB
I/O ports (A port) –0.5 4.6
VI Input voltage range(2) I/O ports (B port) –0.5 4.6 V
Control inputs –0.5 4.6

Voltage range applied to any output in the high-impedance or A port –0.5 4.6
VO V
power-off state(2) B port –0.5 4.6
A port –0.5 VCCA + 0.5
VO Voltage range applied to any output in the high or low state(2) (3) V
B port –0.5 VCCB + 0.5
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCCA, VCCB, or GND ±100 mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed.

5.2 ESD Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
8
pins(1)
kV
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification
1
JESD22-C101, all pins(2)
Machine model (C101) 150 V

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

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5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
VCCI VCCO MIN MAX UNIT
VCCA Supply voltage 1.2 3.6 V
VCCB Supply voltage 1.2 3.6 V
1.2V to 1.95V VCCI × 0.65
High-level
VIH Data inputs(4) 1.95V to 2.7V 1.6 V
input voltage
2.7V to 3.6V 2
1.2V to 1.95V VCCI × 0.35
Low-level
VIL Data inputs(4) 1.95V to 2.7V 0.7 V
input voltage
2.7V to 3.6V 0.8
1.2V to 1.95V VCCA × 0.65
High-level DIR
VIH 1.95V to 2.7V 1.6 V
input voltage (referenced to VCCA)(5)
2.7V to 3.6V 2
1.2V to 1.95V VCCA × 0.35
Low-level DIR
VIL 1.95V to 2.7V 0.7 V
input voltage (referenced to VCCA)(5)
2.7V to 3.6V 0.8
VI Input voltage 0 3.6 V
Active state 0 VCCO
VO Output voltage V
3-state 0 3.6
1.2V –3
1.4V to 1.6V –6
IOH High-level output current 1.65V to 1.95V –8 mA
2.3V to 2.7V –9
3V to 3.6V –12
1.1V to 1.2V 3
1.4V to 1.6V 6
IOL Low-level output current 1.65V to 1.95V 8 mA
2.3V to 2.7V 9
3V to 3.6V 12
Δt/Δv Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature –40 85 °C

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND for proper device operation. Refer to the Implications of Slow or
Floating CMOS Inputs application report.
(4) For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7V, VIL max = VCCI × 0.3V
(5) For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7V, VIL max = VCCA × 0.3V

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5.4 Thermal Information

SN74AVC4T245
THERMAL METRIC(1) D BQB DYY DGV PW RGY RSV UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 85.5 80.8 163.4 126.0 101.8 37.5 146.9
RθJC(top) Junction-to-case (top) thermal resistance 46.9 77.9 90.0 50.8 37.2 54.5 53.6
RθJB Junction-to-board thermal resistance 43.0 50.7 93.1 57.7 60.6 15.6 75.6
ψJT Junction-to-top characterization parameter 13.4 7.4 10.9 5.7 1.6 0.5 13.5 °C/W

ψJB Junction-to-board characterization

42.7 50.6 92.1 57.2 60.0 15.8 75.6
parameter
RθJC(bot) Junction-to-case (bottom) thermal
— 28.4 — — — 3.5 —
resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1) TA = 25°C –40°C to 85°C
(2) TEST CONDITIONS VCCA VCCB UNIT
MIN TYP MAX MIN MAX
IOH = –100μA 1.2V to 3.6V 1.2V to 3.6V VCCO – 0.2
IOH = –3mA 1.2V 1.2V 0.95
IOH = –6mA 1.4V 1.4V 1.05
VOH VI = VIH V
IOH = –8mA 1.65V 1.65V 1.2
IOH = –9mA 2.3V 2.3V 1.75
IOH = –12mA 3V 3V 2.3
IOL = 100μA 1.2V to 3.6V 1.2V to 3.6V 0.2
IOL = 3mA 1.2V 1.2V 0.25
IOL = 6mA 1.4V 1.4V 0.35
VOL VI = VIL V
IOL = 8mA 1.65V 1.65V 0.45
IOL = 9mA 2.3V 2.3V 0.55
IOL = 12mA 3V 3V 0.7
Control
II VI = VCCA or GND 1.2V to 3.6V 1.2V to 3.6V ±0.025 ±0.25 ±1 μA
inputs
0V 0V to 3.6V ±0.1 ±1 ±5
Ioff A or B port VI or VO = 0 to 3.6V μA
0V to 3.6V 0V ±0.1 ±1 ±5
VO = VCCO or GND,
IOZ A or B port 3.6V 3.6V ±0.5 ±2.5 ±5 μA
VI = VCCI or GND, OE = VIH
1.2V to 3.6V 1.2V to 3.6V 8
ICCA VI = VCCI or GND, IO = 0 0V 0V to 3.6V –2 μA
0V to 3.6V 0V 8
1.2V to 3.6V 1.2V to 3.6V 8
ICCB VI = VCCI or GND, IO = 0 0V 0V to 3.6V 8 μA
0V to 3.6V 0V –2
ICCA + ICCB VI = VCCI or GND, IO = 0 1.2V to 3.6V 1.2V to 3.6V 16 μA
Control
Ci VI = 3.3V or GND 3.3V 3.3V 3.5 4.5 pF
inputs
Cio A or B port VO = 3.3V or GND 3.3V 3.3V 6 7 pF

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.

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5.6 Operating Characteristics

TA = 25°C
VCCA = VCCA = VCCA = VCCA = VCCA =
TEST VCCB = 1.2V VCCB = 1.5V VCCB = 1.8V VCCB = 2.5V VCCB = 3.3V
PARAMETER UNIT
CONDITIONS
TYP TYP TYP TYP TYP
Outputs
1 1 1 1.5 2
enabled
A to B
Outputs
CL = 0, 1 1 1 1 1
disabled
CpdA (1) f = 10MHz, pF
Outputs tr = tf = 1ns 12 12.5 13 14 15
enabled
B to A
Outputs
1 1 1 1 1
disabled
Outputs
12 12.5 13 14 15
enabled
A to B
Outputs
CL = 0, 1 1 1 1 1
disabled
CpdB (1) f = 10MHz, pF
Outputs tr = tf = 1ns 1 1 1 1 2
enabled
B to A
Outputs
1 1 1 1 1
disabled

(1) Power dissipation capacitance per transceiver

5.7 Switching Characteristics: VCCA = 1.2V

over recommended operating free-air temperature range, VCCA = 1.2V (unless otherwise noted) (see Figure 6-1)
VCCB = 1.5V VCCB = 1.8V VCCB = 2.5V VCCB = 3.3V
FROM TO VCCB = 1.2V
PARAMETER ± 0.1V ± 0.15V ± 0.2V ± 0.3V UNIT
(INPUT) (OUTPUT)
TYP TYP TYP TYP TYP
tPLH 3.4 2.9 2.7 2.6 2.8
A B ns
tPHL 3.4 2.9 2.7 2.6 2.8
tPLH 3.6 3.1 2.8 2.6 2.6
B A ns
tPHL 3.6 3.1 2.8 2.6 2.6
tPZH 5.6 4.7 4.3 3.9 3.7
OE A ns
tPZL 5.6 4.7 4.3 3.9 3.7
tPZH 5 4.3 3.9 3.6 3.6
OE B ns
tPZL 5 4.3 3.9 3.6 3.6
tPHZ 6.2 5.2 5.2 4.3 4.8
OE A ns
tPLZ 6.2 5.2 5.2 4.3 4.8
tPHZ 5.9 5.1 5 4.7 5.5
OE B ns
tPLZ 5.9 5.1 5 4.7 5.5

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5.8 Switching Characteristics: VCCA = 1.5V ± 0.1V

over recommended operating free-air temperature range, VCCA = 1.5V ± 0.1V (see Figure 6-1)
VCCB = 1.5V VCCB = 1.8V VCCB = 2.5V VCCB = 3.3V
FROM TO VCCB = 1.2V
PARAMETER ± 0.1V ± 0.15V ± 0.2V ± 0.3V UNIT
(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH 3.2 0.3 6.3 0.3 5.2 0.4 4.2 0.4 4.2
A B ns
tPHL 3.2 0.3 6.3 0.3 5.2 0.4 4.2 0.4 4.2
tPLH 3.3 0.7 6.3 0.5 6 0.4 5.7 0.3 5.6
B A ns
tPHL 3.3 0.7 6.3 0.5 6 0.4 5.7 0.3 5.6
tPZH 4.9 1.4 9.6 1.1 9.5 0.7 9.4 0.4 9.4
OE A ns
tPZL 4.9 1.4 9.6 1.1 9.5 0.7 9.4 0.4 9.4
tPZH 4.5 1.4 9.6 1.1 7.7 0.9 5.8 0.9 5.6
OE B ns
tPZL 4.5 1.4 9.6 1.1 7.7 0.9 5.8 0.9 5.6
tPHZ 5.6 1.8 10.2 1.5 10.2 1.3 10.2 1.6 10.2
OE A ns
tPLZ 5.6 1.8 10.2 1.5 10.2 1.3 10.2 1.6 10.2
tPHZ 5.2 1.9 10.3 1.9 9.1 1.4 7.4 1.2 7.6
OE B ns
tPLZ 5.2 1.9 10.3 1.9 9.1 1.4 7.4 1.2 7.6

5.9 Switching Characteristics: VCCA = 1.8V ± 0.15V

over recommended operating free-air temperature range, VCCA = 1.8V ± 0.15V (see Figure 6-1)
VCCB = 1.5V VCCB = 1.8V VCCB = 2.5V VCCB = 3.3V
FROM TO VCCB = 1.2V
PARAMETER ± 0.1V ± 0.15V ± 0.2V ± 0.3V UNIT
(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH 2.9 0.1 6 0.1 4.9 0.1 3.9 0.3 3.9
A B ns
tPHL 2.9 0.1 6 0.1 4.9 0.1 3.9 0.3 3.9
tPLH 3 0.6 5.3 0.5 4.9 0.3 4.6 0.3 4.5
B A ns
tPHL 3 0.6 5.3 0.5 4.9 0.3 4.6 0.3 4.5
tPZH 4.4 1 7.4 1 7.3 0.6 7.3 0.4 7.2
OE A ns
tPZL 4.4 1 7.4 1 7.3 0.6 7.3 0.4 7.2
tPZH 4.1 1.2 9.2 1 7.4 0.8 5.3 0.8 4.6
OE B ns
tPZL 4.1 1.2 9.2 1 7.4 0.8 5.3 0.8 4.6
tPHZ 5.4 1.6 8.6 1.8 8.7 1.3 8.7 1.6 8.7
OE A ns
tPLZ 5.4 1.6 8.6 1.8 8.7 1.3 8.7 1.6 8.7
tPHZ 5 1.7 9.9 1.6 8.7 1.2 6.9 1 6.9
OE B ns
tPLZ 5 1.7 9.9 1.6 8.7 1.2 6.9 1 6.9

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5.10 Switching Characteristics: VCCA = 2.5V ± 0.2V

over recommended operating free-air temperature range, VCCA = 2.5V ± 0.2V (see Figure 6-1)
VCCB = 1.5V VCCB = 1.8V VCCB = 2.5V VCCB = 3.3V
FROM TO VCCB = 1.2V
PARAMETER ± 0.1V ± 0.15V ± 0.2V ± 0.3V UNIT
(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH 2.8 0.1 5.7 0.1 4.6 0.2 3.5 0.1 3.6
A B ns
tPHL 2.8 0.1 5.7 0.1 4.6 0.2 3.5 0.1 3.6
tPLH 2.7 0.6 4.2 0.4 3.9 0.2 3.4 0.2 3.3
B A ns
tPHL 2.7 0.6 4.2 0.4 3.9 0.2 3.4 0.2 3.3
tPZH 4 0.7 6.5 0.7 5.2 0.6 4.8 0.4 4.8
OE A ns
tPZL 4 0.7 6.5 0.7 5.2 0.6 4.8 0.4 4.8
tPZH 3.8 0.9 8.8 0.8 7 0.6 4.8 0.6 4
OE B ns
tPZL 3.8 0.9 8.8 0.8 7 0.6 4.8 0.6 4
tPHZ 4.7 1 8.4 1 8.4 1 6.2 1 6.6
OE A ns
tPLZ 4.7 1 8.4 1 8.4 1 6.2 1 6.6
tPHZ 4.5 1.5 9.4 1.3 8.2 1.1 6.2 0.9 5.2
OE B ns
tPLZ 4.5 1.5 9.4 1.3 8.2 1.1 6.2 0.9 5.2

5.11 Switching Characteristics: VCCA = 3.3V ± 0.3V

over recommended operating free-air temperature range, VCCA = 3.3V ± 0.3V (see Figure 6-1)
VCCB = 1.5V VCCB = 1.8V VCCB = 2.5V VCCB = 3.3V
FROM TO VCCB = 1.2V
PARAMETER ± 0.1V ± 0.15V ± 0.2V ± 0.3V UNIT
(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH 2.9 0.1 5.6 0.1 4.5 0.1 3.3 0.1 2.9
A B ns
tPHL 2.9 0.1 5.6 0.1 4.5 0.1 3.3 0.1 2.9
tPLH 2.6 0.6 4.2 0.4 3.4 0.2 3 0.1 2.8
B A ns
tPHL 2.6 0.6 4.2 0.4 3.4 0.2 3 0.1 2.8
tPZH 3.8 0.6 8.7 0.6 5.2 0.6 3.8 0.4 3.8
OE A ns
tPZL 3.8 0.6 8.7 0.6 5.2 0.6 3.8 0.4 3.8
tPZH 3.7 0.8 8.7 0.6 6.8 0.5 4.7 0.5 3.8
OE B ns
tPZL 3.7 0.8 8.7 0.6 6.8 0.5 4.7 0.5 3.8
tPHZ 4.8 0.7 9.3 0.7 8.3 0.7 5.6 0.7 6.6
OE A ns
tPLZ 4.8 0.7 9.3 0.7 8.3 0.7 5.6 0.7 6.6
tPHZ 5.3 1.4 9.3 1.2 8.1 1 6.4 0.8 6.2
OE B ns
tPLZ 5.3 1.4 9.3 1.2 8.1 1 6.4 0.8 6.2

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5.12 Typical Characteristics

3.6 3.6

3.2 3.2

2.8 2.8

2.4 2.4

VOH Voltage (V)

VOL Voltage (V)

2.0 2.0

1.6 1.6

1.2 1.2

0.8 0.8

-40 °C -40 °C
0.4 0.4
25 °C 25 °C
85 °C 85 °C
0 0
0 20 40 60 80 100 0 20 40 60 80 100
IOL Current (mA) IOH Current (mA)
Figure 5-1. Low-Level Output Voltage (VOL) Figure 5-2. High-Level Output Voltage (VOH)
vs Low-Level Current (IOL) vs High-Level Current (IOH)

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6 Parameter Measurement Information

2 × VCCO
TEST S1
RL S1 Open tpd Open
From Output
GND tPLZ/tPZL 2 × VCCO
Under Test
tPHZ/tPZH GND
CL RL
(see Note A)

LOAD CIRCUIT tw

VCCI
Input VCCI/2 VCCI/2
VCCO CL RL VTP 0V
1.2 V 15 pF 2 kΩ 0.1 V
VOLTAGE WAVEFORMS
1.5 V ± 0.1 V 15 pF 2 kΩ 0.1 V PULSE DURATION
1.8 V ± 0.15 V 15 pF 2 kΩ 0.15 V
2.5 V ± 0.2 V 15 pF 2 kΩ 0.15 V
3.3 V ± 0.3 V 15 pF 2 kΩ 0.3 V VCCA
Output
Control VCCA/2 VCCA/2
(low-level
enabling) 0V

tPZL tPLZ

Output VCCO
VCCI
Input VCCI/2 VCCI/2 Waveform 1 VCCO/2 VOL + VTP
S1 at 2 × VCCO VOL
0V
(see Note B)
tPLH tPHL tPZH tPHZ
Output
VOH
VOH Waveform 2 VOH − VTP
S1 at GND VCCO/2
Output VCCO/2 VCCO/2
(see Note B) 0V
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t PLZ and t PHZ are the same as tdis.
F. t PZL and t PZH are the same as ten.
G. tPLH and t PHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.

Figure 6-1. Load and Circuit and Voltage Waveforms

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7 Detailed Description
7.1 Overview
The SN74AVC4T245 is a 4-bit, dual-supply noninverting bidirectional voltage level translation device. VCCA
supports the Ax pins and control pins (1DIR, 2DIR,1 OE, and 2 OE), and VCCB supports the Bx pins. The A port
can accept I/O voltages ranging from 1.2V to 3.6V, while the B port can accept I/O voltages from
1.2V to 3.6V. A high on DIR allows data transmission from Ax to Bx and a low on DIR allows data transmission
from Bx to Ax when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance
state.
7.2 Functional Block Diagram

DIR

OE

A1

B1

A2

B2

Figure 7-1. Logic Diagram (Positive Logic) for 1/2 of SN74AVC4T245

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7.3 Feature Description

7.3.1 Fully Configurable Dual-Rail Design
The fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range.
Both VCCA and VCCB can be supplied at any voltage between 1.2V and 3.6V; thus, making the device an
excellent choice for translating between any of the low voltage nodes (1.2V, 1.8V, 2.5V, and 3.3V).
7.3.2 Supports High Speed Translation
The SN74AVC4T245 device can support high data rate applications. The translated signal data rate can be up to
380Mbps when the signal is translated from 1.8V to 3.3V.
7.3.3 Ioff Supports Partial-Power-Down Mode Operation
Ioff will prevent backflow current by disabling I/O output circuits when the device is in partial-power-down mode.
7.4 Device Functional Modes
Table 7-1. Function Table
(Each 2-Bit Section)
CONTROL INPUTS OUTPUT CIRCUITS
OPERATION(1)
OE DIR A PORT B PORT
L L Enabled Hi-Z B data to A bus
L H Hi-Z Enabled A data to B bus
H X Hi-Z Hi-Z Isolation

(1) Input circuits of the data I/Os are always active.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The SN74AVC4T245 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74AVC4T245 device is an excellent choice
for applications where a push-pull driver is connected to the data I/Os. The maximum data rate can be up to
380Mbps when device translates a signal from 1.8V to 3.3V.
8.2 Typical Application
1.2 V 3.3 V
0.1 μC 0.1 μC 1 µF

VCCA VCCB
1OE

2OE

1DIR
2DIR
1.2 V 3.3 V
SN74AVC4T245 System
Controller

1A1 1B1
1A2 1B2
Data Data
2A1 2B1
2A2 2B2

GND GND GND

Figure 8-1. Typical Application Diagram

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8.2.1 Design Requirements

For the design example shown in Section 8.2 use the parameters listed in Table 8-1.
Table 8-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 1.2V to 3.6V
Output voltage range 1.2V to 3.6V

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AVC4T245 device to determine the input
voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low,
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AVC4T245 device is driving to determine the output
voltage range.
8.2.3 Application Curves

Input (1.2 V)

Output (3.3 V)

Figure 8-2. Translation Up (1.2V to 3.3V) at 2.5MHz

8.3 Power Supply Recommendations

The SN74AVC4T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts
any supply voltage from 1.2V to 3.6V and VCCB accepts any supply voltage from 1.2V to 3.6V. The A port and B
port are designed to track VCCA and VCCB respectively allowing for low-voltage bidirectional translation between
any of the 1.2V, 1.5V, 1.8V, 2.5V and 3.3V voltage nodes.
The output-enable (OE) input circuit is designed so that VCCA supplies OE, and when the OE input is high, all
outputs are placed in the high-impedance state. To put the outputs in the high-impedance state during power up
or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until
VCCA and VCCB are fully ramped and stable. The current-sinking capability of the driver determines the minimum
value of the pullup resistor to VCCA.

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8.4 Layout
8.4.1 Layout Guidelines
For device reliability, it is recommended to follow common printed-circuit board layout guidelines, such as
follows:
• Bypass capacitors should be used on power supplies.
• Short trace lengths should be used to avoid excessive loading.
• Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals, depending on the system requirements.
8.4.2 Layout Example
LEGEND

VIA to Power Plane Polygonal Copper Pour

VIA to GND Plane (Inner Layer)

VCCA VCCB

Bypass Capacitor Bypass Capacitor

VCCA

1 VCCA VCCB 16

2 1DIR 1OE 15

3 2DIR 2OE 14

Keep OE high until VCCA and

From To VCCB are powered up
4 1A1 1B1 13 System
Controller

From To
5 1A2 1B2 12 System
Controller

To From
6 2A1 2B1 11
Controller System

To From
7 2A2 2B2 10
Controller System

8 GND GND 9

SN74AVC4T245

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9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (November 2014) to Revision H (March 2024) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Added the BQB and DYY package information throughout the data sheet........................................................1
• Updated the package information table to include package lead size................................................................1

Changes from Revision F (October 2014) to Revision G (November 2014) Page

• Changed Pin Functions table. ........................................................................................................................... 3
• Changed Typical Application schematic. ......................................................................................................... 16

Changes from Revision E (December 2011) to Revision F (October 2014) Page

• Added Applications, Pin Configuration and Functions section, Handling Rating table, Thermal Information
table, Feature Description section, Typical Characteristics section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1

Changes from Revision D (September 2007) to Revision E (December 2011) Page

• Fixed tPZL VCCB = 3.3V parameter typographical error from 36.6 to 3.6.............................................................9

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

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 PACKAGE OPTION ADDENDUM

www.ti.com 24-Nov-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

74AVC4T245DGVRE4 ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

74AVC4T245RGYRG4 ACTIVE VQFN RGY 16 3000 TBD Call TI Call TI -40 to 85 Samples

74AVC4T245RSVR-NT ACTIVE UQFN RSV 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ZWU Samples

74AVC4T245RSVRG4 ACTIVE UQFN RSV 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ZWU Samples

SN74AVC4T245BQBR ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 WT245 Samples

SN74AVC4T245D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC4T245 Samples

SN74AVC4T245DGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC4T245 Samples

SN74AVC4T245DRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC4T245 Samples

SN74AVC4T245DT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC4T245 Samples

SN74AVC4T245DYYR ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 WT245 Samples

SN74AVC4T245PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245PWE4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245PWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245PWTE4 ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245PWTG4 ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WT245 Samples

SN74AVC4T245RGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 WT245 Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Nov-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74AVC4T245RSVR ACTIVE UQFN RSV 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ZWU Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AVC4T245 :

• Automotive : SN74AVC4T245-Q1

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Nov-2024

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
74AVC4T245RSVR-NT UQFN RSV 16 3000 180.0 8.4 2.0 2.8 0.7 4.0 8.0 Q1
74AVC4T245RSVR-NT UQFN RSV 16 3000 180.0 9.5 2.1 2.9 0.75 4.0 8.0 Q1
SN74AVC4T245BQBR WQFN BQB 16 3000 180.0 12.4 2.8 3.8 1.2 4.0 12.0 Q1
SN74AVC4T245DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AVC4T245DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74AVC4T245DYYR SOT-23- DYY 16 3000 330.0 12.4 4.8 3.6 1.6 8.0 12.0 Q3
THIN
SN74AVC4T245PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AVC4T245PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AVC4T245RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
SN74AVC4T245RSVR UQFN RSV 16 3000 178.0 13.5 2.1 2.9 0.75 4.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74AVC4T245RSVR-NT UQFN RSV 16 3000 200.0 183.0 25.0
74AVC4T245RSVR-NT UQFN RSV 16 3000 189.0 185.0 36.0
SN74AVC4T245BQBR WQFN BQB 16 3000 210.0 185.0 35.0
SN74AVC4T245DGVR TVSOP DGV 16 2000 356.0 356.0 35.0
SN74AVC4T245DR SOIC D 16 2500 353.0 353.0 32.0
SN74AVC4T245DYYR SOT-23-THIN DYY 16 3000 336.6 336.6 31.8
SN74AVC4T245PWR TSSOP PW 16 2000 356.0 356.0 35.0
SN74AVC4T245PWT TSSOP PW 16 250 356.0 356.0 35.0
SN74AVC4T245RGYR VQFN RGY 16 3000 356.0 356.0 35.0
SN74AVC4T245RSVR UQFN RSV 16 3000 189.0 185.0 36.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74AVC4T245D D SOIC 16 40 507 8 3940 4.32
SN74AVC4T245PW PW TSSOP 16 90 530 10.2 3600 3.5
SN74AVC4T245PWE4 PW TSSOP 16 90 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
RSV0016A SCALE 5.000
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

1.85
B A
1.75

PIN 1 INDEX AREA

2.65
2.55

0.55 C
0.45
SEATING PLANE

0.05 0.05 C
0.00

2X 1.2

SYMM (0.13) TYP

5 ℄ 8
0.45
15X
0.35

4
9

SYMM
2X 1.2 ℄

12X 0.4

1 0.25
12 16X
0.15
0.07 C A B
0.05
16 13
0.55
0.45 PIN 1 ID
(45° X 0.1)

4220314/C 02/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RSV0016A UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

SYMM
(0.7) ℄

16 13 SEE SOLDER MASK

DETAIL

16X (0.2) 1 12

SYMM
12X (0.4) ℄ (2.4)

(R0.05) TYP 4 9

15X (0.6)

5 8
(1.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 25X

0.05 MIN
0.05 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4220314/C 02/2020
NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
RSV0016A UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

(0.7)
16 13

16X (0.2) 1 12

SYMM
12X (0.4) ℄ (2.4)

(R0.05) TYP
4 9

15X (0.6)

5 8
SYMM
℄

(1.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 25X

4220314/C 02/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 GENERIC PACKAGE VIEW
BQB 16 WQFN - 0.8 mm max height
2.5 x 3.5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4226161/A

www.ti.com
 PACKAGE OUTLINE
BQB0016A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

2.6 A
B 2.4

3.6
3.4
PIN 1 INDEX AREA

0.8 C
0.7
SEATING PLANE
1.1 0.08 C
0.05 0.9
0.00 (0.2) TYP
2X 0.5
8 9
10X 0.5
7
10

SYMM
2X 2.1
2.5 1.9

15
2

PIN 1 ID 1 16 16X 0.30

0.18
(OPTIONAL) SYMM 0.5
16X 0.3 0.1 C A B
0.05 C

4224640/A 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
BQB0016A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)
(1)

2X (0.5)
1 16

10X (0.5)
2 15

2X SYMM
(2) (3.3)
(2.5)
2X
(0.75)

10
7

16X (0.24)
(Ø0.2) VIA
TYP 9
16X (0.6)
8
SYMM
(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

0.07 MAX 0.07 MIN METAL UNDER

ALL AROUND ALL AROUND SOLDER MASK

METAL
EXPOSED METAL

SOLDER MASK SOLDER MASK

EXPOSED METAL
OPENING OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

4224640/A 11/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
BQB0016A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)
(0.95)

2X (0.5)
1 16

10X (0.5)
2 15

2X SYMM
(1.79) (3.3)
(2.5)

10
7

16X (0.24)
EXPOSED METAL
9
16X (0.6)
8
SYMM
(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X

4224640/A 11/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DYY0016A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

3.36 C
3.16 SEATING PLANE

A PIN 1 INDEX
AREA 0.1 C
14X 0.5

1 16

4.3 2X
4.1
NOTE 3 3.5

4X 0° - 15°
8
9

2.1 16X 0.3

0.11
1.1 MAX
B 1.9
0.1 C A B

4X 4° - 15°

0.2 TYP
0.08

SEE DETAIL A

0.25
GAUGE PLANE

0°- 8°
0.63 0.1
0.33 0.0
DETAIL A
TYP

4224642/D 07/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AA

www.ti.com
 EXAMPLE BOARD LAYOUT
DYY0016A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

16X (1.05)
SYMM

1 16

16X (0.3)

SYMM

14X (0.5)

8 9

(R0.05) TYP
(3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

SOLDER MASK METAL UNDER

OPENING SOLDER MASK SOLDER MASK
METAL OPENING

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4224642/D 07/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DYY0016A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

16X (1.05)
SYMM

1 16

16X (0.3)

SYMM

14X (0.5)

8 9

(R0.05) TYP
(3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 20X

4224642/D 07/2024

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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