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SN74AVCH8T245
SCES565H – APRIL 2004 – REVISED MARCH 2016

SN74AVCH8T245 8-Bit Dual-Supply Bus Transceiver

With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs
1 Features 3 Description
1• Control Inputs (DIR and OE) VIH and VIL Levels The SN74AVCH8T245 is an 8-bit noninverting bus
Are Referenced to VCCA Voltage transceiver that uses two separate configurable
power-supply rails. The A port is designed to track
• Bus Hold on Data Inputs Eliminates the Need for VCCA, which accepts any supply voltage from 1.2 V to
External Pullup or Pulldown Resistors 3.6 V. The B port is designed to track VCCB, which
• VCC Isolation Feature also accepts any supply voltage from 1.2 V to 3.6 V.
• Fully Configurable Dual-Rail Design This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V,
• I/Os Are 4.6-V Tolerant 2.5-V, and 3.3-V voltage nodes.
• Ioff Supports Partial-Power-Down Mode Operation
The SN74AVCH8T245 is designed for asynchronous
• Max Data Rates: communication between data buses. The device
– 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V) transmits data from either the A bus to the B bus, or
– 170 Mbps (VCCA ≤ 1.8 V or VCCB ≤ 1.8 V) from the B bus to the A bus, depending on the logic
level at the direction-control (DIR) input. The output-
• Latch-Up Performance Exceeds 100 mA Per enable (OE) input can be used to disable the outputs
JESD 78, Class II so the buses are effectively isolated.
• ESD Protection Exceeds JESD 22
– 8000-V Human-Body Model (A114-A) Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– 200-V Machine Model (A115-A)
TVSOP (24) 5.00 mm × 4.40 mm
– 1000-V Charged-Device Model (C101)
SN74AVCH8T245 TSSOP (24) 7.80 mm × 4.40 mm

2 Applications VQFN (24) 5.50 mm × 3.50 mm

• Personal Electronics (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Industrial
• Enterprise
• Telecommunications
Logic Diagram (Positive Logic)

2
DIR

22
OE

3
A1

21
B1

To Seven Other Channels

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 9 Detailed Description ............................................ 18
2 Applications ........................................................... 1 9.1 Overview ................................................................. 18
3 Description ............................................................. 1 9.2 Functional Block Diagram ....................................... 18
4 Revision History..................................................... 2 9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 19
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 4 10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
7 Specifications......................................................... 5
10.2 Typical Application ................................................ 20
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5 11 Power Supply Recommendations ..................... 21
7.3 Recommended Operating Conditions....................... 6 12 Layout................................................................... 22
7.4 Thermal Information .................................................. 6 12.1 Layout Guidelines ................................................. 22
7.5 Electrical Characteristics........................................... 7 12.2 Layout Example .................................................... 22
7.6 Switching Characteristics, VCCA = 1.2 V ................... 9 13 Device and Documentation Support ................. 23
7.7 Switching Characteristics, VCCA= 1.5 V ± 0.1 V...... 10 13.1 Documentation Support ........................................ 23
7.8 Switching Characteristics, VCCA= 1.8 V ± 0.15 V.... 11 13.2 Community Resources.......................................... 23
7.9 Switching Characteristics, VCCA= 2.5 V ± 0.2 V...... 12 13.3 Trademarks ........................................................... 23
7.10 Switching Characteristics, VCCA= 3.3 V ± 0.3 V.... 13 13.4 Electrostatic Discharge Caution ............................ 23
7.11 Operating Characteristics...................................... 14 13.5 Glossary ................................................................ 23
7.12 Typical Characteristics .......................................... 15 14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information ................ 17 Information ........................................................... 23

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (March 2007) to Revision H Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted the Ordering Information table. See the POA at the end of the data sheet. ............................................................ 1

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5 Description (continued)
The SN74AVCH8T245 is designed so that the control pins (DIR and OE) are referenced to VCCA.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device.
The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-
impedance state. The bus-hold circuitry on the powered-up side always stays active.
The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a '245
function, with minimal printed circuit board redesign.
To ensure the high-impedance state during power up or power down, OE shall be tied to VCCA through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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6 Pin Configuration and Functions

DGV or PW Package
24-Pin TVSOP or TSSOP RHL Package
Top View 24-Pin VQFN
Top View

VCCA

VCCB
VCCA 1 24 VCCB
DIR 2 23 VCCB
A1 3 22 OE 1 24
A2 4 21 B1 23 VCCB
DIR 2
A3 5 20 B2 A1 3 22 OE
A4 6 19 B3 A2 4 21 B1
A5 7 18 B4 A3 5 20 B2
A6 8 17 B5 A4 6 19 B3
A7 9 16 B6 A5 7 18 B4
A8 10 15 B7 A6 8 17 B5
GND 11 14 B8 A7 9 16 B6
GND 12 13 GND A8 10 15 B7
GND 11 14 B8
12 13

GND

GND
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A1 3 I/O Input/output A1. Referenced to VCCA.
A2 4 I/O Input/output A2. Referenced to VCCA.
A3 5 I/O Input/output A3. Referenced to VCCA.
A4 6 I/O Input/output A4. Referenced to VCCA.
A5 7 I/O Input/output A5. Referenced to VCCA.
A6 8 I/O Input/output A6. Referenced to VCCA.
A7 9 I/O Input/output A7. Referenced to VCCA.
A8 10 I/O Input/output A8. Referenced to VCCA.
B1 21 I/O Input/output B1. Referenced to VCCB.
B2 20 I/O Input/output B2. Referenced to VCCB.
B3 19 I/O Input/output B3. Referenced to VCCB.
B4 18 I/O Input/output B4. Referenced to VCCB.
B5 17 I/O Input/output B5. Referenced to VCCB.
B6 16 I/O Input/output B6. Referenced to VCCB.
B7 15 I/O Input/output B7. Referenced to VCCB.
B8 14 I/O Input/output B8. Referenced to VCCB.
DIR 2 I Direction-control signal. Referenced to VCCA.
GND 11, 12, 13 — Ground
OE 22 I 3-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced to VCCA.
VCCA 1 — A-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V
VCCB 23, 24 — B-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCCA
Supply voltage –0.5 4.6 V
VCCB
I/O ports (A port) –0.5 4.6
VI Input voltage (2) I/O ports (B port) –0.5 4.6 V
Control inputs –0.5 4.6
Voltage applied to any output A port –0.5 4.6
VO V
in the high-impedance or power-off state (2) B port –0.5 4.6
A port –0.5 VCCA + 0.5
VO Voltage applied to any output in the high or low state (2) (3) V
B port –0.5 VCCB + 0.5
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCCA, VCCB, or GND ±100 mA
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±8000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V
Machine model (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

(1) (2)
See
MIN MAX UNIT
VCCA Supply voltage 1.2 3.6 V
VCCB Supply voltage 1.2 3.6 V
VCCI = 1.2 V to 1.95 V VCCI × 0.65
VIH High-level input voltage (1) Data inputs VCCI = 1.95 V to 2.7 V 1.6 V
VCCI = 2.7 V to 3.6 V 2
VCCI = 1.2 V to 1.95 V VCCI × 0.35
VIL Low-level input voltage (1) Data inputs VCCI = 1.95 V to 2.7 V 0.7 V
VCCI = 2.7 V to 3.6 V 0.8
VCCI = 1.2 V to 1.95 V VCCA × 0.65
DIR and OE
VIH High-level input voltage VCCI = 1.95 V to 2.7 V 1.6 V
(referenced to VCCA)
VCCI = 2.7 V to 3.6 V 2
VCCI = 1.2 V to 1.95 V VCCA × 0.35
DIR and OE
VIL Low-level input voltage VCCI = 1.95 V to 2.7 V 0.7 V
(referenced to VCCA)
VCCI = 2.7 V to 3.6 V 0.8
VI Input voltage Control Inputs 0 3.6 V
Active state 0 VCCO
VO Output voltage (2) V
3-state 0 3.6
VCCO = 1.2 V –3
VCCO = 1.4 V to 1.6 V –6
IOH High-level output current VCCO = 1.65 V to 1.95 V –8 mA
VCCO = 2.3 V to 2.7 V –9
VCCO = 3 V to 3.6 V –12
VCCO = 1.2 V 3
VCCO = 1.4 V to 1.6 V 6
IOL Low-level output current VCCO = 1.65 V to 1.95 V 8 mA
VCCO = 2.3 V to 2.7 V 9
VCCO = 3 V to 3.6 V 12
Δt/Δv Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature –40 85 °C

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.

7.4 Thermal Information

SN74AVCH8T245
(1)
THERMAL METRIC DGV (TVSOP) PW (TSSOP) RHL (VQFN) UNIT
24 PINS 24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance (2) 95.5 92 35 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27 29.3 39.9 °C/W
RθJB Junction-to-board thermal resistance 48.9 46.7 13.8 °C/W
ψJT Junction-to-top characterization parameter 0.7 1.5 0.3 °C/W
ψJB Junction-to-board characterization parameter 48.5 46.2 13.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 1.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.

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7.5 Electrical Characteristics

All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –100 μA, VI= VIH VCCA = VCCB = 1.2 V to 3.6 V VCCO – 0.2
IOH = –3 mA, VI= VIH VCCA = VCCB = 1.2 V 0.95
High-level output IOH = –6 mA, VI= VIH VCCA = VCCB = 1.4 V 1.05
VOH V
voltage (1) IOH = –8 mA, VI= VIH VCCA = VCCB = 1.65 V 1.2
IOH = –9 mA, VI= VIH VCCA = VCCB = 2.3 V 1.75
IOH = –12 mA, VI= VIH VCCA = VCCB = 3 V 2.3
IOL = 100 µA, VI= VIL VCCA = VCCB = 1.2 V to 3.6 V 0.2
IOL = 3 mA, VI= VIL VCCA = VCCB = 1.2 V 0.15
Low-level output IOL = 6 mA, VI= VIL VCCA = VCCB = 1.4 V 0.35
VOL V
voltage IOL = 8 mA, VI= VIL VCCA = VCCB = 1.65 V 0.45
IOL = 9 mA, VI= VIL VCCA = VCCB = 2.3 V 0.55
IOL = 12 mA, VI= VIL VCCA = VCCB = 3 V 0.7
II Control inputs VI = VCCA or GND VCCA = VCCB = 1.2 V to 3.6 V ±0.025 ±1 μA
VI = 0.42 V VCCA = VCCB = 1.2 V 25
VI = 0.49 V VCCA = VCCB = 1.4 V 15
Bus-hold low
IBHL sustaining VI = 0.58 V VCCA = VCCB = 1.65 V 25 μA
current (2)
VI = 0.7 V VCCA = VCCB = 2.3 V 45
VI = 0.8 V VCCA = VCCB = 3.3 V 100
VI = 0.78 V VCCA = VCCB = 1.2 V –25
VI = 0.91 V VCCA = VCCB = 1.4 V –15
Bus-hold high
IBHH sustaining VI = 1.07 V VCCA = VCCB = 1.65 V –25 μA
current (3)
VI = 1.6 V VCCA = VCCB = 2.3 V –45
VI = 2 V VCCA = VCCB = 3.3 V –100
VCCA = VCCB = 1.2 V 50
VCCA = VCCB = 1.6 V 125
Bus-hold low
IBHLO overdrive VI = 0 to VCC VCCA = VCCB = 1.95 V 200 μA
current (4)
VCCA = VCCB = 2.7 V 300
VCCA = VCCB = 3.6 V 500
VCCA = VCCB = 1.2 V –50
VCCA = VCCB = 1.6 V –125
Bus-hold high
IBHHO overdrive VI = 0 to VCC VCCA = VCCB = 1.95 V –200 μA
current (5)
VCCA = VCCB = 2.7 V –300
VCCA = VCCB = 3.6 V –500
VCCA = 0 V,
Input/output A Port ±0.1 ±5
VI = 0 V to 3.6 V, VCCB = 0 V to 3.6 V
Ioff power-off leakge μA
VO= 0 V to 3.6 V VCCA = 0 V to 3.6 V,
current B Port ±0.1 ±5
VCCB = 0 V

(1) VCCO is the VCC associated with the output port.

(2) The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
(3) The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
(4) An external driver must source at least IBHLO to switch this node from low to high.
(5) An external driver must sink at least IBHHO to switch this node from high to low.
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Electrical Characteristics (continued)

All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO = VCCO or GND, A Port,
VCCA = VCCB = 3.6 V ±0.5 ±5
VI = VCCI or GND, OE = VIH B Port
Off-state output VCCA = 0 V,
IOZ VO = VCCO or GND, B Port ±5 μA
current (1) (6) (7) VCCB = 3.6 V
VI = VCCI or GND,
OE = Don't Care VCCA = 3.6 V,
A Port ±5
VCCB = 0 V
VCCA = VCCB = 1.2 V to 3.6 V 8
Supply current A
ICCA VI = VCCI or GND, IO = 0 VCCA = 0 V, VCCB = 3.6 V –2 μA
port (6)
VCCA = 3.6 V, VCCB = 0 V 8
VCCA = VCCB = 1.2 V to 3.6 V 8
Supply current B
ICCB VI = VCCI or GND, IO = 0 VCCA = 0 V, VCCB = 3.6 V 8 μA
port (6)
VCCA = 3.6 V, VCCB = 0 V –2
ICCA+ Combined supply
VI = VCCI or GND, IO = 0 VCCA = VCCB = 1.2 V to 3.6 V 16 μA
ICCB current (6)
Input capacitance
Ci VI = 3.3 V or GND VCCA = VCCB = 3.3 V 3.5 4.5 pF
control pins
Input/output
Cio capacitance a or b VO = 3.3 V or GND VCCA = VCCB = 3.3 V 6 7 pF
port

(6) VCCI is the VCC associated with the input port.

(7) For I/O ports, the parameter IOZ includes the input leakage current.

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7.6 Switching Characteristics, VCCA = 1.2 V

TA= 25°C (see Figure 10)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
VCCB = 1.2 V 3.1
VCCB = 1.5 V 2.6
Propagation delay time:
tPLH,
low-to-high-level output and A B VCCB = 1.8 V 2.5 ns
tPHL
high-to-low level output
VCCB = 2.5 V 3
VCCB = 3.3 V 3.5
VCCB = 1.2 V 3.1
VCCB = 1.5 V 2.7
Propagation delay time:
tPLH,
low-to-high-level output and B A VCCB = 1.8 V 2.5 ns
tPHL
high-to-low level output
VCCB = 2.5 V 2.4
VCCB = 3.3 V 2.3
VCCB = 1.2 V 5.3
VCCB = 1.5 V 5.3
Enable time:
tPZH,
to high level and OE A VCCB = 1.8 V 5.3 ns
tPZL
to low level
VCCB = 2.5 V 5.3
VCCB = 3.3 V 5.3
VCCB = 1.2 V 5.1
VCCB = 1.5 V 4
Enable time:
tPZH,
to high level and OE B VCCB = 1.8 V 3.5 ns
tPZL
to low level
VCCB = 2.5 V 3.2
VCCB = 3.3 V 3.1
VCCB = 1.2 V 4.8
VCCB = 1.5 V 4.8
Disable time:
tPHZ,
from high level and OE A VCCB = 1.8 V 4.8 ns
tPLZ
from low level
VCCB = 2.5 V 4.8
VCCB = 3.3 V 4.8
VCCB = 1.2 V 4.7
VCCB = 1.5 V 4
Disable time:
tPHZ,
from high level and OE B VCCB = 1.8 V 4.1 ns
tPLZ
from low level
VCCB = 2.5 V 4.3
VCCB = 3.3 V 5.1

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7.7 Switching Characteristics, VCCA= 1.5 V ± 0.1 V

All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 10)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
VCCB = 1.2 V 2.7
VCCB = 1.5 V 0.5 5.4
Propagation delay time:
tPLH,
low-to-high-level output and A B VCCB = 1.8 V 0.5 4.6 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 4.9
VCCB = 3.3 V 0.5 6.8
VCCB = 1.2 V 2.6
VCCB = 1.5 V 0.5 5.4
Propagation delay time:
tPLH,
low-to-high-level output and B A VCCB = 1.8 V 0.5 5.1 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 4.7
VCCB = 3.3 V 0.5 4.5
VCCB = 1.2 V 3.7
VCCB = 1.5 V 1.1 8.7
Enable time:
tPZH,
to high level and OE A VCCB = 1.8 V 1.1 8.7 ns
tPZL
to low level
VCCB = 2.5 V 1.1 8.7
VCCB = 3.3 V 1.1 8.7
VCCB = 1.2 V 4.8
VCCB = 1.5 V 1.1 7.6
Enable time:
tPZH,
to high level and OE B VCCB = 1.8 V 1.1 7.1 ns
tPZL
to low level
VCCB = 2.5 V 1.1 5.6
VCCB = 3.3 V 1.1 5.2
VCCB = 1.2 V 3.1
VCCB = 1.5 V 0.5 8.6
Disable time:
tPHZ,
from high level and OE A VCCB = 1.8 V 0.5 8.6 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 8.6
VCCB = 3.3 V 0.5 8.6
VCCB = 1.2 V 4.1
VCCB = 1.5 V 0.5 8.4
Disable time:
tPHZ,
from high level and OE B VCCB = 1.8 V 0.5 7.6 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 7.2
VCCB = 3.3 V 0.5 7.8

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7.8 Switching Characteristics, VCCA= 1.8 V ± 0.15 V

All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 10)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
VCCB = 1.2 V 2.5
VCCB = 1.5 V 0.5 5.1
Propagation delay time:
tPLH,
low-to-high-level output and A B VCCB = 1.8 V 0.5 4.4 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 4
VCCB = 3.3 V 0.5 3.9
VCCB = 1.2 V 2.5
VCCB = 1.5 V 0.5 4.6
Propagation delay time:
tPLH,
low-to-high-level output and B A VCCB = 1.8 V 0.5 4.4 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 3.9
VCCB = 3.3 V 0.5 3.7
VCCB = 1.2 V 3
VCCB = 1.5 V 1 6.8
Enable time:
tPZH,
to high level and OE A VCCB = 1.8 V 1 6.8 ns
tPZL
to low level
VCCB = 2.5 V 1 6.8
VCCB = 3.3 V 1 6.8
VCCB = 1.2 V 4.6
VCCB = 1.5 V 1.1 8.2
Enable time:
tPZH,
to high level and OE B VCCB = 1.8 V 1 6.7 ns
tPZL
to low level
VCCB = 2.5 V 0.5 5.1
VCCB = 3.3 V 0.5 4.5
VCCB = 1.2 V 2.8
VCCB = 1.5 V 0.5 7.1
Disable time:
tPHZ,
from high level and OE A VCCB = 1.8 V 0.5 7.1 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 7.1
VCCB = 3.3 V 0.5 7.1
VCCB = 1.2 V 3.9
VCCB = 1.5 V 0.5 7.8
Disable time:
tPHZ,
from high level and OE B VCCB = 1.8 V 0.5 6.9 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 6
VCCB = 3.3 V 0.5 5.8

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7.9 Switching Characteristics, VCCA= 2.5 V ± 0.2 V

All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 10)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
VCCB = 1.2 V 2.4
VCCB = 1.5 V 0.5 4.7
Propagation delay time:
tPLH,
low-to-high-level output and A B VCCB = 1.8 V 0.5 3.9 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 3.1
VCCB = 3.3 V 0.5 2.8
VCCB = 1.2 V 3
VCCB = 1.5 V 0.5 4.9
Propagation delay time:
tPLH,
low-to-high-level output and B A VCCB = 1.8 V 0.5 4 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 3.1
VCCB = 3.3 V 0.5 2.9
VCCB = 1.2 V 2.2
VCCB = 1.5 V 0.5 4.8
Enable time:
tPZH,
to high level and OE A VCCB = 1.8 V 0.5 4.8 ns
tPZL
to low level
VCCB = 2.5 V 0.5 4.8
VCCB = 3.3 V 0.5 4.8
VCCB = 1.2 V 4.5
VCCB = 1.5 V 1.1 7.9
Enable time:
tPZH,
to high level and OE B VCCB = 1.8 V 0.5 6.4 ns
tPZL
to low level
VCCB = 2.5 V 0.5 4.6
VCCB = 3.3 V 0.5 4
VCCB = 1.2 V 1.8
VCCB = 1.5 V 0.5 5.1
Disable time:
tPHZ,
from high level and OE A VCCB = 1.8 V 0.5 5.1 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 5.1
VCCB = 3.3 V 0.5 5.1
VCCB = 1.2 V 3.6
VCCB = 1.5 V 0.5 7.1
Disable time:
tPHZ,
from high level and OE B VCCB = 1.8 V 0.5 6.3 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 5.1
VCCB = 3.3 V 0.5 3.9

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7.10 Switching Characteristics, VCCA= 3.3 V ± 0.3 V

All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 10)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
VCCB = 1.2 V 2.3
VCCB = 1.5 V 0.5 4.5
Propagation delay time:
tPLH,
low-to-high-level output and A B VCCB = 1.8 V 0.5 3.7 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 2.9
VCCB = 3.3 V 0.5 2.5
VCCB = 1.2 V 3.5
VCCB = 1.5 V 0.5 6.8
Propagation delay time:
tPLH,
low-to-high-level output and B A VCCB = 1.8 V 0.5 3.9 ns
tPHL
high-to-low level output
VCCB = 2.5 V 0.5 2.8
VCCB = 3.3 V 0.5 2.5
VCCB = 1.2 V 2
VCCB = 1.5 V 0.5 4
Enable time:
tPZH,
to high level and OE A VCCB = 1.8 V 0.5 4 ns
tPZL
to low level
VCCB = 2.5 V 0.5 4
VCCB = 3.3 V 0.5 4
VCCB = 1.2 V 4.5
VCCB = 1.5 V 1.1 7.8
Enable time:
tPZH,
to high level and OE B VCCB = 1.8 V 0.5 6.2 ns
tPZL
to low level
VCCB = 2.5 V 0.5 4.5
VCCB = 3.3 V 0.5 3.9
VCCB = 1.2 V 1.7
VCCB = 1.5 V 0.5 4
Disable time:
tPHZ,
from high level and OE A VCCB = 1.8 V 0.5 4 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 4
VCCB = 3.3 V 0.5 4
VCCB = 1.2 V 3.4
VCCB = 1.5 V 0.5 6.9
Disable time:
tPHZ,
from high level and OE B VCCB = 1.8 V 0.5 6 ns
tPLZ
from low level
VCCB = 2.5 V 0.5 4.8
VCCB = 3.3 V 0.5 4.2

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7.11 Operating Characteristics

TA= 25°C
FROM TO
PARAMETER TEST CONDITIONS TYP UNIT
(INPUT) (OUTPUT)
VCCA = VCCB = 1.2 V 1
VCCA = VCCB = 1.5 V 1
Power dissipation capacitance CL = 0 pF,
per transceiver (1) A B f = 10 MHz, VCCA = VCCB = 1.8 V 1
port A - outputs enabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 1
VCCA = VCCB = 3.3 V 1
VCCA = VCCB = 1.2 V 1
VCCA = VCCB = 1.5 V 1
Power dissipation capacitance CL = 0 pF,
per transceiver (1) A B f = 10 MHz, VCCA = VCCB = 1.8 V 1
port A - outputs disabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 1
VCCA = VCCB = 3.3 V 1
CpdA pF
VCCA = VCCB = 1.2 V 12
VCCA = VCCB = 1.5 V 12
Power dissipation capacitance CL = 0 pF,
per transceiver (1) B A f = 10 MHz, VCCA = VCCB = 1.8 V 12
port A - outputs enabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 13
VCCA = VCCB = 3.3 V 14
VCCA = VCCB = 1.2 V 1
VCCA = VCCB = 1.5 V 1
Power dissipation capacitance CL = 0 pF,
per transceiver (1) B A f = 10 MHz, VCCA = VCCB = 1.8 V 1
port A - outputs disabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 1
VCCA = VCCB = 3.3 V 1
VCCA = VCCB = 1.2 V 12
VCCA = VCCB = 1.5 V 12
Power dissipation capacitance CL = 0 pF,
per transceiver (1) A B f = 10 MHz, VCCA = VCCB = 1.8 V 12
port B - outputs enabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 13
VCCA = VCCB = 3.3 V 14
VCCA = VCCB = 1.2 V 1
VCCA = VCCB = 1.5 V 1
Power dissipation capacitance CL = 0 pF,
per transceiver (1) A B f = 10 MHz, VCCA = VCCB = 1.8 V 1
port B - outputs disabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 1
VCCA = VCCB = 3.3 V 1
CpdB pF
VCCA = VCCB = 1.2 V 1
VCCA = VCCB = 1.5 V 1
Power dissipation capacitance CL = 0 pF,
per transceiver (1) B A f = 10 MHz, VCCA = VCCB = 1.8 V 1
port B - outputs enabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 1
VCCA = VCCB = 3.3 V 1
VCCA = VCCB = 1.2 V 1
VCCA = VCCB = 1.5 V 1
Power dissipation capacitance CL = 0 pF,
per transceiver (1) B A f = 10 MHz, VCCA = VCCB = 1.8 V 1
port B - outputs disabled tr = tf = 1 ns
VCCA = VCCB = 2.5 V 1
VCCA = VCCB = 3.3 V 1

(1) See to TI application report, CMOS Power Consumption and Cpd Calculation (SCAA035).

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7.12 Typical Characteristics

TA = 25°C

6 6

5 5

4 4

tPLH − ns
tPD − ns

3 3

2 VCCB = 1.2 V 2 VCCB = 1.2 V

VCCB = 1.5 V VCCB = 1.5 V

VCCB = 1.8 V VCCB = 1.8 V

1 1
VCCB = 2.5 V VCCB = 2.5 V
VCCB = 3.3 V VCCB = 3.3 V

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
CL − pF CL − pF

VCCA = 1.2 V VCCA = 1.5 V

Figure 1. Typical Propagation Delay (A to B) vs Load Figure 2. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance
6 6
VCCB = 1.2 V
VCCB = 1.5 V
5 5
VCCB = 1.8 V
VCCB = 2.5 V
4 4 VCCB = 3.3 V

tPLH − ns
tPHL − ns

3 3

2 VCCB = 1.2 V 2
VCCB = 1.5 V
VCCB = 1.8 V
1 1
VCCB = 2.5 V
VCCB = 3.3 V

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
CL − pF CL − pF

VCCA = 1.5 V VCCA = 1.8 V

Figure 3. Typical Propagation Delay (A to B) vs Load Figure 4. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance
6 6
VCCB = 1.2 V VCCB = 1.2 V
VCCB = 1.5 V VCCB = 1.5 V
5 5
VCCB = 1.8 V VCCB = 1.8 V
VCCB = 2.5 V VCCB = 2.5 V
4 VCCB = 3.3 V 4 VCCB = 3.3 V
tPLH − ns
tPHL − ns

3 3

2 2

1 1

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
CL − pF CL − pF

VCCA = 1.8 V VCCA = 2.5 V

Figure 5. Typical Propagation Delay (A to B) vs Load Figure 6. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance

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Typical Characteristics (continued)

TA = 25°C
6 6
VCCB = 1.2 V VCCB = 1.2 V
VCCB = 1.5 V VCCB = 1.5 V
5 5
VCCB = 1.8 V VCCB = 1.8 V
VCCB = 2.5 V VCCB = 2.5 V
4 VCCB = 3.3 V 4 VCCB = 3.3 V

tPLH − ns
tPHL − ns

3 3

2 2

1 1

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
CL − pF CL − pF

VCCA = 2.5 V VCCA = 3.3 V

Figure 7. Typical Propagation Delay (A to B) vs Load Figure 8. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance
6
VCCB = 1.2 V
VCCB = 1.5 V
5
VCCB = 1.8 V
VCCB = 2.5 V
4 VCCB = 3.3 V
tPHL − ns

0
0 10 20 30 40 50 60
CL − pF

VCCA = 3.3 V

Figure 9. Typical Propagation Delay (A to B) vs Load Capacitance

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8 Parameter Measurement Information

2 × VCCO
TEST S1
RL S1 Open t pd Open
From Output
GND t PLZ/t PZL 2 × VCCO
Under Test
t PHZ/t PZH GND
CL RL
(see Note A)

LOAD CIRCUIT tw

VCCI
Input VCCI/2 VCCI/2
VCCO CL RL VTP 0V
1.2 V 15 pF 2 kW 0.1 V
VOLTAGE WAVEFORMS
1.5 V ± 0.1 V 15 pF 2 kW 0.1 V PULSE DURATION
1.8 V ± 0.15 V 15 pF 2 kW 0.15 V
2.5 V ± 0.2 V 15 pF 2 kW 0.15 V
3.3 V ± 0.3 V 15 pF 2 kW 0.3 V VCCA
Output
Control VCCA/2 VCCA/2
(low-level
enabling) 0V

t PZL t PLZ

VCCO
VCCI
Input VCCI/2 VCCI/2 Output VCCO/2 VOL + VTP
0V Waveform 1 VOL
S1 at 2 × VCCO
t PLH t PHL (see Note B) t PZH t PHZ
Output
VOH
VOH Waveform 2 VOH − VTP
S1 at GND VCCO/2
Output VCCO/2 VCCO/2
(see Note B) 0V
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.

Figure 10. Load Circuit and Voltage Waveforms

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9 Detailed Description

9.1 Overview
The SN74AVCH8T245 is an 8-bit, dual supply noninverting bidirectional voltage level translator. Pins A1 through
A4, and the control pins (DIR and OE) are referenced to VCCA, while pins B1 through B4 are referenced to VCCB.
Both the A port and B port can accept I/O voltages ranging from 1.2 V to 3.6 V. With OE set to low, a high on
DIR allows data transmission from Port A to Port B, and a low on DIR allows data transmission from Port B to
Port A. When OE is set to high, both Port A and Port B outputs are in the high-impedance state. See AVC Logic
Family Technology and Application (SCEA006).

9.2 Functional Block Diagram

2
DIR

22
OE

3
A1

21
B1

To Seven Other Channels

Figure 11. Logic Diagram (Positive Logic)

9.3 Feature Description

9.3.1 Fully Configurable Dual-Rail Design
Both VCCA and VCCB can be supplied at any voltage from 1.2 V to 3.6 V, making the device suitable for translating
between any of the low voltage nodes: 1.2 V, 1.8 V, 2.5 V, and 3.3 V.

Table 1. Typical Total Static Power Consumption (ICCA + ICCB)

VCCA
VCCB UNIT
0V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
0V 0 <0.5 <0.5 <0.5 <0.5 <0.5
1.2 V <0.5 <1 <1 <1 <1 1
1.5 V <0.5 <1 <1 <1 <1 1
μA
1.8 V <0.5 <1 <1 <1 <1 <1
2.5 V <0.5 1 <1 <1 <1 <1
3.3 V <0.5 1 <1 <1 <1 <1

9.3.2 Supports High-Speed Translation

SN74AVCH8T245 can support high data rate applications, which can be calculated from the maximum
propagation delay. This is also dependent on output load. The translated signal data rate can be up to 320 Mbps
when both VCCA and VCCB are at least 1.8 V.

9.3.3 Partial-Power-Down Mode Operation

Ioff circuitry disables the outputs, preventing damaging current backflow through the SN74AVCH8T245 when it is
powered down. This can occur in applications where subsections of a system are powered down (partial-power-
down) to reduce power consumption.

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9.3.4 Bus-Hold Circuitry

Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state, which helps with board space
savings and reduced component costs. Use of pull-up or pull-down resistors with the bus-hold circuitry is not
recommended. See Bus-Hold Circuit (SCLA015).

9.3.5 VCC Isolation Feature

The VCC isolation feature ensures that if either VCCA or VCCB are at GND (or < 0.4 V), both ports will be in a high-
impedance state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to
either bus.

9.4 Device Functional Modes

Table 2 lists the functional modes of the SN74AVCH8T245.

Table 2. Function Table (Each 8-Bit Section)

CONTROL INPUTS (1) OUTPUT CIRCUITS
OPERATION
OE DIR A PORT B PORT
L L Enabled Hi-Z B data to A bus
L H Hi-Z Enabled A data to B bus
H X Hi-Z Hi-Z Isolation

(1) Input circuits of the data I/Os are always active.

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN74AVCH8T245 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74AVCH8T245 device is ideal for data
transmission which direction is different with each channel. The maximum data rate can be up to 320 Mbps when
device voltage power supply is more than 1.8 V.

10.2 Typical Application

1.2V 3.3V

0.1 µF 0.1 µF 1 µF

VCCA VCCB

DIR

OE

1.2 V 3.3 V
SN74AVCH8T245
Controller System

A1 B1
A2 B2
A3 B3
A4 B4
Data Data
A5 B5
A6 B6
A7 B7
A8 B8

GND GND GND

Figure 12. Typical Application Schematic

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Typical Application (continued)

10.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.

Table 3. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
Input voltage 1.2 V to 3.6 V
Output voltage 1.2 V to 3.6 V

10.2.2 Detailed Design Procedure

To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AVCH8T245 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AVCH8T245 device is driving to determine the output
voltage range.

10.2.3 Application Curves

1.2V to 3.3V Voltage Translation(2.5MHz)

Input(1.2V)

Output(3.3V)

Figure 13. Translation Up (1.2 V to 3.3 V) at 2.5 MHz

11 Power Supply Recommendations

The output-enable (OE) input circuit is designed so that it is referenced to VCCA and when the OE input is high,
all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during
power up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be
enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is
determined by the current-sinking capability of the driver.
VCCA or VCCB can be powered up first. If the SN74LVCH8T245 is powered up in a permanently enabled state
(for example OE is always kept low), pullup resistors are recommended at the input. This ensures proper, glitch-
free, power-up. See Designing with SN4LVCXT245 and SN74LVCHXT245 Family of Direction Controlled Voltage
Translators/Level-Shifters (SLVA746). In addition, the OE pin may be shorted to GND if the application does not
require use of the high-impedance state at any time.

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12 Layout

12.1 Layout Guidelines

To ensure reliability of the device, TI recommends following the common printed-circuit board layout guidelines.
• Bypass capacitors should be used on power supplies.
• Short trace lengths should be used to avoid excessive loading.
• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.

12.2 Layout Example

LEGEND

VIA to Power Plane Polygonal Copper Pour

VIA to GND Plane (Inner Layer)

VCCA VCCB

Bypass Capacitor Bypass Capacitor

VCCA

1 VCCA VCCB 16

Keep OE high until VCCA and

2 DIR VCCB 15 VCCB are powered up

From
3 A1 OE 14
Controller

From To
4 A2 B1 13 System
Controller

From To
5 A3 B2 12 System
Controller

From To
6 A4 B3 11 System
Controller

From To
7 A5 B4 10 System
Controller

From To
8 A6 B5 12 System
Controller

From To
9 A7 B6 11 System
Controller

From To
10 A8 B7 10 System
Controller

To
11 GND B8 10 System

12 GND GND 13

SN74AVCH8T245

Figure 14. SN74AVCH8T245 Layout Example

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation
For related documentation, see the following:
• Designing with SN74LVCXT245 and SN74LVCHXT245 Family of Direction Controlled Voltage
Translators/Level-Shifters, SLVA746
• Bus-Hold Circuit, SCLA015
• AVC Logic Family Technology and Applications, SCEA006
• CMOS Power Consumption and Cpd Calculation, SCAA035

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

74AVCH8T245PWRG4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WP245

74AVCH8T245RHLRG4 ACTIVE VQFN RHL 24 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 WP245

SN74AVCH8T245DGVR ACTIVE TVSOP DGV 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WP245

SN74AVCH8T245PW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WP245

SN74AVCH8T245PWG4 ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WP245

SN74AVCH8T245PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WP245

SN74AVCH8T245RHLR ACTIVE VQFN RHL 24 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 WP245

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AVCH8T245DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AVCH8T245PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74AVCH8T245RHLR VQFN RHL 24 1000 180.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AVCH8T245DGVR TVSOP DGV 24 2000 356.0 356.0 35.0
SN74AVCH8T245PWR TSSOP PW 24 2000 356.0 356.0 35.0
SN74AVCH8T245RHLR VQFN RHL 24 1000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74AVCH8T245PW PW TSSOP 24 60 530 10.2 3600 3.5
SN74AVCH8T245PWG4 PW TSSOP 24 60 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0024A SCALE 2.000
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1

2X
7.9 7.15
7.7
NOTE 3

12
13
0.30
24X
4.5 0.19 1.2 MAX
B
4.3 0.1 C A B
NOTE 4

0.25
GAGE PLANE
0.15
0.05

(0.15) TYP
SEE DETAIL A 0.75
0 -8 0.50
DETAIL A
A 20

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

1 (R0.05) TYP

24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220208/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

(R0.05) TYP
1
24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220208/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
RHL0024A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
3.6 A
B 3.4

PIN 1 INDEX AREA

5.6
5.4

1 MAX
C

SEATING PLANE
0.05
0.00 2.05±0.1 0.08 C
2X 1.5

24X 0.5
SYMM
0.3 (0.1) TYP
12 13
18X 0.5
11
14

21

2X SYMM
4.05±0.1
4.5

23
2
24X 0.30
0.18
PIN 1 ID 1 24
0.1 C A B
(OPTIONAL) 4X (0.2)
2X (0.55) 0.05 C
4225250/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RHL0024A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1 24
24X (0.6)

24X (0.24) 2X (0.4)

23
2

18X (0.5)

2X (1.105)

25 6X (0.67)
SYMM
(4.05) 4.6 (5.3)
4.4

SOLDER MASK
OPENING

METAL UNDER
SOLDER MASK

(Ø 0.2) VIA
TYP

(R0.05) TYP
11
14

12 13
4X
(0.775)
4X (0.2)

2X (0.55)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 18X
0.07 MIN SOLDER MASK
0.07 MAX OPENING
ALL AROUND ALL AROUND

EXPOSED METAL EXPOSED METAL

METAL

SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4225250/A 09/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RHL0024A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(3.3)
(2.05)
2X (1.5)
SYMM
SOLDER MASK EDGE
1 24 TYP
24X (0.6)

24X (0.24)
23
2

18X (0.5)

25

SYMM
4.6 (5.3)
4.4

4X
(1.34)

METAL TYP

(R0.05) TYP
11
14

12 13 2X (0.84)
6X (0.56)
4X (0.2)

2X (0.55)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 18X

4225250/A 09/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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