SN74LVC2G74

SCES203Q – APRIL 1999 – REVISED SEPTEMBER 2021

SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop

With Clear and Preset

1 Features 3 Description
• Available in the Texas Instruments This single positive-edge-triggered D-type flip-flop is
NanoFree™ package designed for 1.65 V to 5.5 V VCC operation.
• Supports 5 V VCC operation
NanoFree™ package technology is a major
• Inputs accept voltages to 5.5 V
breakthrough in IC packaging concepts, using the die
• Maximum tpd of 5.9 ns at 3.3 V
as the package.
• Low power consumption, 10 μA maximum ICC
• ±24 mA output drive at 3.3 V A low level at the preset (PRE) or clear (CLR) input
• Typical VOLP (output ground bounce) sets or resets the outputs, regardless of the levels
< 0.8 V at VCC = 3.3 V, TA = 25°C of the other inputs. When PRE and CLR are inactive
• Typical VOHV (output VOH undershoot) (high), data at the data (D) input meeting the setup
> 2 V at VCC = 3.3 V, TA = 25°C time requirements is transferred to the outputs on
• Ioff supports live insertion, partial-power-down the positive-going edge of the clock pulse. Clock
mode, and back-drive protection triggering occurs at a voltage level and is not related
• Latch-up performance exceeds 100 mA Per JESD directly to the rise time of the clock pulse. Following
78, class II the hold-time interval, data at the D input can be
• ESD protection exceeds JESD 22 changed without affecting the levels at the outputs.
– 2000 V human-body model This device is fully specified for partial-power-down
– 200 V machine model applications using Ioff. The Ioff circuitry disables
– 1000 V charged-device model the outputs, preventing damaging current backflow
2 Applications through the device when it is powered down.
• Servers Device Information(1)
• LED displays PART NUMBER PACKAGE BODY SIZE
• Network switch SM8 (8) 2.95 mm × 2.80 mm
• Telecom infrastructure SN74LVC2G74 VSSOP (8) 2.30 mm × 2.00 mm
• Motor drivers DSBGA (8) 1.91 mm × 0.91 mm
• I/O expanders
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

PRE
D Q

CLK Q
CLR

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.1 Overview..................................................................... 9
2 Applications..................................................................... 1 8.2 Functional Block Diagram........................................... 9
3 Description.......................................................................1 8.3 Feature Description.....................................................9
4 Revision History.............................................................. 2 8.4 Device Functional Modes............................................9
5 Pin Configuration and Functions...................................3 9 Application and Implementation.................................. 10
6 Specifications.................................................................. 4 9.1 Application Information............................................. 10
6.1 Absolute Maximum Ratings........................................ 4 9.2 Typical Power Button Circuit..................................... 10
6.2 ESD Ratings............................................................... 4 10 Power Supply Recommendations..............................11
6.3 Recommended Operating Conditions.........................5 11 Layout........................................................................... 12
6.4 Thermal Information....................................................5 11.1 Layout Guidelines................................................... 12
6.5 Electrical Characteristics.............................................6 11.2 Layout Example...................................................... 12
6.6 Timing Requirements, –40°C to +85°C.......................6 12 Device and Documentation Support..........................13
6.7 Timing Requirements, –40°C to +125°C.....................6 12.1 Receiving Notification of Documentation Updates..13
6.8 Switching Characteristics, –40°C to +85°C.................7 12.2 Support Resources................................................. 13
6.9 Switching Characteristics, –40°C to +125°C...............7 12.3 Trademarks............................................................. 13
6.10 Operating Characteristics......................................... 7 12.4 Electrostatic Discharge Caution..............................13
6.11 Typical Characteristics.............................................. 7 12.5 Glossary..................................................................13
7 Parameter Measurement Information............................ 8 13 Mechanical, Packaging, and Orderable
8 Detailed Description........................................................9 Information.................................................................... 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (July 2016) to Revision Q (September 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Application and Information section............................................................................................. 10
• Updated the Device Power Button Circuit figure in the Typical Power Button Circuit section.......................... 10

Changes from Revision O (January 2015) to Revision P (July 2016) Page

• Changed SSOP to SM8 in Device Information table.......................................................................................... 1
• Updated pinout images to new format................................................................................................................ 3
• Added pin number for DSBGA package in Pin Functions table..........................................................................3
• Changed 6 PINS to 8 PINS in Thermal Information table...................................................................................5
• Changed 23 to 2.3 for tsu data in Timing Requirements, –40°C to +125°C ....................................................... 6

Changes from Revision N (July 2013) to Revision O (January 2015) Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1

Changes from Revision M (February 2007) to Revision N (July 2013) Page

• Changed Ioff description in Features...................................................................................................................1
• Added parameter values for –40 to +125°C temperature ratings in Electrical Characteristics table.................. 6
• Changed Timing Requirements, –40°C to +85°C table...................................................................................... 6
• Added Timing Requirements, –40°C to +125°C table........................................................................................ 6
• Changed Switching Characteristics, –40°C to +85°C table................................................................................ 7
• Added Switching Characteristics, –40°C to +125°C table.................................................................................. 7

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5 Pin Configuration and Functions

DCT PACKAGE DCU PACKAGE
(TOP VIEW) (TOP VIEW)

CLK 1 8 VCC
CLK 1 8 VCC
D 2 7 PRE
D 2 7 PRE Q 3 6 CLR
Q GND 4 5 Q
3 6 CLR

GND 4 5 Q

See mechanical drawings for dimensions.

Figure 5-1. DCT 8-Pin SM8 and DCU 8-Pin VSSOP Package Top View

See mecahnical drawings for dimensions.

Figure 5-2. YZP Package 8-Pin DSBGA Bottom View

Table 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME VSSOP, SM8 DSBGA
CLK 1 A1 I Clock input
CLR 6 C2 I Clear input – Pull low to set Q output low
D 2 B1 I Input
GND 4 D1 — Ground
PRE 7 B2 I Preset input – Pull low to set Q output high
Q 5 D2 O Output
Q 3 C1 O Inverted output
VCC 8 A2 — Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VI Input voltage(2) –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state(2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in Section 6.3 table.

6.2 ESD Ratings

PARAMETER DEFINITION VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000 V
V(ESD)
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

6.4 Thermal Information

SN74LVC2G74
THERMAL METRIC(1) DCT DCU YZP UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance(2) 220 227 102 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to +125°C
–40°C to +85°C
PARAMETER TEST CONDITIONS VCC Recommended UNIT
MIN TYP(1) MAX MIN TYP MAX
IOH = –100 μA 1.65 V to 5.5 V VCC – 0.1 VCC – 0.1
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.85
VOH V
IOH = –16 mA 2.4 2.4
3V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
Data or
II VI = 5.5 V or GND 0 to 5.5 V ±5 ±5 μA
control inputs
Ioff VI or VO = 5.5 V 0 ±10 ±10 μA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 μA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 500 μA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3 V 5 5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Timing Requirements, –40°C to +85°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
–40°C to +85°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER FROM TO UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock 80 175 175 200 MHz
CLK 6.2 2.7 2.7 2
tw ns
PRE or CLR low 6.2 2.7 2.7 2
Data 2.9 1.7 1.3 1.1
tsu ns
PRE or CLR inactive 1.9 1.4 1.2 1
th 0 0.3 1.2 0.5 ns

6.7 Timing Requirements, –40°C to +125°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
–40°C to +125°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER FROM TO UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock 80 120 120 140 MHz
CLK 6.2 3.5 3.5 3.3
tw ns
PRE or CLR low 6.2 3.5 3.5 3.3
Data 2.9 2.3 1.9 1.7
tsu ns
PRE or CLR inactive 1.9 2 1.8 1.6
th 0 0.3 0.5 0.5 ns

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6.8 Switching Characteristics, –40°C to +85°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
–40°C to +85°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER FROM TO UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 80 175 175 200 MHz
Q 4.8 13.4 2.2 7.1 2.2 5.9 1.4 4.1
CLK
tpd Q 6 14.4 3 7.7 2.6 6.2 1.6 4.4 ns
PRE or CLR low Q or Q 4.4 12.9 2.3 7 1.7 5.9 1.6 4.1

6.9 Switching Characteristics, –40°C to +125°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
–40°C to +125°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER FROM TO UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 80 120 120 140 MHz
Q 4.8 14.4 2.2 8.1 2.2 6.9 1.4 5.1
CLK
tpd Q 6 16 3 9.7 2.6 7.2 1.6 5.4 ns
PRE or CLR low Q or Q 4.4 14.9 2.3 9.5 1.7 7.9 1.6 6.1

6.10 Operating Characteristics

TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 35 35 37 40 pF

6.11 Typical Characteristics

14 10
VCC = 3 V, VCC = 3 V,
TA = 25°C TA = 25°C
12
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns

One Output Switching One Output Switching

8
10

8 6

6
4
4

2 2
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 6-1. Propagation Delay (Low to High Transition) Figure 6-2. Propagation Delay (High to Low Transition)
vs Load Capacitance vs Load Capacitance

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description
8.1 Overview
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
7
PRE

1 C
CLK C

C
5
Q
TG

C C C

2
D TG TG TG

3
Q
C C C
6
CLR

8.3 Feature Description

• Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
• Inputs accept voltage levels up to 5.5 V
• Ioff Feature
– Can prevent backflow current that can damage device when powered down.
8.4 Device Functional Modes
Table 8-1 shows the functional modes of SN74LVC2G74.
Table 8-1. Function Table
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H(1) H(1)
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0

(1) This configuration is non-stable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
The 330 Ω resistor and 22 pF capacitor shown in Figure 9-1 produce enough delay to meet the hold time
requirement of the D input. To calculate the delay for a particular RC combination, use Equation 1. The delay
with this RC combination is 5.03 ns

tdelay = −RC ln(0.5) ≈ 0.693 RC (1)

To ensure proper operation, check that the transition time of the RC circuit meets the transition time
requirements of the device inputs listed in the Recommended Operating Conditions table. Transition time for
an RC can be approximated with Equation 2.

tt≈ 2.2 RC (2)

In this case, transition time is 18.15 ns, which equates to a 4.54 ns / V input transition rate at VCC = 5 V, and is
below the 5 ns / V maximum requirement for recommended operation.
9.2 Typical Power Button Circuit
VCC
VCC

VCC 0.1 F
0.1 F
10 k
1A 1Y
CLK VCC
1
F VCC D PRE
330 
Q CLR
22 pF
20 k GND Q MCU
2A 2Y

1 F
SN74LVC2G17

Figure 9-1. Device Power Button Circuit

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9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads so routing and load
conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
• For rise time and fall time specifications, see (Δt/ΔV) in the Recommended Operating Conditions table.
• For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend Output Conditions:
• Load currents should not exceed 50 mA per output and 100 mA total for the part.
• Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
9.2.3 Application Curves

60 100
TA = 25°C, VCC = 3 V, TA = 25°C, VCC = 3 V,
40 VIH = 3 V, VIL = 0 V, VIH = 3 V, VIL = 0 V,
All Outputs Switching 80 All Outputs Switching
20
60
0
I OL – mA
I OH – mA

–20 40

–40
20
–60
0
–80

–100 –20
–1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VOH – V VOL – V
Figure 9-2. Output Current Drive Figure 9-3. Output Current Drive
vs HIGH-Level Output Voltage vs LOW-Level Output Voltage

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple
VCC terminals then .01-μF or .022-μF capacitors are recommended for each power terminal. It is acceptable
to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are
commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible
for best results.

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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part
when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 11-1. Layout Diagram

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
NanoFree™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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Product Folder Links: SN74LVC2G74
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Jul-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC2G74DCT3 ACTIVE SM8 DCT 8 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 C74
Non-Green Z
SN74LVC2G74DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C74
Z
SN74LVC2G74DCTRE4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C74
Z
SN74LVC2G74DCTRE6 ACTIVE SM8 DCT 8 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 C74
Non-Green Z
SN74LVC2G74DCTRG4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C74
Z
SN74LVC2G74DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (74, C74J, C74Q, C
74R)
CZ
SN74LVC2G74DCURE4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C74R

SN74LVC2G74DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C74R

SN74LVC2G74DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C74J, C74Q, C74R)

SN74LVC2G74DCUTE4 ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C74R

SN74LVC2G74DCUTG4 ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C74R

SN74LVC2G74YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 CPN

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Jul-2021

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC2G74 :

• Automotive : SN74LVC2G74-Q1
• Enhanced Product : SN74LVC2G74-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC2G74DCT3 SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74LVC2G74DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74LVC2G74DCTRE6 SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74LVC2G74DCUR VSSOP DCU 8 3000 178.0 9.0 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G74DCUR VSSOP DCU 8 3000 180.0 9.0 2.25 3.4 1.0 4.0 8.0 Q3
SN74LVC2G74DCURG4 VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G74DCUT VSSOP DCU 8 250 178.0 9.0 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G74DCUTG4 VSSOP DCU 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G74YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jul-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC2G74DCT3 SM8 DCT 8 3000 182.0 182.0 20.0
SN74LVC2G74DCTR SM8 DCT 8 3000 182.0 182.0 20.0
SN74LVC2G74DCTRE6 SM8 DCT 8 3000 182.0 182.0 20.0
SN74LVC2G74DCUR VSSOP DCU 8 3000 180.0 180.0 18.0
SN74LVC2G74DCUR VSSOP DCU 8 3000 182.0 182.0 20.0
SN74LVC2G74DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0
SN74LVC2G74DCUT VSSOP DCU 8 250 180.0 180.0 18.0
SN74LVC2G74DCUTG4 VSSOP DCU 8 250 202.0 201.0 28.0
SN74LVC2G74YZPR DSBGA YZP 8 3000 220.0 220.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DCU0008A SCALE 6.000
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE

3.2
TYP C
3.0
A
0.1 C
PIN 1 INDEX AREA SEATING
6X 0.5 PLANE
8
1

2X
2.1
1.5
1.9
NOTE 3

4
5
0.25
8X
0.17
2.4
B 0.08 C A B
2.2
NOTE 3

SEE DETAIL A

0.12 0.9
GAGE PLANE 0.6

0.1
0 -6 0.35 0.0
(0.13) TYP
0.20

DETAIL A
A 30

TYPICAL

4225266/A 09/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DCU0008A VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE

SEE SOLDER MASK

8X (0.85) SYMM DETAILS

(R0.05) TYP

8X (0.3) 1 8

SYMM
6X (0.5)

4 5

(3.1)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 25X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225266/A 09/2014
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCU0008A VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE

8X (0.85)
SYMM
(R0.05) TYP

8X (0.3) 1 8

SYMM
6X (0.5)

4 5

(3.1)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 25X

4225266/A 09/2014
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DCT0008A SCALE 3.500
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE

C
4.25
TYP
3.75 SEATING PLANE
A PIN 1 ID
AREA 0.1 C

6X 0.65
8
1

3.15 2X
2.75 1.95
NOTE 3

4
5
0.30
8X
0.15
2.9 0.13 C A B 1.3
B
2.7 1.0
NOTE 4

SEE DETAIL A (0.15) TYP

0.25
GAGE PLANE

0.1
0 -8 0.6 0.0
0.2

DETAIL A
TYPICAL

4220784/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DCT0008A SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE

8X (1.1)
SYMM
(R0.05)
1 TYP
8

8X (0.4)
SYMM

6X (0.65)
5
4

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220784/C 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCT0008A SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE

8X (1.1) SYMM
1
8

8X (0.4)
SYMM

6X (0.65)
5
4

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4220784/C 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
YZP0008 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX

SEATING PLANE
0.19
0.15 0.05 C
BALL TYP

0.5 TYP

C
SYMM
1.5
TYP
D: Max = 1.919 mm, Min =1.858 mm
B
E: Max = 0.918 mm, Min =0.857 mm
0.5
TYP
A

0.25
8X 1 2
0.21
0.015 C A B
SYMM

4223082/A 07/2016
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0008 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
8X ( 0.23)
1 2

(0.5) TYP

B
SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING

( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223082/A 07/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0008 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

8X ( 0.25)
(R0.05) TYP
1 2

(0.5)
TYP

B
SYMM

METAL
TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4223082/A 07/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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