SN74LV1T08

SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022

SN74LV1T08 Single Power Supply 2-Input Positive AND Gate CMOS Logic Level
Shifter
• Latch-up performance exceeds 250 mA Per
1 Features JESD 17
• Single-supply voltage translator at 5.0-V, 3.3-V, • Supports standard logic pinouts
2.5-V, and 1.8-V VCC • CMOS output B compatible with AUP1G and
• Operating range of 1.8 V to 5.5 V LVC1G families 1
• Up translation:
2 Applications
– 1.2 V(1) to 1.8 V at 1.8-V VCC
– 1.5 V(1) to 2.5 V at 2.5-V VCC • Telecom
– 1.8 V(1) to 3.3 V at 3.3-V VCC • Portable applications
– 3.3 V to 5.0 V at 5.0-V VCC • Servers
• Down translation: • PC and notebooks
– 3.3 V to 1.8 V at 1.8-V VCC 3 Description
– 3.3 V to 2.5 V at 2.5-V VCC
– 5.0 V to 3.3 V at 3.3-V VCC The SN74LV1T08 is a single 2-input AND gate
• Logic output is referenced to VCC with reduced input thresholds to support voltage
• Output drive: translation applications.
– 8 mA Output Drive at 5 V Device Information
– 7 mA Output Drive at 3.3 V PART NUMBER (1) PACKAGE BODY SIZE (NOM)
– 3 mA Output Drive at 1.8 V DBV (SOT-23, 5) 2.90 mm × 1.60 mm
• Characterized up to 50 MHz at 3.3-V VCC SN74LV1T08
DCK (SC70, 5) 2.00 mm × 1.25 mm
• 5 V tolerance on input pins
• –40°C to 125°C operating temperature range (1) For all available packages, see the orderable addendum at
• Pb-free packages available: SC-70 (DCK) the end of the data sheet.
– 2 × 2.1 × 0.65 mm (height 1.1 mm)
Vcc = 3.3V

5.0V, 3.3V
3.3V
2.5V, 1.8V
System
LV1Txx Logic System

VOH min = 2.4V

VIH min = 1.36V

VIL min = 0.8V VOL max = 0.4V

Switching Thresholds for 1.8-V to 3.3-V Translation

1 Refer to the VIH/VIL and output drive for lower VCC condition.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 9 Detailed Description......................................................10
2 Applications..................................................................... 1 9.1 Overview................................................................... 10
3 Description.......................................................................1 9.2 Functional Block Diagram......................................... 10
4 Revision History.............................................................. 2 9.3 Feature Description...................................................10
5 Related Products............................................................. 3 9.4 Device Functional Modes..........................................12
6 Pin Configuration and Functions...................................4 10 Power Supply Recommendations..............................13
7 Specifications.................................................................. 5 11 Layout........................................................................... 13
7.1 Absolute Maximum Ratings........................................ 5 11.1 Layout Guidelines................................................... 13
7.2 ESD Ratings............................................................... 5 12 Device and Documentation Support..........................14
7.3 Recommended Operating Conditions.........................6 12.1 Receiving Notification of Documentation Updates..14
7.4 Thermal Information....................................................6 12.2 Support Resources................................................. 14
7.5 Electrical Characteristics.............................................6 12.3 Trademarks............................................................. 14
7.6 Switching Characteristics............................................7 12.4 Electrostatic Discharge Caution..............................14
7.7 Operating Characteristics........................................... 8 12.5 Glossary..................................................................14
7.8 Typical Characteristics................................................ 8 13 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information............................ 9 Information.................................................................... 14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2014) to Revision C (June 2022) Page
• Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Pin Configuration and
Functions section, Detailed Description section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Receiving Notification of Documentation Updates section, and
Community Resources section........................................................................................................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added Thermal Information table....................................................................................................................... 6
• Added Typical Characteristics............................................................................................................................ 8

Changes from Revision A (September 2013) to Revision B (February 2014) Page

• Updated document formatting. .......................................................................................................................... 1
• Updated document formatting............................................................................................................................ 1
• Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Pin Configuration and
Functions section, Detailed Description section, Power Supply Recommendations section, Layout section,
Receiving Notification of Documentation Updates section, and Community Resources section....................... 5
• Updated Electrical characteristics table..............................................................................................................6
• Removed Ioh test condition for Voh parameter ................................................................................................... 6
• Removed Ioh = -2.3mA for Vol parameter ...........................................................................................................6

Changes from Revision * (September 2013) to Revision A (September 2013) Page

• Updated VCC values for VIH parameter in the Electrical Characteristics table....................................................6

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5 Related Products
DEVICE PACKAGE DESCRIPTION
SN74LV1T00 DCK, DBV 2-Input Positive-NAND Gate
SN74LV1T02 DCK, DBV 2-Input Positive-NOR Gate
SN74LV1T04 DCK, DBV Inverter Gate
SN74LV1T08 DCK, DBV 2-Input Positive-AND Gate
SN74LV1T17 DCK, DBV Single Schmitt-Trigger Buffer Gate
SN74LV1T14 DCK, DBV Single Schmitt-Trigger Inverter Gate
SN74LV1T32 DCK, DBV 2-Input Positive-OR Gate
SN74LV1T34 DCK, DBV Single Buffer Gate
SN74LV1T86 DCK, DBV Single 2-Input Exclusive-Or Gate
SN74LV1T125 DCK, DBV Single Buffer Gate with 3-state Output
SN74LV1T126 DCK, DBV Single Buffer Gate with 3-state Output
SN74LV4T125 RGY, PW Quadruple Bus Buffer Gate With 3-State Outputs

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6 Pin Configuration and Functions

A 1 5 VCC

B 2

GND 3 4 Y

Figure 6-1. DCK or DBV Package, 5-Pin SC70 or SOT-23 (Top View)

Table 6-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
A 1 I Input A
B 2 I Input B
GND 3 G Ground
Y 4 O Output Y
VCC 5 P Positive supply

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7.0 V
VI Input voltage range(2) –0.5 7.0 V
Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V
VO
Voltage range applied to any output in the high or low state(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Machine Model (MM), per JEDEC specification ±200 V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage 1.6 5.5 V
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.8 V –3
VCC = 2.5 V –5
IOH High-level output current mA
VCC = 3.3 V –7
VCC = 5.0 V –8
VCC = 1.8 V 3
VCC = 2.5 V 5
IOL Low-level output current mA
VCC = 3.3 V 7
VCC = 5.0 V 8
VCC = 1.8 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V or 2.5 V 20 ns/V
VCC = 5.0 V 20
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4 Thermal Information

DBV DCK
THERMAL METRIC(1) UNIT
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 206 252 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C TA = –40°C to +125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN TYP MAX
VCC = 1.65 V to 1.8 V 0.94 1.0
VCC = 2.0 V 1.02 1.03
VCC = 2.25 V to 2.5 V 1.135 1.18

High-level VCC = 2.75 V 1.21 1.23

VIH V
input voltage VCC = 3 V to 3.3 V 1.35 1.37
VCC = 3.6 V 1.47 1.48
VCC = 4.5 V to 5.0 V 2.02 2.03
VCC = 5.5 V 2.1 2.11
VCC = 1.65 V to 2.0 V 0.58 0.55

Low-level VCC = 2.25 V to 2.75 V 0.75 0.71

VIL V
input voltage VCC = 3 V to 3.6 V 0.8 0.65
VCC = 4.5 V to 5.5 V 0.8 0.8

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over recommended operating free-air temperature range (unless otherwise noted)

TA = 25°C TA = –40°C to +125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN TYP MAX
IOH = –20 µA 1.65 V to 5.5 V VCC – 0.1 VCC – 0.1
1.65 V 1.28 1.21
IOH = –2.0 mA
1.8 V 1.5 1.45
IOH = –2.3 mA 2.0 2.0
2.3 V
IOH = –3 mA 2.0 1.93
High-level IOH = –3 mA 2.5 V 2.25 2.15
VOH output V
voltage IOH = –3.0 mA 2.78 2.7
3.0 V
IOH = –5.5 mA 2.6 2.49
IOH = –5.5 mA 3.3 V 2.9 2.8
IOH = –4 mA 4.2 4.1
4.5 V
IOH = –8 mA 4.1 3.95
IOH = –8 mA 5.0 V 4.6 4.5
IOL = 20 µA 1.65 V to 5.5 V 0.1 0.1
IOL = 1.9 mA 1.65 V 0.2 0.25
IOL =2.3 mA 0.1 0.15
2.3 V
Low-level IOL = 3 mA 0.15 0.2
VOL output V
voltage IOL = 3 mA 0.1 0.15
3.0 V
IOL = 5.5 mA 0.2 0.252
IOL = 4 mA 0.15 0.2
4.5 V
IOL = 8 mA 0.3 0.35
Input
0 V, 1.8 V, 2.5 V,
II leakage A input; VI = 0 V or VCC 0.12 ±1 μA
3.3 V, 5.5 V
current
5.0 V 1 10

Static supply VI = 0 V or VCC, 3.3 V 1 10

ICC μA
current IO = 0; open on loading 2.5 V 1 10
1.8 V 1 10
One input at 0.3 V or 3.4 V,
Other inputs at 0 or VCC, 5.5 V 1.35 1.5 mA
Additional IO = 0
ΔICC static supply
current One input at 0.3 V or 1.1 V
Other inputs at 0 or VCC, 1.8 V 10 10 μA
IO = 0
Input
Ci VI = VCC or GND 3.3 V 2 10 2 10 pF
capacitance
Output
Co VO = VCC or GND 3.3 V 2.5 2.5 pF
capacitance

7.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Parameter Measurement Information)
FROM TO FREQUENCY TA = 25°C TA = –65°C to 125°C
PARAMETER VCC CL UNIT
(INPUT) (OUTPUT) (TYP) MIN TYP MAX MIN TYP MAX
15 pF 4 5 4 5
5.0 V ns
30 pF 5.5 7.0 5.5 7.0
DC to 50 MHz
15 pF 4.8 5 5 5.5
3.3 V ns
30 pF 5 5.5 5.5 6.5
tpd Any In Y
15 pF 6 6.5 7 7.5
DC to 25 MHz 2.5 V ns
30 pF 6.5 7.5 7.5 8.5
15 pF 10.5 11 11 12
DC to 15 MHz 1.8 V ns
30 pF 12 13 12 14

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7.7 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
1.8 V ± 0.15 V 10
2.5 V ± 0.2 V 10
Cpd Power dissipation capacitance f = 1 MHz and 10 MHz pF
3.3 V ± 0.3 V 10
5.5 V ± 0.5 V 10

7.8 Typical Characteristics

Figure 7-2. Excellent Signal Integrity

Figure 7-1. Excellent Signal Integrity (3.3 V to 3.3 V at 3.3-V VCC)
(1.8 V to 3.3 V at 3.3-V VCC)

Figure 7-3. Excellent Signal Integrity

(3.3 V to 1.8 V at 1.8-V VCC)

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8 Parameter Measurement Information

From Output
Under Test VCC = 2.5 V VCC = 3.3 V
CL ± 0.2 V ± 0.3 V
1 MΩ
(see Note A) CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF
VMI VI/2 VI/2
VMO VCC/2 VCC/2

LOAD CIRCUIT

VI
Input VMI VMI
0V

tPLH tPHL
VOH
Output VMO VMo
VOL
tPHL tPLH

VOH
Output VMo VMo
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.

Figure 8-1. Load Circuit and Voltage Waveforms

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9 Detailed Description
9.1 Overview
The SN74LV1T08 device is a low-voltage CMOS gate logic that operates at a wider voltage range for industrial,
portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able
to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to
match 1.8 V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the
5 V tolerant input pins enable down translation (that is, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC
range of 1.8 V to 5.5 V allows generation of desired output levels to connect to controllers or processors. The
SN74LV1T08 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and
undershoot caused by high-drive outputs.
9.2 Functional Block Diagram
1
A 4
2 Y
B
Figure 9-1. Logic Diagram

9.3 Feature Description

9.3.1 Clamp Diode Structure
The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have
negative clamping diodes only as depicted in Figure 9-2.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

VCC
Device

+IOK

Input Logic Output

-IIK -IOK

GND

Figure 9-2. Electrical Placement of Clamping Diodes for Each Input and Output

9.3.2 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.

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9.3.3 LVxT Enhanced Input Voltage

The SN74LV1T08 belongs to TI's LVxT family of Logic devices with integrated voltage level translation. This
family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs
tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be
referenced to the supply voltage (VCC), as described in the Electrical Characteristics table. To ensure proper
functionality, input signals must remain at or below the specified VIH(MIN) level for a HIGH input state, and at or
below the specified VIL(MAX) for a LOW input state. Figure 9-3 shows the typical VIH and VIL levels for the LVxT
family of devices, as well as the voltage levels for standard CMOS devices for comparison.
The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance
given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage,
given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical
Characteristics, using Ohm's law (R = V ÷ I).
The inputs require that input signals transition between valid logic states quickly, as defined by the input
transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification
will result in excessive power consumption and could cause oscillations. More details can be found in the
Implications of Slow or Floating CMOS Inputs application report.
Do not leave inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If
a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide
a valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ
resistor is recommended and will typically meet all requirements.

3.6

3.4 3.3-V CMOS

3.2
VIH
3 VIL
2.8 HIGH Input
LOW Input
2.6 2.5-V CMOS
2.4 2.4 V (VOH)
2.2

2
VIN - Input Voltage (V)

2 V (VOH)
1.8-V CMOS
1.8

1.6

1.4 1.45 V (VOH)

1.2 1.2-V CMOS

1.1 V (VOH)
1

0.8

0.6

0.4 0.45 V (VOL)

0.4 V (VOL) 0.4 V (VOL)
0.3 V (VOL)
0.2

0
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.5

VCC - Supply Voltage (V)

Figure 9-3. LVxT Input Voltage Levels

9.3.3.1 Down Translation

Signals can be translated down using the SN74LV1T08. The voltage applied at the VCC will determine the
output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and
0 V in the LOW state. Ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input
signals in the LOW state are lower than VIL(MAX) as shown in Figure 9-3.
For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to
match 1.8 V CMOS signals when operating from 1.8-V VCC. See Figure 9-4.

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Down Translation Combinations:

• 1.8-V VCC – Inputs from 2.5 V, 3.3 V, and 5.0 V
• 2.5-V VCC – Inputs from 3.3 V and 5.0 V
• 3.3-V VCC – Inputs from 5.0 V
9.3.3.2 Up Translation
Input signals can be up translated using the SN74LV1T08. The voltage applied at VCC will determine the
output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC
in the HIGH state, and 0 V in the LOW state.
The inputs have reduced thresholds that allow for input high-state levels which are much lower than standard
values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V.
For the SN74LV1T08, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical
2.5-V to 5-V signals.
Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower
than VIL(MAX) as shown in Figure 9-4.
Up Translation Combinations:
• 1.8-V VCC – Inputs from 1.2 V
• 2.5-V VCC – Inputs from 1.8 V
• 3.3-V VCC – Inputs from 1.8 V and 2.5 V
• 5.0-V VCC – Inputs from 2.5 V and 3.3 V
VIH = 2.0 V Vcc = 5.0 V VIH = 0.99 V Vcc = 1.8 V
VIL = 0.8 V VIL = 0.5 V

5.0 V, 3.3 V
5.0 V
5.0 V 2.5 V, 1.8 V 1.8 V
3.3 V LV1Txx Logic System 1.5 V, 1.2 V
LV1Txx Logic System
System
System

Figure 9-4. LVxT Up and Down Translation Example

9.4 Device Functional Modes

Function Table
INPUT(1) OUTPUT(2)
(LOWER LEVEL INPUT) (VCC CMOS)
A B Y
H H H
L X L
X L L
SUPPLY VCC = 3.3 V
A B Y
VIH(min) = 1.35 V VOH(min) = 2.9 V
VIL(max) = 0.08 V VOL(max) = 0.2 V

(1) H = High Voltage Level, L = Low Voltage Level, X = Do not

Care, Z = High Impedance
(2) H = Driving High, L = Driving Low, Z = High Impedance State

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the
following layout example.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: SN74LV1T08

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LV1T08DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (NEE3, NEEJ, NEES)

SN74LV1T08DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NEE3

SN74LV1T08DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (WE3, WEJ, WES)

SN74LV1T08DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM WE3

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Oct-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV1T08DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LV1T08DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LV1T08DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LV1T08DBVRG4 SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LV1T08DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LV1T08DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LV1T08DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LV1T08DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Oct-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV1T08DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LV1T08DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74LV1T08DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LV1T08DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LV1T08DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74LV1T08DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LV1T08DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LV1T08DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.

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 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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